usr/src/uts/intel/sys/controlregs.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
  23  * Copyright 2015, Joyent, Inc.
  24  *
  25  * Copyright 2018 Joyent, Inc.
  26  */
  27
  28 #ifndef _SYS_CONTROLREGS_H
  29 #define _SYS_CONTROLREGS_H
  30
  31 #ifndef _ASM
  32 #include <sys/types.h>
  33 #endif
  34
  35 #ifdef __cplusplus
  36 extern "C" {
  37 #endif
  38
  39 /*
  40  * This file describes the x86 architecture control registers which
  41  * are part of the privileged architecture.
  42  *
  43  * Many of these definitions are shared between IA-32-style and
  44  * AMD64-style processors.
  45  */
  46
  47 /* CR0 Register */
  48
  49 #define CR0_PG  0x80000000              /* paging enabled       */
  50 #define CR0_CD  0x40000000              /* cache disable        */
  51 #define CR0_NW  0x20000000              /* not writethrough     */
  52 #define CR0_AM  0x00040000              /* alignment mask       */
  53 #define CR0_WP  0x00010000              /* write protect        */
  54 #define CR0_NE  0x00000020              /* numeric error        */
  55 #define CR0_ET  0x00000010              /* extension type       */
  56 #define CR0_TS  0x00000008              /* task switch          */
  57 #define CR0_EM  0x00000004              /* emulation            */
  58 #define CR0_MP  0x00000002              /* monitor coprocessor  */
  59 #define CR0_PE  0x00000001              /* protection enabled   */
  60
  61 /* XX64 eliminate these compatibility defines */
  62
  63 #define CR0_CE  CR0_CD
  64 #define CR0_WT  CR0_NW
  65
  66 #define FMT_CR0 \
  67         "\20\40pg\37cd\36nw\35am\21wp\6ne\5et\4ts\3em\2mp\1pe"
  68
  69 /*
  70  * Set the FPU-related control bits to explain to the processor that
  71  * we're managing FPU state:
  72  * - set monitor coprocessor (allow TS bit to control FPU)
  73  * - set numeric exception (disable IGNNE# mechanism)
  74  * - set task switch (#nm on first fp instruction)
  75  * - clear emulate math bit (cause we're not emulating!)
  76  */
  77 #define CR0_ENABLE_FPU_FLAGS(cr)        \
  78         (((cr) | CR0_MP | CR0_NE | CR0_TS) & (uint32_t)~CR0_EM)
  79
  80 /*
  81  * Set the FPU-related control bits to explain to the processor that
  82  * we're -not- managing FPU state:
  83  * - set emulate (all fp instructions cause #nm)
  84  * - clear monitor coprocessor (so fwait/wait doesn't #nm)
  85  */
  86 #define CR0_DISABLE_FPU_FLAGS(cr)       \
  87         (((cr) | CR0_EM) & (uint32_t)~CR0_MP)
  88
  89 /* CR3 Register */
  90
  91 #define CR3_PCD 0x00000010              /* cache disable                */
  92 #define CR3_PWT 0x00000008              /* write through                */
  93
  94 #define FMT_CR3 "\20\5pcd\4pwt"
  95
  96 /* CR4 Register */
  97
  98 #define CR4_VME         0x0001          /* virtual-8086 mode extensions */
  99 #define CR4_PVI         0x0002          /* protected-mode virtual interrupts */
 100 #define CR4_TSD         0x0004          /* time stamp disable           */
 101 #define CR4_DE          0x0008          /* debugging extensions         */
 102 #define CR4_PSE         0x0010          /* page size extensions         */
 103 #define CR4_PAE         0x0020          /* physical address extension   */
 104 #define CR4_MCE         0x0040          /* machine check enable         */
 105 #define CR4_PGE         0x0080          /* page global enable           */
 106 #define CR4_PCE         0x0100          /* perf-monitoring counter enable */
 107 #define CR4_OSFXSR      0x0200          /* OS fxsave/fxrstor support    */
 108 #define CR4_OSXMMEXCPT  0x0400          /* OS unmasked exception support */
 109                                         /* 0x0800 reserved */
 110                                         /* 0x1000 reserved */
 111 #define CR4_VMXE        0x2000
 112 #define CR4_SMXE        0x4000
 113 #define CR4_PCIDE       0x20000         /* PCID enable */
 114 #define CR4_OSXSAVE     0x40000         /* OS xsave/xrestore support    */
 115 #define CR4_SMEP        0x100000        /* NX for user pages in kernel */
 116 #define CR4_SMAP        0x200000        /* kernel can't access user pages */
 117
 118 #define FMT_CR4                                         \
 119         "\20\26smap\25smep\23osxsav\22pcide"            \
 120         "\17smxe\16vmxe\13xmme\12fxsr\11pce\10pge"      \
 121         "\7mce\6pae\5pse\4de\3tsd\2pvi\1vme"
 122
 123 /*
 124  * Enable the SSE-related control bits to explain to the processor that
 125  * we're managing XMM state and exceptions
 126  */
 127 #define CR4_ENABLE_SSE_FLAGS(cr)        \
 128         ((cr) | CR4_OSFXSR | CR4_OSXMMEXCPT)
 129
 130 /*
 131  * Disable the SSE-related control bits to explain to the processor
 132  * that we're NOT managing XMM state
 133  */
 134 #define CR4_DISABLE_SSE_FLAGS(cr)       \
 135         ((cr) & ~(uint32_t)(CR4_OSFXSR | CR4_OSXMMEXCPT))
 136
 137 /* Intel's SYSENTER configuration registers */
 138
 139 #define MSR_INTC_SEP_CS 0x174           /* kernel code selector MSR */
 140 #define MSR_INTC_SEP_ESP 0x175          /* kernel esp MSR */
 141 #define MSR_INTC_SEP_EIP 0x176          /* kernel eip MSR */
 142
 143 /* Intel's microcode registers */
 144 #define MSR_INTC_UCODE_WRITE            0x79    /* microcode write */
 145 #define MSR_INTC_UCODE_REV              0x8b    /* microcode revision */
 146 #define INTC_UCODE_REV_SHIFT            32      /* Bits 63:32 */
 147
 148 /* Intel's platform identification */
 149 #define MSR_INTC_PLATFORM_ID            0x17
 150 #define INTC_PLATFORM_ID_SHIFT          50      /* Bit 52:50 */
 151 #define INTC_PLATFORM_ID_MASK           0x7
 152
 153 /* AMD's EFER register */
 154
 155 #define MSR_AMD_EFER    0xc0000080      /* extended feature enable MSR */
 156
 157 #define AMD_EFER_FFXSR  0x4000          /* fast fxsave/fxrstor          */
 158 #define AMD_EFER_SVME   0x1000          /* svm enable                   */
 159 #define AMD_EFER_NXE    0x0800          /* no-execute enable            */
 160 #define AMD_EFER_LMA    0x0400          /* long mode active (read-only) */
 161 #define AMD_EFER_LME    0x0100          /* long mode enable             */
 162 #define AMD_EFER_SCE    0x0001          /* system call extensions       */
 163
 164 #define FMT_AMD_EFER \
 165         "\20\17ffxsr\15svme\14nxe\13lma\11lme\1sce"
 166
 167 /* AMD's SYSCFG register */
 168
 169 #define MSR_AMD_SYSCFG  0xc0000010      /* system configuration MSR */
 170
 171 #define AMD_SYSCFG_TOM2 0x200000        /* MtrrTom2En */
 172 #define AMD_SYSCFG_MVDM 0x100000        /* MtrrVarDramEn */
 173 #define AMD_SYSCFG_MFDM 0x080000        /* MtrrFixDramModEn */
 174 #define AMD_SYSCFG_MFDE 0x040000        /* MtrrFixDramEn */
 175
 176 #define FMT_AMD_SYSCFG \
 177         "\20\26tom2\25mvdm\24mfdm\23mfde"
 178
 179 /* AMD's syscall/sysret MSRs */
 180
 181 #define MSR_AMD_STAR    0xc0000081      /* %cs:%ss:%cs:%ss:%eip for syscall */
 182 #define MSR_AMD_LSTAR   0xc0000082      /* target %rip of 64-bit syscall */
 183 #define MSR_AMD_CSTAR   0xc0000083      /* target %rip of 32-bit syscall */
 184 #define MSR_AMD_SFMASK  0xc0000084      /* syscall flag mask */
 185
 186 /* AMD's FS.base and GS.base MSRs */
 187
 188 #define MSR_AMD_FSBASE  0xc0000100      /* 64-bit base address for %fs */
 189 #define MSR_AMD_GSBASE  0xc0000101      /* 64-bit base address for %gs */
 190 #define MSR_AMD_KGSBASE 0xc0000102      /* swapgs swaps this with gsbase */
 191 #define MSR_AMD_TSCAUX  0xc0000103      /* %ecx value on rdtscp insn */
 192
 193 /* AMD's configuration MSRs, weakly documented in the revision guide */
 194
 195 #define MSR_AMD_DC_CFG  0xc0011022
 196
 197 #define AMD_DC_CFG_DIS_CNV_WC_SSO       (UINT64_C(1) << 3)
 198 #define AMD_DC_CFG_DIS_SMC_CHK_BUF      (UINT64_C(1) << 10)
 199
 200 /* AMD's HWCR MSR */
 201
 202 #define MSR_AMD_HWCR    0xc0010015
 203
 204 #define AMD_HWCR_TLBCACHEDIS            (UINT64_C(1) << 3)
 205 #define AMD_HWCR_FFDIS                  0x00040 /* disable TLB Flush Filter */
 206 #define AMD_HWCR_MCI_STATUS_WREN        0x40000 /* enable write of MCi_STATUS */
 207
 208 /* AMD's NorthBridge Config MSR, SHOULD ONLY BE WRITTEN TO BY BIOS */
 209
 210 #define MSR_AMD_NB_CFG  0xc001001f
 211
 212 #define AMD_NB_CFG_SRQ_HEARTBEAT        (UINT64_C(1) << 20)
 213 #define AMD_NB_CFG_SRQ_SPR              (UINT64_C(1) << 32)
 214
 215 #define MSR_AMD_BU_CFG  0xc0011023
 216
 217 #define AMD_BU_CFG_E298                 (UINT64_C(1) << 1)
 218
 219 #define MSR_AMD_DE_CFG  0xc0011029
 220
 221 #define AMD_DE_CFG_E721                 (UINT64_C(1))
 222
 223 /* AMD's osvw MSRs */
 224 #define MSR_AMD_OSVW_ID_LEN             0xc0010140
 225 #define MSR_AMD_OSVW_STATUS             0xc0010141
 226
 227
 228 #define OSVW_ID_LEN_MASK                0xffffULL
 229 #define OSVW_ID_CNT_PER_MSR             64
 230
 231 /*
 232  * Enable PCI Extended Configuration Space (ECS) on Greyhound
 233  */
 234 #define AMD_GH_NB_CFG_EN_ECS            (UINT64_C(1) << 46)
 235
 236 /* AMD microcode patch loader */
 237 #define MSR_AMD_PATCHLEVEL      0x8b
 238 #define MSR_AMD_PATCHLOADER     0xc0010020
 239
 240 #ifdef __cplusplus
 241 }
 242 #endif
 243
 244 #endif  /* !_SYS_CONTROLREGS_H */