4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
23 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
26 /* Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */
27 /* Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T */
28 /* All Rights Reserved */
30 /* Copyright (c) 1987, 1988 Microsoft Corporation */
31 /* All Rights Reserved */
35 * Copyright 2018 Joyent, Inc.
38 #include <sys/types.h>
39 #include <sys/sysmacros.h>
40 #include <sys/param.h>
41 #include <sys/signal.h>
42 #include <sys/systm.h>
46 #include <sys/class.h>
48 #include <sys/syscall.h>
49 #include <sys/cpuvar.h>
51 #include <sys/sysinfo.h>
52 #include <sys/fault.h>
53 #include <sys/stack.h>
55 #include <sys/regset.h>
59 #include <sys/vtrace.h>
60 #include <sys/cmn_err.h>
61 #include <sys/prsystm.h>
62 #include <sys/mutex_impl.h>
63 #include <sys/machsystm.h>
64 #include <sys/archsystm.h>
66 #include <sys/avintr.h>
71 #include <vm/seg_kmem.h>
74 #include <vm/hat_pte.h>
75 #include <vm/hat_i86.h>
77 #include <sys/procfs.h>
79 #include <sys/reboot.h>
80 #include <sys/debug.h>
81 #include <sys/debugreg.h>
82 #include <sys/modctl.h>
83 #include <sys/aio_impl.h>
85 #include <sys/tnf_probe.h>
88 #include <sys/x86_archext.h>
89 #include <sys/copyops.h>
91 #include <sys/ftrace.h>
92 #include <sys/panic.h>
93 #include <sys/traptrace.h>
94 #include <sys/ontrap.h>
95 #include <sys/cpc_impl.h>
96 #include <sys/bootconf.h>
97 #include <sys/bootinfo.h>
98 #include <sys/promif.h>
99 #include <sys/mach_mmu.h>
100 #include <sys/contract/process_impl.h>
102 #define USER 0x10000 /* user-mode flag added to trap type */
104 static const char *trap_type_mnemonic
[] = {
105 "de", "db", "2", "bp",
106 "of", "br", "ud", "nm",
107 "df", "9", "ts", "np",
108 "ss", "gp", "pf", "15",
109 "mf", "ac", "mc", "xf"
112 static const char *trap_type
[] = {
113 "Divide error", /* trap id 0 */
114 "Debug", /* trap id 1 */
115 "NMI interrupt", /* trap id 2 */
116 "Breakpoint", /* trap id 3 */
117 "Overflow", /* trap id 4 */
118 "BOUND range exceeded", /* trap id 5 */
119 "Invalid opcode", /* trap id 6 */
120 "Device not available", /* trap id 7 */
121 "Double fault", /* trap id 8 */
122 "Coprocessor segment overrun", /* trap id 9 */
123 "Invalid TSS", /* trap id 10 */
124 "Segment not present", /* trap id 11 */
125 "Stack segment fault", /* trap id 12 */
126 "General protection", /* trap id 13 */
127 "Page fault", /* trap id 14 */
128 "Reserved", /* trap id 15 */
129 "x87 floating point error", /* trap id 16 */
130 "Alignment check", /* trap id 17 */
131 "Machine check", /* trap id 18 */
132 "SIMD floating point exception", /* trap id 19 */
135 #define TRAP_TYPES (sizeof (trap_type) / sizeof (trap_type[0]))
137 #define SLOW_SCALL_SIZE 2
138 #define FAST_SCALL_SIZE 2
145 #if defined(TRAPDEBUG) || defined(lint)
153 #endif /* defined(TRAPDEBUG) || defined(lint) */
155 #if defined(TRAPTRACE)
157 * trap trace record for cpu0 is allocated here.
158 * trap trace records for non-boot cpus are allocated in mp_startup_init().
160 static trap_trace_rec_t trap_tr0
[TRAPTR_NENT
];
161 trap_trace_ctl_t trap_trace_ctl
[NCPU
] = {
163 (uintptr_t)trap_tr0
, /* next record */
164 (uintptr_t)trap_tr0
, /* first record */
165 (uintptr_t)(trap_tr0
+ TRAPTR_NENT
), /* limit */
166 (uintptr_t)0 /* current */
171 * default trap buffer size
173 size_t trap_trace_bufsize
= TRAPTR_NENT
* sizeof (trap_trace_rec_t
);
174 int trap_trace_freeze
= 0;
175 int trap_trace_off
= 0;
178 * A dummy TRAPTRACE entry to use after death.
180 trap_trace_rec_t trap_trace_postmort
;
182 static void dump_ttrace(void);
183 #endif /* TRAPTRACE */
184 static void dumpregs(struct regs
*);
185 static void showregs(uint_t
, struct regs
*, caddr_t
);
186 static int kern_gpfault(struct regs
*);
190 die(uint_t type
, struct regs
*rp
, caddr_t addr
, processorid_t cpuid
)
192 struct panic_trap_info ti
;
193 const char *trap_name
, *trap_mnemonic
;
195 if (type
< TRAP_TYPES
) {
196 trap_name
= trap_type
[type
];
197 trap_mnemonic
= trap_type_mnemonic
[type
];
208 ti
.trap_type
= type
& ~USER
;
211 curthread
->t_panic_trap
= &ti
;
213 if (type
== T_PGFLT
&& addr
< (caddr_t
)kernelbase
) {
214 panic("BAD TRAP: type=%x (#%s %s) rp=%p addr=%p "
215 "occurred in module \"%s\" due to %s",
216 type
, trap_mnemonic
, trap_name
, (void *)rp
, (void *)addr
,
217 mod_containing_pc((caddr_t
)rp
->r_pc
),
218 addr
< (caddr_t
)PAGESIZE
?
219 "a NULL pointer dereference" :
220 "an illegal access to a user address");
222 panic("BAD TRAP: type=%x (#%s %s) rp=%p addr=%p",
223 type
, trap_mnemonic
, trap_name
, (void *)rp
, (void *)addr
);
228 * Rewrite the instruction at pc to be an int $T_SYSCALLINT instruction.
230 * int <vector> is two bytes: 0xCD <vector>
234 rewrite_syscall(caddr_t pc
)
236 uchar_t instr
[SLOW_SCALL_SIZE
] = { 0xCD, T_SYSCALLINT
};
238 if (uwrite(curthread
->t_procp
, instr
, SLOW_SCALL_SIZE
,
246 * Test to see if the instruction at pc is sysenter or syscall. The second
247 * argument should be the x86 feature flag corresponding to the expected
250 * sysenter is two bytes: 0x0F 0x34
251 * syscall is two bytes: 0x0F 0x05
252 * int $T_SYSCALLINT is two bytes: 0xCD 0x91
256 instr_is_other_syscall(caddr_t pc
, int which
)
258 uchar_t instr
[FAST_SCALL_SIZE
];
260 ASSERT(which
== X86FSET_SEP
|| which
== X86FSET_ASYSC
|| which
== 0xCD);
262 if (copyin_nowatch(pc
, (caddr_t
)instr
, FAST_SCALL_SIZE
) != 0)
267 if (instr
[0] == 0x0F && instr
[1] == 0x34)
271 if (instr
[0] == 0x0F && instr
[1] == 0x05)
275 if (instr
[0] == 0xCD && instr
[1] == T_SYSCALLINT
)
284 syscall_insn_string(int syscall_insn
)
286 switch (syscall_insn
) {
299 ldt_rewrite_syscall(struct regs
*rp
, proc_t
*p
, int syscall_insn
)
304 mutex_enter(&p
->p_ldtlock
); /* Must be held across linear_pc() */
306 if (linear_pc(rp
, p
, &linearpc
) == 0) {
309 * If another thread beat us here, it already changed
310 * this site to the slower (int) syscall instruction.
312 if (instr_is_other_syscall(linearpc
, 0xCD)) {
314 } else if (instr_is_other_syscall(linearpc
, syscall_insn
)) {
316 if (rewrite_syscall(linearpc
) == 0) {
321 cmn_err(CE_WARN
, "failed to rewrite %s "
322 "instruction in process %d",
323 syscall_insn_string(syscall_insn
),
329 mutex_exit(&p
->p_ldtlock
); /* Must be held across linear_pc() */
331 return (return_code
);
335 * Test to see if the instruction at pc is a system call instruction.
337 * The bytes of an lcall instruction used for the syscall trap.
338 * static uchar_t lcall[7] = { 0x9a, 0, 0, 0, 0, 0x7, 0 };
339 * static uchar_t lcallalt[7] = { 0x9a, 0, 0, 0, 0, 0x27, 0 };
345 instr_is_lcall_syscall(caddr_t pc
)
347 uchar_t instr
[LCALLSIZE
];
349 if (copyin_nowatch(pc
, (caddr_t
)instr
, LCALLSIZE
) == 0 &&
355 (instr
[5] == 0x7 || instr
[5] == 0x27) &&
365 * In the first revisions of amd64 CPUs produced by AMD, the LAHF and
366 * SAHF instructions were not implemented in 64-bit mode. Later revisions
367 * did implement these instructions. An extension to the cpuid instruction
368 * was added to check for the capability of executing these instructions
371 * Intel originally did not implement these instructions in EM64T either,
372 * but added them in later revisions.
374 * So, there are different chip revisions by both vendors out there that
375 * may or may not implement these instructions. The easy solution is to
376 * just always emulate these instructions on demand.
378 * SAHF == store %ah in the lower 8 bits of %rflags (opcode 0x9e)
379 * LAHF == load the lower 8 bits of %rflags into %ah (opcode 0x9f)
385 instr_is_lsahf(caddr_t pc
, uchar_t
*instr
)
387 if (copyin_nowatch(pc
, (caddr_t
)instr
, LSAHFSIZE
) == 0 &&
388 (*instr
== 0x9e || *instr
== 0x9f))
394 * Emulate the LAHF and SAHF instructions. The reference manuals define
395 * these instructions to always load/store bit 1 as a 1, and bits 3 and 5
396 * as a 0. The other, defined, bits are copied (the PS_ICC bits and PS_P).
398 * Note that %ah is bits 8-15 of %rax.
401 emulate_lsahf(struct regs
*rp
, uchar_t instr
)
404 /* sahf. Copy bits from %ah to flags. */
405 rp
->r_ps
= (rp
->r_ps
& ~0xff) |
406 ((rp
->r_rax
>> 8) & PSL_LSAHFMASK
) | PS_MB1
;
408 /* lahf. Copy bits from flags to %ah. */
409 rp
->r_rax
= (rp
->r_rax
& ~0xff00) |
410 (((rp
->r_ps
& PSL_LSAHFMASK
) | PS_MB1
) << 8);
412 rp
->r_pc
+= LSAHFSIZE
;
416 #ifdef OPTERON_ERRATUM_91
419 * Test to see if the instruction at pc is a prefetch instruction.
421 * The first byte of prefetch instructions is always 0x0F.
422 * The second byte is 0x18 for regular prefetch or 0x0D for AMD 3dnow prefetch.
423 * The third byte (ModRM) contains the register field bits (bits 3-5).
424 * These bits must be between 0 and 3 inclusive for regular prefetch and
425 * 0 and 1 inclusive for AMD 3dnow prefetch.
427 * In 64-bit mode, there may be a one-byte REX prefex (0x40-0x4F).
431 cmp_to_prefetch(uchar_t
*p
)
434 if ((p
[0] & 0xF0) == 0x40) /* 64-bit REX prefix */
437 return ((p
[0] == 0x0F && p
[1] == 0x18 && ((p
[2] >> 3) & 7) <= 3) ||
438 (p
[0] == 0x0F && p
[1] == 0x0D && ((p
[2] >> 3) & 7) <= 1));
442 instr_is_prefetch(caddr_t pc
)
444 uchar_t instr
[4]; /* optional REX prefix plus 3-byte opcode */
446 return (copyin_nowatch(pc
, instr
, sizeof (instr
)) == 0 &&
447 cmp_to_prefetch(instr
));
450 #endif /* OPTERON_ERRATUM_91 */
453 * Called from the trap handler when a processor trap occurs.
455 * Note: All user-level traps that might call stop() must exit
456 * trap() by 'goto out' or by falling through.
457 * Note Also: trap() is usually called with interrupts enabled, (PS_IE == 1)
458 * however, there are paths that arrive here with PS_IE == 0 so special care
459 * must be taken in those cases.
462 trap(struct regs
*rp
, caddr_t addr
, processorid_t cpuid
)
464 kthread_t
*ct
= curthread
;
467 proc_t
*p
= ttoproc(ct
);
468 klwp_t
*lwp
= ttolwp(ct
);
471 faultcode_t
pagefault(), res
, errcode
;
472 enum fault_type fault_type
;
486 ASSERT_STACK_ALIGNED();
489 CPU_STATS_ADDQ(CPU
, sys
, trap
, 1);
491 if (type
== T_PGFLT
) {
494 if (errcode
& PF_ERR_WRITE
)
496 else if ((caddr_t
)rp
->r_pc
== addr
||
497 (mmu
.pt_nx
!= 0 && (errcode
& PF_ERR_EXEC
)))
504 * Pentium Pro work-around
506 if ((errcode
& PF_ERR_PROT
) && pentiumpro_bug4046376
) {
508 uint_t priv_violation
;
509 uint_t access_violation
;
511 if (hat_getattr(addr
< (caddr_t
)kernelbase
?
512 curproc
->p_as
->a_hat
: kas
.a_hat
, addr
, &attr
)
514 errcode
&= ~PF_ERR_PROT
;
516 priv_violation
= (errcode
& PF_ERR_USER
) &&
518 access_violation
= (errcode
& PF_ERR_WRITE
) &&
519 !(attr
& PROT_WRITE
);
520 if (!priv_violation
&& !access_violation
)
526 } else if (type
== T_SGLSTP
&& lwp
!= NULL
)
527 lwp
->lwp_pcb
.pcb_drstat
= (uintptr_t)addr
;
530 showregs(type
, rp
, addr
);
532 if (USERMODE(rp
->r_cs
)) {
534 * Set up the current cred to use during this trap. u_cred
535 * no longer exists. t_cred is used instead.
536 * The current process credential applies to the thread for
537 * the entire trap. If trapping from the kernel, this
538 * should already be set up.
540 if (ct
->t_cred
!= p
->p_cred
) {
541 cred_t
*oldcred
= ct
->t_cred
;
543 * DTrace accesses t_cred in probe context. t_cred
544 * must always be either NULL, or point to a valid,
545 * allocated cred structure.
547 ct
->t_cred
= crgetcred();
552 ASSERT(lwptoregs(lwp
) == rp
);
553 lwp
->lwp_state
= LWP_SYS
;
557 if ((caddr_t
)rp
->r_pc
== addr
)
567 mstate
= new_mstate(ct
, mstate
);
569 bzero(&siginfo
, sizeof (siginfo
));
575 case T_SGLSTP
+ USER
:
576 case T_BPTFLT
+ USER
:
580 FTRACE_2("trap(): type=0x%lx, regs=0x%lx",
581 (ulong_t
)type
, (ulong_t
)rp
);
587 /* Make sure we enable interrupts before die()ing */
588 sti(); /* The SIMD exception comes in via cmninttrap */
593 showregs(type
, rp
, (caddr_t
)0);
594 printf("trap: Unknown trap type %d in user mode\n",
596 siginfo
.si_signo
= SIGILL
;
597 siginfo
.si_code
= ILL_ILLTRP
;
598 siginfo
.si_addr
= (caddr_t
)rp
->r_pc
;
599 siginfo
.si_trapno
= type
& ~USER
;
602 (void) die(type
, rp
, addr
, cpuid
);
607 case T_PGFLT
: /* system page fault */
609 * If we're under on_trap() protection (see <sys/ontrap.h>),
610 * set ot_trap and bounce back to the on_trap() call site
611 * via the installed trampoline.
613 if ((ct
->t_ontrap
!= NULL
) &&
614 (ct
->t_ontrap
->ot_prot
& OT_DATA_ACCESS
)) {
615 ct
->t_ontrap
->ot_trap
|= OT_DATA_ACCESS
;
616 rp
->r_pc
= ct
->t_ontrap
->ot_trampoline
;
621 * If we have an Instruction fault in kernel mode, then that
622 * means we've tried to execute a user page (SMEP) or both of
623 * PAE and NXE are enabled. In either case, given that it's a
624 * kernel fault, we should panic immediately and not try to make
625 * any more forward progress. This indicates a bug in the
626 * kernel, which if execution continued, could be exploited to
627 * wreak havoc on the system.
629 if (errcode
& PF_ERR_EXEC
) {
630 (void) die(type
, rp
, addr
, cpuid
);
634 * We need to check if SMAP is in play. If SMAP is in play, then
635 * any access to a user page will show up as a protection
636 * violation. To see if SMAP is enabled we first check if it's a
637 * user address and whether we have the feature flag set. If we
638 * do and the interrupted registers do not allow for user
639 * accesses (PS_ACHK is not enabled), then we need to die
642 if (addr
< (caddr_t
)kernelbase
&&
643 is_x86_feature(x86_featureset
, X86FSET_SMAP
) == B_TRUE
&&
644 (rp
->r_ps
& PS_ACHK
) == 0) {
645 (void) die(type
, rp
, addr
, cpuid
);
649 * See if we can handle as pagefault. Save lofault and onfault
650 * across this. Here we assume that an address less than
651 * KERNELBASE is a user fault. We can do this as copy.s
652 * routines verify that the starting address is less than
653 * KERNELBASE before starting and because we know that we
654 * always have KERNELBASE mapped as invalid to serve as a
657 lofault
= ct
->t_lofault
;
658 onfault
= ct
->t_onfault
;
661 mstate
= new_mstate(ct
, LMS_KFAULT
);
663 if (addr
< (caddr_t
)kernelbase
) {
664 res
= pagefault(addr
,
665 (errcode
& PF_ERR_PROT
)? F_PROT
: F_INVAL
, rw
, 0);
666 if (res
== FC_NOMAP
&&
667 addr
< p
->p_usrstack
&&
671 res
= pagefault(addr
,
672 (errcode
& PF_ERR_PROT
)? F_PROT
: F_INVAL
, rw
, 1);
674 (void) new_mstate(ct
, mstate
);
677 * Restore lofault and onfault. If we resolved the fault, exit.
678 * If we didn't and lofault wasn't set, die.
680 ct
->t_lofault
= lofault
;
681 ct
->t_onfault
= onfault
;
685 #if defined(OPTERON_ERRATUM_93) && defined(_LP64)
686 if (lofault
== 0 && opteron_erratum_93
) {
688 * Workaround for Opteron Erratum 93. On return from
689 * a System Managment Interrupt at a HLT instruction
690 * the %rip might be truncated to a 32 bit value.
691 * BIOS is supposed to fix this, but some don't.
692 * If this occurs we simply restore the high order bits.
693 * The HLT instruction is 1 byte of 0xf4.
695 uintptr_t rip
= rp
->r_pc
;
697 if ((rip
& 0xfffffffful
) == rip
) {
698 rip
|= 0xfffffffful
<< 32;
699 if (hat_getpfnum(kas
.a_hat
, (caddr_t
)rip
) !=
701 (*(uchar_t
*)rip
== 0xf4 ||
702 *(uchar_t
*)(rip
- 1) == 0xf4)) {
708 #endif /* OPTERON_ERRATUM_93 && _LP64 */
710 #ifdef OPTERON_ERRATUM_91
711 if (lofault
== 0 && opteron_erratum_91
) {
713 * Workaround for Opteron Erratum 91. Prefetches may
714 * generate a page fault (they're not supposed to do
715 * that!). If this occurs we simply return back to the
718 caddr_t pc
= (caddr_t
)rp
->r_pc
;
721 * If the faulting PC is not mapped, this is a
722 * legitimate kernel page fault that must result in a
723 * panic. If the faulting PC is mapped, it could contain
724 * a prefetch instruction. Check for that here.
726 if (hat_getpfnum(kas
.a_hat
, pc
) != PFN_INVALID
) {
727 if (cmp_to_prefetch((uchar_t
*)pc
)) {
729 cmn_err(CE_WARN
, "Opteron erratum 91 "
730 "occurred: kernel prefetch"
731 " at %p generated a page fault!",
737 (void) die(type
, rp
, addr
, cpuid
);
739 #endif /* OPTERON_ERRATUM_91 */
742 (void) die(type
, rp
, addr
, cpuid
);
745 * Cannot resolve fault. Return to lofault.
748 showregs(type
, rp
, addr
);
751 if (FC_CODE(res
) == FC_OBJERR
)
756 rp
->r_pc
= ct
->t_lofault
;
759 case T_PGFLT
+ USER
: /* user page fault */
777 printf("user %s fault: addr=0x%lx errcode=0x%x\n",
778 fault_str
, (uintptr_t)addr
, errcode
);
781 #if defined(OPTERON_ERRATUM_100) && defined(_LP64)
783 * Workaround for AMD erratum 100
785 * A 32-bit process may receive a page fault on a non
786 * 32-bit address by mistake. The range of the faulting
789 * 0xffffffff80000000 .. 0xffffffffffffffff or
790 * 0x0000000100000000 .. 0x000000017fffffff
792 * The fault is always due to an instruction fetch, however
793 * the value of r_pc should be correct (in 32 bit range),
794 * so we ignore the page fault on the bogus address.
796 if (p
->p_model
== DATAMODEL_ILP32
&&
797 (0xffffffff80000000 <= (uintptr_t)addr
||
798 (0x100000000 <= (uintptr_t)addr
&&
799 (uintptr_t)addr
<= 0x17fffffff))) {
800 if (!opteron_erratum_100
)
801 panic("unexpected erratum #100");
802 if (rp
->r_pc
<= 0xffffffff)
805 #endif /* OPTERON_ERRATUM_100 && _LP64 */
807 ASSERT(!(curthread
->t_flag
& T_WATCHPT
));
808 watchpage
= (pr_watch_active(p
) && pr_is_watchpage(addr
, rw
));
811 * In 32-bit mode, the lcall (system call) instruction fetches
812 * one word from the stack, at the stack pointer, because of the
813 * way the call gate is constructed. This is a bogus
814 * read and should not be counted as a read watchpoint.
815 * We work around the problem here by testing to see if
816 * this situation applies and, if so, simply jumping to
817 * the code in locore.s that fields the system call trap.
818 * The registers on the stack are already set up properly
819 * due to the match between the call gate sequence and the
820 * trap gate sequence. We just have to adjust the pc.
822 if (watchpage
&& addr
== (caddr_t
)rp
->r_sp
&&
823 rw
== S_READ
&& instr_is_lcall_syscall((caddr_t
)rp
->r_pc
)) {
824 extern void watch_syscall(void);
826 rp
->r_pc
+= LCALLSIZE
;
827 watch_syscall(); /* never returns */
832 if (!watchpage
|| (sz
= instr_size(rp
, &vaddr
, rw
)) <= 0)
833 fault_type
= (errcode
& PF_ERR_PROT
)? F_PROT
: F_INVAL
;
834 else if ((watchcode
= pr_is_watchpoint(&vaddr
, &ta
,
835 sz
, NULL
, rw
)) != 0) {
837 do_watch_step(vaddr
, sz
, rw
,
838 watchcode
, rp
->r_pc
);
839 fault_type
= F_INVAL
;
841 bzero(&siginfo
, sizeof (siginfo
));
842 siginfo
.si_signo
= SIGTRAP
;
843 siginfo
.si_code
= watchcode
;
844 siginfo
.si_addr
= vaddr
;
845 siginfo
.si_trapafter
= 0;
846 siginfo
.si_pc
= (caddr_t
)rp
->r_pc
;
851 /* XXX pr_watch_emul() never succeeds (for now) */
852 if (rw
!= S_EXEC
&& pr_watch_emul(rp
, vaddr
, rw
))
854 do_watch_step(vaddr
, sz
, rw
, 0, 0);
855 fault_type
= F_INVAL
;
858 res
= pagefault(addr
, fault_type
, rw
, 0);
861 * If pagefault() succeeded, ok.
862 * Otherwise attempt to grow the stack.
866 addr
< p
->p_usrstack
&&
868 lwp
->lwp_lastfault
= FLTPAGE
;
869 lwp
->lwp_lastfaddr
= addr
;
870 if (prismember(&p
->p_fltmask
, FLTPAGE
)) {
871 bzero(&siginfo
, sizeof (siginfo
));
872 siginfo
.si_addr
= addr
;
873 (void) stop_on_fault(FLTPAGE
, &siginfo
);
876 } else if (res
== FC_PROT
&& addr
< p
->p_usrstack
&&
877 (mmu
.pt_nx
!= 0 && (errcode
& PF_ERR_EXEC
))) {
878 report_stack_exec(p
, addr
);
881 #ifdef OPTERON_ERRATUM_91
883 * Workaround for Opteron Erratum 91. Prefetches may generate a
884 * page fault (they're not supposed to do that!). If this
885 * occurs we simply return back to the instruction.
887 * We rely on copyin to properly fault in the page with r_pc.
889 if (opteron_erratum_91
&&
890 addr
!= (caddr_t
)rp
->r_pc
&&
891 instr_is_prefetch((caddr_t
)rp
->r_pc
)) {
893 cmn_err(CE_WARN
, "Opteron erratum 91 occurred: "
894 "prefetch at %p in pid %d generated a trap!",
895 (void *)rp
->r_pc
, p
->p_pid
);
899 #endif /* OPTERON_ERRATUM_91 */
902 showregs(type
, rp
, addr
);
904 * In the case where both pagefault and grow fail,
905 * set the code to the value provided by pagefault.
906 * We map all errors returned from pagefault() to SIGSEGV.
908 bzero(&siginfo
, sizeof (siginfo
));
909 siginfo
.si_addr
= addr
;
910 switch (FC_CODE(res
)) {
913 siginfo
.si_signo
= SIGBUS
;
914 siginfo
.si_code
= BUS_ADRERR
;
918 siginfo
.si_signo
= SIGBUS
;
919 siginfo
.si_code
= BUS_ADRALN
;
923 if ((siginfo
.si_errno
= FC_ERRNO(res
)) != EINTR
) {
924 siginfo
.si_signo
= SIGBUS
;
925 siginfo
.si_code
= BUS_OBJERR
;
929 default: /* FC_NOMAP or FC_PROT */
930 siginfo
.si_signo
= SIGSEGV
;
932 (res
== FC_NOMAP
)? SEGV_MAPERR
: SEGV_ACCERR
;
938 case T_ILLINST
+ USER
: /* invalid opcode fault */
940 * If the syscall instruction is disabled due to LDT usage, a
941 * user program that attempts to execute it will trigger a #ud
942 * trap. Check for that case here. If this occurs on a CPU which
943 * doesn't even support syscall, the result of all of this will
944 * be to emulate that particular instruction.
946 if (p
->p_ldt
!= NULL
&&
947 ldt_rewrite_syscall(rp
, p
, X86FSET_ASYSC
))
952 * Emulate the LAHF and SAHF instructions if needed.
953 * See the instr_is_lsahf function for details.
955 if (p
->p_model
== DATAMODEL_LP64
&&
956 instr_is_lsahf((caddr_t
)rp
->r_pc
, &instr
)) {
957 emulate_lsahf(rp
, instr
);
965 showregs(type
, rp
, (caddr_t
)0);
966 siginfo
.si_signo
= SIGILL
;
967 siginfo
.si_code
= ILL_ILLOPC
;
968 siginfo
.si_addr
= (caddr_t
)rp
->r_pc
;
972 case T_ZERODIV
+ USER
: /* integer divide by zero */
973 if (tudebug
&& tudebugfpe
)
974 showregs(type
, rp
, (caddr_t
)0);
975 siginfo
.si_signo
= SIGFPE
;
976 siginfo
.si_code
= FPE_INTDIV
;
977 siginfo
.si_addr
= (caddr_t
)rp
->r_pc
;
981 case T_OVFLW
+ USER
: /* integer overflow */
982 if (tudebug
&& tudebugfpe
)
983 showregs(type
, rp
, (caddr_t
)0);
984 siginfo
.si_signo
= SIGFPE
;
985 siginfo
.si_code
= FPE_INTOVF
;
986 siginfo
.si_addr
= (caddr_t
)rp
->r_pc
;
990 case T_NOEXTFLT
+ USER
: /* math coprocessor not available */
991 if (tudebug
&& tudebugfpe
)
992 showregs(type
, rp
, addr
);
993 if (fpnoextflt(rp
)) {
994 siginfo
.si_signo
= SIGILL
;
995 siginfo
.si_code
= ILL_ILLOPC
;
996 siginfo
.si_addr
= (caddr_t
)rp
->r_pc
;
1001 case T_EXTOVRFLT
: /* extension overrun fault */
1002 /* check if we took a kernel trap on behalf of user */
1004 extern void ndptrap_frstor(void);
1005 if (rp
->r_pc
!= (uintptr_t)ndptrap_frstor
) {
1006 sti(); /* T_EXTOVRFLT comes in via cmninttrap */
1007 (void) die(type
, rp
, addr
, cpuid
);
1012 case T_EXTOVRFLT
+ USER
: /* extension overrun fault */
1013 if (tudebug
&& tudebugfpe
)
1014 showregs(type
, rp
, addr
);
1015 if (fpextovrflt(rp
)) {
1016 siginfo
.si_signo
= SIGSEGV
;
1017 siginfo
.si_code
= SEGV_MAPERR
;
1018 siginfo
.si_addr
= (caddr_t
)rp
->r_pc
;
1023 case T_EXTERRFLT
: /* x87 floating point exception pending */
1024 /* check if we took a kernel trap on behalf of user */
1026 extern void ndptrap_frstor(void);
1027 if (rp
->r_pc
!= (uintptr_t)ndptrap_frstor
) {
1028 sti(); /* T_EXTERRFLT comes in via cmninttrap */
1029 (void) die(type
, rp
, addr
, cpuid
);
1035 case T_EXTERRFLT
+ USER
: /* x87 floating point exception pending */
1036 if (tudebug
&& tudebugfpe
)
1037 showregs(type
, rp
, addr
);
1038 if (sicode
= fpexterrflt(rp
)) {
1039 siginfo
.si_signo
= SIGFPE
;
1040 siginfo
.si_code
= sicode
;
1041 siginfo
.si_addr
= (caddr_t
)rp
->r_pc
;
1046 case T_SIMDFPE
+ USER
: /* SSE and SSE2 exceptions */
1047 if (tudebug
&& tudebugsse
)
1048 showregs(type
, rp
, addr
);
1049 if (!is_x86_feature(x86_featureset
, X86FSET_SSE
) &&
1050 !is_x86_feature(x86_featureset
, X86FSET_SSE2
)) {
1052 * There are rumours that some user instructions
1053 * on older CPUs can cause this trap to occur; in
1054 * which case send a SIGILL instead of a SIGFPE.
1056 siginfo
.si_signo
= SIGILL
;
1057 siginfo
.si_code
= ILL_ILLTRP
;
1058 siginfo
.si_addr
= (caddr_t
)rp
->r_pc
;
1059 siginfo
.si_trapno
= type
& ~USER
;
1061 } else if ((sicode
= fpsimderrflt(rp
)) != 0) {
1062 siginfo
.si_signo
= SIGFPE
;
1063 siginfo
.si_code
= sicode
;
1064 siginfo
.si_addr
= (caddr_t
)rp
->r_pc
;
1068 sti(); /* The SIMD exception comes in via cmninttrap */
1071 case T_BPTFLT
: /* breakpoint trap */
1073 * Kernel breakpoint traps should only happen when kmdb is
1074 * active, and even then, it'll have interposed on the IDT, so
1075 * control won't get here. If it does, we've hit a breakpoint
1076 * without the debugger, which is very strange, and very
1079 if (tudebug
&& tudebugbpt
)
1080 showregs(type
, rp
, (caddr_t
)0);
1082 (void) die(type
, rp
, addr
, cpuid
);
1085 case T_SGLSTP
: /* single step/hw breakpoint exception */
1089 * We'd never normally get here, as kmdb handles its own single
1090 * step traps. There is one nasty exception though, as
1091 * described in more detail in sys_sysenter(). Note that
1092 * checking for all four locations covers both the KPTI and the
1093 * non-KPTI cases correctly: the former will never be found at
1094 * (brand_)sys_sysenter, and vice versa.
1096 if (lwp
!= NULL
&& (lwp
->lwp_pcb
.pcb_drstat
& DR_SINGLESTEP
)) {
1097 if (rp
->r_pc
== (greg_t
)brand_sys_sysenter
||
1098 rp
->r_pc
== (greg_t
)sys_sysenter
||
1099 rp
->r_pc
== (greg_t
)tr_brand_sys_sysenter
||
1100 rp
->r_pc
== (greg_t
)tr_sys_sysenter
) {
1102 rp
->r_pc
+= 0x3; /* sizeof (swapgs) */
1104 rp
->r_ps
&= ~PS_T
; /* turn off trace */
1105 lwp
->lwp_pcb
.pcb_flags
|= DEBUG_PENDING
;
1110 if (tudebug
&& tudebugbpt
)
1111 showregs(type
, rp
, (caddr_t
)0);
1116 if (boothowto
& RB_DEBUG
)
1119 (void) die(type
, rp
, addr
, cpuid
);
1122 case T_NMIFLT
: /* NMI interrupt */
1123 printf("Unexpected NMI in system mode\n");
1126 case T_NMIFLT
+ USER
: /* NMI interrupt */
1127 printf("Unexpected NMI in user mode\n");
1130 case T_GPFLT
: /* general protection violation */
1132 * Any #GP that occurs during an on_trap .. no_trap bracket
1133 * with OT_DATA_ACCESS or OT_SEGMENT_ACCESS protection,
1134 * or in a on_fault .. no_fault bracket, is forgiven
1135 * and we trampoline. This protection is given regardless
1136 * of whether we are 32/64 bit etc - if a distinction is
1137 * required then define new on_trap protection types.
1139 * On amd64, we can get a #gp from referencing addresses
1140 * in the virtual address hole e.g. from a copyin or in
1141 * update_sregs while updating user segment registers.
1143 * On the 32-bit hypervisor we could also generate one in
1144 * mfn_to_pfn by reaching around or into where the hypervisor
1145 * lives which is protected by segmentation.
1149 * If we're under on_trap() protection (see <sys/ontrap.h>),
1150 * set ot_trap and trampoline back to the on_trap() call site
1151 * for OT_DATA_ACCESS or OT_SEGMENT_ACCESS.
1153 if (ct
->t_ontrap
!= NULL
) {
1154 int ttype
= ct
->t_ontrap
->ot_prot
&
1155 (OT_DATA_ACCESS
| OT_SEGMENT_ACCESS
);
1158 ct
->t_ontrap
->ot_trap
|= ttype
;
1160 showregs(type
, rp
, (caddr_t
)0);
1161 rp
->r_pc
= ct
->t_ontrap
->ot_trampoline
;
1167 * If we're under lofault protection (copyin etc.),
1168 * longjmp back to lofault with an EFAULT.
1170 if (ct
->t_lofault
) {
1172 * Fault is not resolvable, so just return to lofault
1175 showregs(type
, rp
, addr
);
1179 rp
->r_pc
= ct
->t_lofault
;
1184 * We fall through to the next case, which repeats
1185 * the OT_SEGMENT_ACCESS check which we've already
1186 * done, so we'll always fall through to the
1190 case T_SEGFLT
: /* segment not present fault */
1192 * One example of this is #NP in update_sregs while
1193 * attempting to update a user segment register
1194 * that points to a descriptor that is marked not
1197 if (ct
->t_ontrap
!= NULL
&&
1198 ct
->t_ontrap
->ot_prot
& OT_SEGMENT_ACCESS
) {
1199 ct
->t_ontrap
->ot_trap
|= OT_SEGMENT_ACCESS
;
1201 showregs(type
, rp
, (caddr_t
)0);
1202 rp
->r_pc
= ct
->t_ontrap
->ot_trampoline
;
1206 case T_STKFLT
: /* stack fault */
1207 case T_TSSFLT
: /* invalid TSS fault */
1209 showregs(type
, rp
, (caddr_t
)0);
1210 if (kern_gpfault(rp
))
1211 (void) die(type
, rp
, addr
, cpuid
);
1215 * ONLY 32-bit PROCESSES can USE a PRIVATE LDT! 64-bit apps
1216 * should have no need for them, so we put a stop to it here.
1218 * So: not-present fault is ONLY valid for 32-bit processes with
1219 * a private LDT trying to do a system call. Emulate it.
1221 * #gp fault is ONLY valid for 32-bit processes also, which DO NOT
1222 * have a private LDT, and are trying to do a system call. Emulate it.
1225 case T_SEGFLT
+ USER
: /* segment not present fault */
1226 case T_GPFLT
+ USER
: /* general protection violation */
1227 #ifdef _SYSCALL32_IMPL
1228 if (p
->p_model
!= DATAMODEL_NATIVE
) {
1229 #endif /* _SYSCALL32_IMPL */
1230 if (instr_is_lcall_syscall((caddr_t
)rp
->r_pc
)) {
1231 if (type
== T_SEGFLT
+ USER
)
1232 ASSERT(p
->p_ldt
!= NULL
);
1234 if ((p
->p_ldt
== NULL
&& type
== T_GPFLT
+ USER
) ||
1235 type
== T_SEGFLT
+ USER
) {
1238 * The user attempted a system call via the obsolete
1239 * call gate mechanism. Because the process doesn't have
1240 * an LDT (i.e. the ldtr contains 0), a #gp results.
1241 * Emulate the syscall here, just as we do above for a
1246 * Since this is a not-present trap, rp->r_pc points to
1247 * the trapping lcall instruction. We need to bump it
1248 * to the next insn so the app can continue on.
1250 rp
->r_pc
+= LCALLSIZE
;
1254 * Normally the microstate of the LWP is forced back to
1255 * LMS_USER by the syscall handlers. Emulate that
1264 #ifdef _SYSCALL32_IMPL
1266 #endif /* _SYSCALL32_IMPL */
1268 * If the current process is using a private LDT and the
1269 * trapping instruction is sysenter, the sysenter instruction
1270 * has been disabled on the CPU because it destroys segment
1271 * registers. If this is the case, rewrite the instruction to
1272 * be a safe system call and retry it. If this occurs on a CPU
1273 * which doesn't even support sysenter, the result of all of
1274 * this will be to emulate that particular instruction.
1276 if (p
->p_ldt
!= NULL
&&
1277 ldt_rewrite_syscall(rp
, p
, X86FSET_SEP
))
1282 case T_BOUNDFLT
+ USER
: /* bound fault */
1283 case T_STKFLT
+ USER
: /* stack fault */
1284 case T_TSSFLT
+ USER
: /* invalid TSS fault */
1286 showregs(type
, rp
, (caddr_t
)0);
1287 siginfo
.si_signo
= SIGSEGV
;
1288 siginfo
.si_code
= SEGV_MAPERR
;
1289 siginfo
.si_addr
= (caddr_t
)rp
->r_pc
;
1293 case T_ALIGNMENT
+ USER
: /* user alignment error (486) */
1295 showregs(type
, rp
, (caddr_t
)0);
1296 bzero(&siginfo
, sizeof (siginfo
));
1297 siginfo
.si_signo
= SIGBUS
;
1298 siginfo
.si_code
= BUS_ADRALN
;
1299 siginfo
.si_addr
= (caddr_t
)rp
->r_pc
;
1303 case T_SGLSTP
+ USER
: /* single step/hw breakpoint exception */
1304 if (tudebug
&& tudebugbpt
)
1305 showregs(type
, rp
, (caddr_t
)0);
1307 /* Was it single-stepping? */
1308 if (lwp
->lwp_pcb
.pcb_drstat
& DR_SINGLESTEP
) {
1309 pcb_t
*pcb
= &lwp
->lwp_pcb
;
1313 * If both NORMAL_STEP and WATCH_STEP are in effect,
1314 * give precedence to WATCH_STEP. If neither is set,
1315 * user must have set the PS_T bit in %efl; treat this
1318 if ((fault
= undo_watch_step(&siginfo
)) == 0 &&
1319 ((pcb
->pcb_flags
& NORMAL_STEP
) ||
1320 !(pcb
->pcb_flags
& WATCH_STEP
))) {
1321 siginfo
.si_signo
= SIGTRAP
;
1322 siginfo
.si_code
= TRAP_TRACE
;
1323 siginfo
.si_addr
= (caddr_t
)rp
->r_pc
;
1326 pcb
->pcb_flags
&= ~(NORMAL_STEP
|WATCH_STEP
);
1330 case T_BPTFLT
+ USER
: /* breakpoint trap */
1331 if (tudebug
&& tudebugbpt
)
1332 showregs(type
, rp
, (caddr_t
)0);
1334 * int 3 (the breakpoint instruction) leaves the pc referring
1335 * to the address one byte after the breakpointed address.
1336 * If the P_PR_BPTADJ flag has been set via /proc, We adjust
1337 * it back so it refers to the breakpointed address.
1339 if (p
->p_proc_flag
& P_PR_BPTADJ
)
1341 siginfo
.si_signo
= SIGTRAP
;
1342 siginfo
.si_code
= TRAP_BRKPT
;
1343 siginfo
.si_addr
= (caddr_t
)rp
->r_pc
;
1349 * This occurs only after the cs register has been made to
1350 * look like a kernel selector, either through debugging or
1351 * possibly by functions like setcontext(). The thread is
1352 * about to cause a general protection fault at common_iret()
1353 * in locore. We let that happen immediately instead of
1354 * doing the T_AST processing.
1358 case T_AST
+ USER
: /* profiling, resched, h/w error pseudo trap */
1359 if (lwp
->lwp_pcb
.pcb_flags
& ASYNC_HWERR
) {
1360 proc_t
*p
= ttoproc(curthread
);
1361 extern void print_msg_hwerr(ctid_t ct_id
, proc_t
*p
);
1363 lwp
->lwp_pcb
.pcb_flags
&= ~ASYNC_HWERR
;
1364 print_msg_hwerr(p
->p_ct_process
->conp_contract
.ct_id
,
1366 contract_process_hwerr(p
->p_ct_process
, p
);
1367 siginfo
.si_signo
= SIGKILL
;
1368 siginfo
.si_code
= SI_NOINFO
;
1369 } else if (lwp
->lwp_pcb
.pcb_flags
& CPC_OVERFLOW
) {
1370 lwp
->lwp_pcb
.pcb_flags
&= ~CPC_OVERFLOW
;
1371 if (kcpc_overflow_ast()) {
1373 * Signal performance counter overflow
1376 showregs(type
, rp
, (caddr_t
)0);
1377 bzero(&siginfo
, sizeof (siginfo
));
1378 siginfo
.si_signo
= SIGEMT
;
1379 siginfo
.si_code
= EMT_CPCOVF
;
1380 siginfo
.si_addr
= (caddr_t
)rp
->r_pc
;
1389 * We can't get here from a system trap
1391 ASSERT(type
& USER
);
1394 /* We took a fault so abort single step. */
1395 lwp
->lwp_pcb
.pcb_flags
&= ~(NORMAL_STEP
|WATCH_STEP
);
1397 * Remember the fault and fault adddress
1398 * for real-time (SIGPROF) profiling.
1400 lwp
->lwp_lastfault
= fault
;
1401 lwp
->lwp_lastfaddr
= siginfo
.si_addr
;
1403 DTRACE_PROC2(fault
, int, fault
, ksiginfo_t
*, &siginfo
);
1406 * If a debugger has declared this fault to be an
1407 * event of interest, stop the lwp. Otherwise just
1408 * deliver the associated signal.
1410 if (siginfo
.si_signo
!= SIGKILL
&&
1411 prismember(&p
->p_fltmask
, fault
) &&
1412 stop_on_fault(fault
, &siginfo
) == 0)
1413 siginfo
.si_signo
= 0;
1416 if (siginfo
.si_signo
)
1417 trapsig(&siginfo
, (fault
!= FLTFPE
&& fault
!= FLTCPCOVF
));
1419 if (lwp
->lwp_oweupc
)
1420 profil_tick(rp
->r_pc
);
1422 if (ct
->t_astflag
| ct
->t_sig_check
) {
1424 * Turn off the AST flag before checking all the conditions that
1425 * may have caused an AST. This flag is on whenever a signal or
1426 * unusual condition should be handled after the next trap or
1431 * If a single-step trap occurred on a syscall (see above)
1432 * recognize it now. Do this before checking for signals
1433 * because deferred_singlestep_trap() may generate a SIGTRAP to
1434 * the LWP or may otherwise mark the LWP to call issig(FORREAL).
1436 if (lwp
->lwp_pcb
.pcb_flags
& DEBUG_PENDING
)
1437 deferred_singlestep_trap((caddr_t
)rp
->r_pc
);
1439 ct
->t_sig_check
= 0;
1442 * As in other code paths that check against TP_CHANGEBIND,
1443 * we perform the check first without p_lock held -- only
1444 * acquiring p_lock in the unlikely event that it is indeed
1445 * set. This is safe because we are doing this after the
1446 * astoff(); if we are racing another thread setting
1447 * TP_CHANGEBIND on us, we will pick it up on a subsequent
1450 if (curthread
->t_proc_flag
& TP_CHANGEBIND
) {
1451 mutex_enter(&p
->p_lock
);
1452 if (curthread
->t_proc_flag
& TP_CHANGEBIND
) {
1454 curthread
->t_proc_flag
&= ~TP_CHANGEBIND
;
1456 mutex_exit(&p
->p_lock
);
1460 * for kaio requests that are on the per-process poll queue,
1461 * aiop->aio_pollq, they're AIO_POLL bit is set, the kernel
1462 * should copyout their result_t to user memory. by copying
1463 * out the result_t, the user can poll on memory waiting
1464 * for the kaio request to complete.
1469 * If this LWP was asked to hold, call holdlwp(), which will
1470 * stop. holdlwps() sets this up and calls pokelwps() which
1471 * sets the AST flag.
1473 * Also check TP_EXITLWP, since this is used by fresh new LWPs
1474 * through lwp_rtt(). That flag is set if the lwp_create(2)
1475 * syscall failed after creating the LWP.
1481 * All code that sets signals and makes ISSIG evaluate true must
1482 * set t_astflag afterwards.
1484 if (ISSIG_PENDING(ct
, lwp
, p
)) {
1487 ct
->t_sig_check
= 1;
1490 if (ct
->t_rprof
!= NULL
) {
1491 realsigprof(0, 0, 0);
1492 ct
->t_sig_check
= 1;
1496 * /proc can't enable/disable the trace bit itself
1497 * because that could race with the call gate used by
1498 * system calls via "lcall". If that happened, an
1499 * invalid EFLAGS would result. prstep()/prnostep()
1500 * therefore schedule an AST for the purpose.
1502 if (lwp
->lwp_pcb
.pcb_flags
& REQUEST_STEP
) {
1503 lwp
->lwp_pcb
.pcb_flags
&= ~REQUEST_STEP
;
1506 if (lwp
->lwp_pcb
.pcb_flags
& REQUEST_NOSTEP
) {
1507 lwp
->lwp_pcb
.pcb_flags
&= ~REQUEST_NOSTEP
;
1512 out
: /* We can't get here from a system trap */
1513 ASSERT(type
& USER
);
1519 * Set state to LWP_USER here so preempt won't give us a kernel
1520 * priority if it occurs after this point. Call CL_TRAPRET() to
1521 * restore the user-level priority.
1523 * It is important that no locks (other than spinlocks) be entered
1524 * after this point before returning to user mode (unless lwp_state
1525 * is set back to LWP_SYS).
1527 lwp
->lwp_state
= LWP_USER
;
1529 if (ct
->t_trapret
) {
1535 if (CPU
->cpu_runrun
|| curthread
->t_schedflag
& TS_ANYWAITQ
)
1538 (void) new_mstate(ct
, mstate
);
1542 cleanup
: /* system traps end up here */
1543 ASSERT(!(type
& USER
));
1547 * Patch non-zero to disable preemption of threads in the kernel.
1549 int IGNORE_KERNEL_PREEMPTION
= 0; /* XXX - delete this someday */
1551 struct kpreempt_cnts
{ /* kernel preemption statistics */
1552 int kpc_idle
; /* executing idle thread */
1553 int kpc_intr
; /* executing interrupt thread */
1554 int kpc_clock
; /* executing clock thread */
1555 int kpc_blocked
; /* thread has blocked preemption (t_preempt) */
1556 int kpc_notonproc
; /* thread is surrendering processor */
1557 int kpc_inswtch
; /* thread has ratified scheduling decision */
1558 int kpc_prilevel
; /* processor interrupt level is too high */
1559 int kpc_apreempt
; /* asynchronous preemption */
1560 int kpc_spreempt
; /* synchronous preemption */
1564 * kernel preemption: forced rescheduling, preempt the running kernel thread.
1565 * the argument is old PIL for an interrupt,
1566 * or the distingished value KPREEMPT_SYNC.
1569 kpreempt(int asyncspl
)
1571 kthread_t
*ct
= curthread
;
1573 if (IGNORE_KERNEL_PREEMPTION
) {
1574 aston(CPU
->cpu_dispthread
);
1579 * Check that conditions are right for kernel preemption
1582 if (ct
->t_preempt
) {
1584 * either a privileged thread (idle, panic, interrupt)
1585 * or will check when t_preempt is lowered
1586 * We need to specifically handle the case where
1587 * the thread is in the middle of swtch (resume has
1588 * been called) and has its t_preempt set
1589 * [idle thread and a thread which is in kpreempt
1590 * already] and then a high priority thread is
1591 * available in the local dispatch queue.
1592 * In this case the resumed thread needs to take a
1593 * trap so that it can call kpreempt. We achieve
1594 * this by using siron().
1595 * How do we detect this condition:
1596 * idle thread is running and is in the midst of
1597 * resume: curthread->t_pri == -1 && CPU->dispthread
1599 * Need to ensure that this happens only at high pil
1600 * resume is called at high pil
1601 * Only in resume_from_idle is the pil changed.
1603 if (ct
->t_pri
< 0) {
1604 kpreempt_cnts
.kpc_idle
++;
1605 if (CPU
->cpu_dispthread
!= CPU
->cpu_thread
)
1607 } else if (ct
->t_flag
& T_INTR_THREAD
) {
1608 kpreempt_cnts
.kpc_intr
++;
1609 if (ct
->t_pil
== CLOCK_LEVEL
)
1610 kpreempt_cnts
.kpc_clock
++;
1612 kpreempt_cnts
.kpc_blocked
++;
1613 if (CPU
->cpu_dispthread
!= CPU
->cpu_thread
)
1616 aston(CPU
->cpu_dispthread
);
1619 if (ct
->t_state
!= TS_ONPROC
||
1620 ct
->t_disp_queue
!= CPU
->cpu_disp
) {
1621 /* this thread will be calling swtch() shortly */
1622 kpreempt_cnts
.kpc_notonproc
++;
1623 if (CPU
->cpu_thread
!= CPU
->cpu_dispthread
) {
1624 /* already in swtch(), force another */
1625 kpreempt_cnts
.kpc_inswtch
++;
1630 if (getpil() >= DISP_LEVEL
) {
1632 * We can't preempt this thread if it is at
1633 * a PIL >= DISP_LEVEL since it may be holding
1634 * a spin lock (like sched_lock).
1636 siron(); /* check back later */
1637 kpreempt_cnts
.kpc_prilevel
++;
1640 if (!interrupts_enabled()) {
1642 * Can't preempt while running with ints disabled
1644 kpreempt_cnts
.kpc_prilevel
++;
1647 if (asyncspl
!= KPREEMPT_SYNC
)
1648 kpreempt_cnts
.kpc_apreempt
++;
1650 kpreempt_cnts
.kpc_spreempt
++;
1655 } while (CPU
->cpu_kprunrun
);
1659 * Print out debugging info.
1662 showregs(uint_t type
, struct regs
*rp
, caddr_t addr
)
1668 if (PTOU(curproc
)->u_comm
[0])
1669 printf("%s: ", PTOU(curproc
)->u_comm
);
1670 if (type
< TRAP_TYPES
)
1671 printf("#%s %s\n", trap_type_mnemonic
[type
], trap_type
[type
]);
1675 printf("Syscall Trap:\n");
1681 printf("Bad Trap = %d\n", type
);
1684 if (type
== T_PGFLT
) {
1685 printf("Bad %s fault at addr=0x%lx\n",
1686 USERMODE(rp
->r_cs
) ? "user": "kernel", (uintptr_t)addr
);
1688 printf("addr=0x%lx\n", (uintptr_t)addr
);
1691 printf("pid=%d, pc=0x%lx, sp=0x%lx, eflags=0x%lx\n",
1692 (ttoproc(curthread
) && ttoproc(curthread
)->p_pidp
) ?
1693 ttoproc(curthread
)->p_pid
: 0, rp
->r_pc
, rp
->r_sp
, rp
->r_ps
);
1695 printf("cr0: %b cr4: %b\n",
1696 (uint_t
)getcr0(), FMT_CR0
, (uint_t
)getcr4(), FMT_CR4
);
1698 printf("cr2: %lx ", getcr2());
1699 printf("cr3: %lx ", getcr3());
1700 #if defined(__amd64)
1701 printf("cr8: %lx\n", getcr8());
1710 dumpregs(struct regs
*rp
)
1712 #if defined(__amd64)
1713 const char fmt
[] = "\t%3s: %16lx %3s: %16lx %3s: %16lx\n";
1715 printf(fmt
, "rdi", rp
->r_rdi
, "rsi", rp
->r_rsi
, "rdx", rp
->r_rdx
);
1716 printf(fmt
, "rcx", rp
->r_rcx
, " r8", rp
->r_r8
, " r9", rp
->r_r9
);
1717 printf(fmt
, "rax", rp
->r_rax
, "rbx", rp
->r_rbx
, "rbp", rp
->r_rbp
);
1718 printf(fmt
, "r10", rp
->r_r10
, "r11", rp
->r_r11
, "r12", rp
->r_r12
);
1719 printf(fmt
, "r13", rp
->r_r13
, "r14", rp
->r_r14
, "r15", rp
->r_r15
);
1721 printf(fmt
, "fsb", rdmsr(MSR_AMD_FSBASE
), "gsb", rdmsr(MSR_AMD_GSBASE
),
1723 printf(fmt
, " es", rp
->r_es
, " fs", rp
->r_fs
, " gs", rp
->r_gs
);
1725 printf(fmt
, "trp", rp
->r_trapno
, "err", rp
->r_err
, "rip", rp
->r_rip
);
1726 printf(fmt
, " cs", rp
->r_cs
, "rfl", rp
->r_rfl
, "rsp", rp
->r_rsp
);
1728 printf("\t%3s: %16lx\n", " ss", rp
->r_ss
);
1730 #elif defined(__i386)
1731 const char fmt
[] = "\t%3s: %8lx %3s: %8lx %3s: %8lx %3s: %8lx\n";
1733 printf(fmt
, " gs", rp
->r_gs
, " fs", rp
->r_fs
,
1734 " es", rp
->r_es
, " ds", rp
->r_ds
);
1735 printf(fmt
, "edi", rp
->r_edi
, "esi", rp
->r_esi
,
1736 "ebp", rp
->r_ebp
, "esp", rp
->r_esp
);
1737 printf(fmt
, "ebx", rp
->r_ebx
, "edx", rp
->r_edx
,
1738 "ecx", rp
->r_ecx
, "eax", rp
->r_eax
);
1739 printf(fmt
, "trp", rp
->r_trapno
, "err", rp
->r_err
,
1740 "eip", rp
->r_eip
, " cs", rp
->r_cs
);
1741 printf("\t%3s: %8lx %3s: %8lx %3s: %8lx\n",
1742 "efl", rp
->r_efl
, "usp", rp
->r_uesp
, " ss", rp
->r_ss
);
1748 * Test to see if the instruction is iret on i386 or iretq on amd64.
1750 * On the hypervisor we can only test for nopop_sys_rtt_syscall. If true
1751 * then we are in the context of hypervisor's failsafe handler because it
1752 * tried to iret and failed due to a bad selector. See xen_failsafe_callback.
1755 instr_is_iret(caddr_t pc
)
1759 #if defined(__amd64)
1760 static const uint8_t iret_insn
[2] = { 0x48, 0xcf }; /* iretq */
1762 #elif defined(__i386)
1763 static const uint8_t iret_insn
[1] = { 0xcf }; /* iret */
1765 return (bcmp(pc
, iret_insn
, sizeof (iret_insn
)) == 0);
1772 * Test to see if the instruction is part of __SEGREGS_POP
1774 * Note carefully the appallingly awful dependency between
1775 * the instruction sequence used in __SEGREGS_POP and these
1776 * instructions encoded here.
1779 instr_is_segregs_pop(caddr_t pc
)
1781 static const uint8_t movw_0_esp_gs
[4] = { 0x8e, 0x6c, 0x24, 0x0 };
1782 static const uint8_t movw_4_esp_fs
[4] = { 0x8e, 0x64, 0x24, 0x4 };
1783 static const uint8_t movw_8_esp_es
[4] = { 0x8e, 0x44, 0x24, 0x8 };
1784 static const uint8_t movw_c_esp_ds
[4] = { 0x8e, 0x5c, 0x24, 0xc };
1786 if (bcmp(pc
, movw_0_esp_gs
, sizeof (movw_0_esp_gs
)) == 0 ||
1787 bcmp(pc
, movw_4_esp_fs
, sizeof (movw_4_esp_fs
)) == 0 ||
1788 bcmp(pc
, movw_8_esp_es
, sizeof (movw_8_esp_es
)) == 0 ||
1789 bcmp(pc
, movw_c_esp_ds
, sizeof (movw_c_esp_ds
)) == 0)
1798 * Test to see if the instruction is part of _sys_rtt (or the KPTI trampolines
1799 * which are used by _sys_rtt).
1801 * Again on the hypervisor if we try to IRET to user land with a bad code
1802 * or stack selector we will get vectored through xen_failsafe_callback.
1803 * In which case we assume we got here via _sys_rtt since we only allow
1804 * IRET to user land to take place in _sys_rtt.
1807 instr_is_sys_rtt(caddr_t pc
)
1809 extern void _sys_rtt(), _sys_rtt_end();
1812 extern void tr_sysc_ret_start(), tr_sysc_ret_end();
1813 extern void tr_intr_ret_start(), tr_intr_ret_end();
1815 if ((uintptr_t)pc
>= (uintptr_t)tr_sysc_ret_start
&&
1816 (uintptr_t)pc
<= (uintptr_t)tr_sysc_ret_end
)
1819 if ((uintptr_t)pc
>= (uintptr_t)tr_intr_ret_start
&&
1820 (uintptr_t)pc
<= (uintptr_t)tr_intr_ret_end
)
1824 if ((uintptr_t)pc
< (uintptr_t)_sys_rtt
||
1825 (uintptr_t)pc
> (uintptr_t)_sys_rtt_end
)
1832 * Handle #gp faults in kernel mode.
1834 * One legitimate way this can happen is if we attempt to update segment
1835 * registers to naughty values on the way out of the kernel.
1837 * This can happen in a couple of ways: someone - either accidentally or
1838 * on purpose - creates (setcontext(2), lwp_create(2)) or modifies
1839 * (signal(2)) a ucontext that contains silly segment register values.
1840 * Or someone - either accidentally or on purpose - modifies the prgregset_t
1841 * of a subject process via /proc to contain silly segment register values.
1843 * (The unfortunate part is that we can end up discovering the bad segment
1844 * register value in the middle of an 'iret' after we've popped most of the
1845 * stack. So it becomes quite difficult to associate an accurate ucontext
1846 * with the lwp, because the act of taking the #gp trap overwrites most of
1847 * what we were going to send the lwp.)
1849 * OTOH if it turns out that's -not- the problem, and we're -not- an lwp
1850 * trying to return to user mode and we get a #gp fault, then we need
1851 * to die() -- which will happen if we return non-zero from this routine.
1854 kern_gpfault(struct regs
*rp
)
1856 kthread_t
*t
= curthread
;
1857 proc_t
*p
= ttoproc(t
);
1858 klwp_t
*lwp
= ttolwp(t
);
1859 struct regs tmpregs
, *trp
= NULL
;
1860 caddr_t pc
= (caddr_t
)rp
->r_pc
;
1862 uint32_t auditing
= AU_AUDITING();
1865 * if we're not an lwp, or in the case of running native the
1866 * pc range is outside _sys_rtt, then we should immediately
1867 * be die()ing horribly.
1869 if (lwp
== NULL
|| !instr_is_sys_rtt(pc
))
1873 * So at least we're in the right part of the kernel.
1875 * Disassemble the instruction at the faulting pc.
1876 * Once we know what it is, we carefully reconstruct the stack
1877 * based on the order in which the stack is deconstructed in
1880 if (instr_is_iret(pc
)) {
1882 * We took the #gp while trying to perform the IRET.
1883 * This means that either %cs or %ss are bad.
1884 * All we know for sure is that most of the general
1885 * registers have been restored, including the
1886 * segment registers, and all we have left on the
1887 * topmost part of the lwp's stack are the
1888 * registers that the iretq was unable to consume.
1890 * All the rest of the state was crushed by the #gp
1891 * which pushed -its- registers atop our old save area
1892 * (because we had to decrement the stack pointer, sigh) so
1893 * all that we can try and do is to reconstruct the
1894 * crushed frame from the #gp trap frame itself.
1897 trp
->r_ss
= lwptoregs(lwp
)->r_ss
;
1898 trp
->r_sp
= lwptoregs(lwp
)->r_sp
;
1899 trp
->r_ps
= lwptoregs(lwp
)->r_ps
;
1900 trp
->r_cs
= lwptoregs(lwp
)->r_cs
;
1901 trp
->r_pc
= lwptoregs(lwp
)->r_pc
;
1902 bcopy(rp
, trp
, offsetof(struct regs
, r_pc
));
1905 * Validate simple math
1907 ASSERT(trp
->r_pc
== lwptoregs(lwp
)->r_pc
);
1908 ASSERT(trp
->r_err
== rp
->r_err
);
1914 #if defined(__amd64)
1915 if (trp
== NULL
&& lwp
->lwp_pcb
.pcb_rupdate
!= 0) {
1918 * This is the common case -- we're trying to load
1919 * a bad segment register value in the only section
1920 * of kernel code that ever loads segment registers.
1922 * We don't need to do anything at this point because
1923 * the pcb contains all the pending segment register
1924 * state, and the regs are still intact because we
1925 * didn't adjust the stack pointer yet. Given the fidelity
1926 * of all this, we could conceivably send a signal
1927 * to the lwp, rather than core-ing.
1929 trp
= lwptoregs(lwp
);
1930 ASSERT((caddr_t
)trp
== (caddr_t
)rp
->r_sp
);
1933 #elif defined(__i386)
1935 if (trp
== NULL
&& instr_is_segregs_pop(pc
))
1936 trp
= lwptoregs(lwp
);
1944 * If we get to here, we're reasonably confident that we've
1945 * correctly decoded what happened on the way out of the kernel.
1946 * Rewrite the lwp's registers so that we can create a core dump
1947 * the (at least vaguely) represents the mcontext we were
1948 * being asked to restore when things went so terribly wrong.
1952 * Make sure that we have a meaningful %trapno and %err.
1954 trp
->r_trapno
= rp
->r_trapno
;
1955 trp
->r_err
= rp
->r_err
;
1957 if ((caddr_t
)trp
!= (caddr_t
)lwptoregs(lwp
))
1958 bcopy(trp
, lwptoregs(lwp
), sizeof (*trp
));
1961 mutex_enter(&p
->p_lock
);
1962 lwp
->lwp_cursig
= SIGSEGV
;
1963 mutex_exit(&p
->p_lock
);
1966 * Terminate all LWPs but don't discard them. If another lwp beat
1967 * us to the punch by calling exit(), evaporate now.
1970 if (exitlwps(1) != 0) {
1971 mutex_enter(&p
->p_lock
);
1975 if (auditing
) /* audit core dump */
1976 audit_core_start(SIGSEGV
);
1977 v
= core(SIGSEGV
, B_FALSE
);
1978 if (auditing
) /* audit core dump */
1979 audit_core_finish(v
? CLD_KILLED
: CLD_DUMPED
);
1980 exit(v
? CLD_KILLED
: CLD_DUMPED
, SIGSEGV
);
1985 * dump_tss() - Display the TSS structure
1988 #if defined(__amd64)
1993 const char tss_fmt
[] = "tss.%s:\t0x%p\n"; /* Format string */
1994 tss_t
*tss
= CPU
->cpu_tss
;
1996 printf(tss_fmt
, "tss_rsp0", (void *)tss
->tss_rsp0
);
1997 printf(tss_fmt
, "tss_rsp1", (void *)tss
->tss_rsp1
);
1998 printf(tss_fmt
, "tss_rsp2", (void *)tss
->tss_rsp2
);
2000 printf(tss_fmt
, "tss_ist1", (void *)tss
->tss_ist1
);
2001 printf(tss_fmt
, "tss_ist2", (void *)tss
->tss_ist2
);
2002 printf(tss_fmt
, "tss_ist3", (void *)tss
->tss_ist3
);
2003 printf(tss_fmt
, "tss_ist4", (void *)tss
->tss_ist4
);
2004 printf(tss_fmt
, "tss_ist5", (void *)tss
->tss_ist5
);
2005 printf(tss_fmt
, "tss_ist6", (void *)tss
->tss_ist6
);
2006 printf(tss_fmt
, "tss_ist7", (void *)tss
->tss_ist7
);
2009 #elif defined(__i386)
2014 const char tss_fmt
[] = "tss.%s:\t0x%p\n"; /* Format string */
2015 tss_t
*tss
= CPU
->cpu_tss
;
2017 printf(tss_fmt
, "tss_link", (void *)(uintptr_t)tss
->tss_link
);
2018 printf(tss_fmt
, "tss_esp0", (void *)(uintptr_t)tss
->tss_esp0
);
2019 printf(tss_fmt
, "tss_ss0", (void *)(uintptr_t)tss
->tss_ss0
);
2020 printf(tss_fmt
, "tss_esp1", (void *)(uintptr_t)tss
->tss_esp1
);
2021 printf(tss_fmt
, "tss_ss1", (void *)(uintptr_t)tss
->tss_ss1
);
2022 printf(tss_fmt
, "tss_esp2", (void *)(uintptr_t)tss
->tss_esp2
);
2023 printf(tss_fmt
, "tss_ss2", (void *)(uintptr_t)tss
->tss_ss2
);
2024 printf(tss_fmt
, "tss_cr3", (void *)(uintptr_t)tss
->tss_cr3
);
2025 printf(tss_fmt
, "tss_eip", (void *)(uintptr_t)tss
->tss_eip
);
2026 printf(tss_fmt
, "tss_eflags", (void *)(uintptr_t)tss
->tss_eflags
);
2027 printf(tss_fmt
, "tss_eax", (void *)(uintptr_t)tss
->tss_eax
);
2028 printf(tss_fmt
, "tss_ebx", (void *)(uintptr_t)tss
->tss_ebx
);
2029 printf(tss_fmt
, "tss_ecx", (void *)(uintptr_t)tss
->tss_ecx
);
2030 printf(tss_fmt
, "tss_edx", (void *)(uintptr_t)tss
->tss_edx
);
2031 printf(tss_fmt
, "tss_esp", (void *)(uintptr_t)tss
->tss_esp
);
2034 #endif /* __amd64 */
2036 #if defined(TRAPTRACE)
2038 int ttrace_nrec
= 10; /* number of records to dump out */
2039 int ttrace_dump_nregs
= 0; /* dump out this many records with regs too */
2042 * Dump out the last ttrace_nrec traptrace records on each CPU
2047 trap_trace_ctl_t
*ttc
;
2048 trap_trace_rec_t
*rec
;
2052 #if defined(__amd64)
2053 const char banner
[] =
2054 "CPU ADDRESS TIMESTAMP TYPE VC HANDLER PC\n";
2055 /* Define format for the CPU, ADDRESS, and TIMESTAMP fields */
2056 const char fmt1
[] = "%3d %016lx %12llx";
2057 char data1
[34]; /* length of string formatted by fmt1 + 1 */
2058 #elif defined(__i386)
2059 const char banner
[] =
2060 "CPU ADDRESS TIMESTAMP TYPE VC HANDLER PC\n";
2061 /* Define format for the CPU, ADDRESS, and TIMESTAMP fields */
2062 const char fmt1
[] = "%3d %08lx %12llx";
2063 char data1
[26]; /* length of string formatted by fmt1 + 1 */
2065 /* Define format for the TYPE and VC fields */
2066 const char fmt2
[] = "%4s %3x";
2067 char data2
[9]; /* length of string formatted by fmt2 + 1 */
2069 * Define format for the HANDLER field. Width is arbitrary, but should
2070 * be enough for common handler's names, and leave enough space for
2071 * the PC field, especially when we are in kmdb.
2073 const char fmt3h
[] = "#%-15s";
2074 const char fmt3p
[] = "%-16p";
2075 const char fmt3s
[] = "%-16s";
2076 char data3
[17]; /* length of string formatted by fmt3* + 1 */
2078 if (ttrace_nrec
== 0)
2084 for (i
= 0; i
< n
; i
++) {
2085 ttc
= &trap_trace_ctl
[i
];
2086 if (ttc
->ttc_first
== (uintptr_t)NULL
)
2089 current
= ttc
->ttc_next
- sizeof (trap_trace_rec_t
);
2090 for (j
= 0; j
< ttrace_nrec
; j
++) {
2092 struct autovec
*vec
;
2093 extern struct av_head autovect
[];
2098 if (current
< ttc
->ttc_first
)
2100 ttc
->ttc_limit
- sizeof (trap_trace_rec_t
);
2102 if (current
== (uintptr_t)NULL
)
2105 rec
= (trap_trace_rec_t
*)current
;
2107 if (rec
->ttr_stamp
== 0)
2110 (void) snprintf(data1
, sizeof (data1
), fmt1
, i
,
2111 (uintptr_t)rec
, rec
->ttr_stamp
);
2113 switch (rec
->ttr_marker
) {
2118 sys
= &sysent32
[rec
->ttr_sysnum
];
2119 switch (rec
->ttr_marker
) {
2121 sys
= &sysent
[rec
->ttr_sysnum
];
2124 stype
= "sysc"; /* syscall */
2127 stype
= "lcal"; /* lcall */
2130 stype
= "syse"; /* sysenter */
2135 (void) snprintf(data2
, sizeof (data2
), fmt2
,
2136 stype
, rec
->ttr_sysnum
);
2138 sym
= kobj_getsymname(
2139 (uintptr_t)sys
->sy_callc
,
2142 (void) snprintf(data3
,
2143 sizeof (data3
), fmt3s
, sym
);
2145 (void) snprintf(data3
,
2146 sizeof (data3
), fmt3p
,
2150 (void) snprintf(data3
, sizeof (data3
),
2156 (void) snprintf(data2
, sizeof (data2
), fmt2
,
2157 "intr", rec
->ttr_vector
);
2158 if (get_intr_handler
!= NULL
)
2159 vec
= (struct autovec
*)
2161 (rec
->ttr_cpuid
, rec
->ttr_vector
);
2164 autovect
[rec
->ttr_vector
].avh_link
;
2167 sym
= kobj_getsymname(
2168 (uintptr_t)vec
->av_vector
, &off
);
2170 (void) snprintf(data3
,
2171 sizeof (data3
), fmt3s
, sym
);
2173 (void) snprintf(data3
,
2174 sizeof (data3
), fmt3p
,
2178 (void) snprintf(data3
, sizeof (data3
),
2185 type
= rec
->ttr_regs
.r_trapno
;
2186 (void) snprintf(data2
, sizeof (data2
), fmt2
,
2188 if (type
< TRAP_TYPES
) {
2189 (void) snprintf(data3
, sizeof (data3
),
2190 fmt3h
, trap_type_mnemonic
[type
]);
2194 (void) snprintf(data3
,
2195 sizeof (data3
), fmt3s
,
2199 (void) snprintf(data3
,
2200 sizeof (data3
), fmt3s
, "");
2210 sym
= kobj_getsymname(rec
->ttr_regs
.r_pc
, &off
);
2212 printf("%s %s %s %s+%lx\n", data1
, data2
, data3
,
2215 printf("%s %s %s %lx\n", data1
, data2
, data3
,
2216 rec
->ttr_regs
.r_pc
);
2219 if (ttrace_dump_nregs
-- > 0) {
2222 if (rec
->ttr_marker
== TT_INTERRUPT
)
2224 "\t\tipl %x spl %x pri %x\n",
2229 dumpregs(&rec
->ttr_regs
);
2231 printf("\t%3s: %p\n\n", " ct",
2232 (void *)rec
->ttr_curthread
);
2235 * print out the pc stack that we recorded
2236 * at trap time (if any)
2238 for (s
= 0; s
< rec
->ttr_sdepth
; s
++) {
2241 if (s
>= TTR_STACK_DEPTH
) {
2242 printf("ttr_sdepth corrupt\n");
2246 fullpc
= (uintptr_t)rec
->ttr_stack
[s
];
2248 sym
= kobj_getsymname(fullpc
, &off
);
2250 printf("-> %s+0x%lx()\n",
2253 printf("-> 0x%lx()\n", fullpc
);
2257 current
-= sizeof (trap_trace_rec_t
);
2262 #endif /* TRAPTRACE */
2265 panic_showtrap(struct panic_trap_info
*tip
)
2267 showregs(tip
->trap_type
, tip
->trap_regs
, tip
->trap_addr
);
2269 #if defined(TRAPTRACE)
2273 if (tip
->trap_type
== T_DBLFLT
)
2278 panic_savetrap(panic_data_t
*pdp
, struct panic_trap_info
*tip
)
2280 panic_saveregs(pdp
, tip
->trap_regs
);