4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
23 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
26 * Copyright (c) 2010, Intel Corporation.
27 * All rights reserved.
30 * Copyright 2018 Joyent, Inc.
31 * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
32 * Copyright 2018 OmniOS Community Edition (OmniOSce) Association.
35 #include <sys/types.h>
36 #include <sys/thread.h>
37 #include <sys/cpuvar.h>
39 #include <sys/t_lock.h>
40 #include <sys/param.h>
43 #include <sys/class.h>
44 #include <sys/cmn_err.h>
45 #include <sys/debug.h>
47 #include <sys/asm_linkage.h>
48 #include <sys/x_call.h>
49 #include <sys/systm.h>
51 #include <sys/vtrace.h>
54 #include <vm/seg_kmem.h>
55 #include <vm/seg_kp.h>
56 #include <sys/segments.h>
58 #include <sys/stack.h>
59 #include <sys/smp_impldefs.h>
60 #include <sys/x86_archext.h>
61 #include <sys/machsystm.h>
62 #include <sys/traptrace.h>
63 #include <sys/clock.h>
64 #include <sys/cpc_impl.h>
67 #include <sys/dtrace.h>
68 #include <sys/archsystm.h>
70 #include <sys/reboot.h>
71 #include <sys/kdi_machimpl.h>
72 #include <vm/hat_i86.h>
73 #include <vm/vm_dep.h>
74 #include <sys/memnode.h>
75 #include <sys/pci_cfgspace.h>
76 #include <sys/mach_mmu.h>
77 #include <sys/sysmacros.h>
78 #include <sys/cpu_module.h>
79 #include <sys/ontrap.h>
81 struct cpu cpus
[1] __aligned(MMU_PAGESIZE
);
82 struct cpu
*cpu
[NCPU
] = {&cpus
[0]};
83 struct cpu
*cpu_free_list
;
84 cpu_core_t cpu_core
[NCPU
];
86 #define cpu_next_free cpu_prev
89 * Useful for disabling MP bring-up on a MP capable system.
94 * to be set by a PSM to indicate what cpus
95 * are sitting around on the system.
100 * This variable is used by the hat layer to decide whether or not
101 * critical sections are needed to prevent race conditions. For sun4m,
102 * this variable is set once enough MP initialization has been done in
103 * order to allow cross calls.
105 int flushes_require_xcalls
;
107 cpuset_t cpu_ready_set
; /* initialized in startup() */
109 static void mp_startup_boot(void);
110 static void mp_startup_hotplug(void);
112 static void cpu_sep_enable(void);
113 static void cpu_sep_disable(void);
114 static void cpu_asysc_enable(void);
115 static void cpu_asysc_disable(void);
118 * Init CPU info - get CPU type info for processor_info system call.
121 init_cpu_info(struct cpu
*cp
)
123 processor_info_t
*pi
= &cp
->cpu_type_info
;
126 * Get clock-frequency property for the CPU.
128 pi
->pi_clock
= cpu_freq
;
131 * Current frequency in Hz.
133 cp
->cpu_curr_clock
= cpu_freq_hz
;
136 * Supported frequencies.
138 if (cp
->cpu_supp_freqs
== NULL
) {
139 cpu_set_supp_freqs(cp
, NULL
);
142 (void) strcpy(pi
->pi_processor_type
, "i386");
144 (void) strcpy(pi
->pi_fputypes
, "i387 compatible");
146 cp
->cpu_idstr
= kmem_zalloc(CPU_IDSTRLEN
, KM_SLEEP
);
147 cp
->cpu_brandstr
= kmem_zalloc(CPU_IDSTRLEN
, KM_SLEEP
);
150 * If called for the BSP, cp is equal to current CPU.
151 * For non-BSPs, cpuid info of cp is not ready yet, so use cpuid info
152 * of current CPU as default values for cpu_idstr and cpu_brandstr.
153 * They will be corrected in mp_startup_common() after cpuid_pass1()
154 * has been invoked on target CPU.
156 (void) cpuid_getidstr(CPU
, cp
->cpu_idstr
, CPU_IDSTRLEN
);
157 (void) cpuid_getbrandstr(CPU
, cp
->cpu_brandstr
, CPU_IDSTRLEN
);
161 * Configure syscall support on this CPU.
165 init_cpu_syscall(struct cpu
*cp
)
169 if (is_x86_feature(x86_featureset
, X86FSET_MSR
) &&
170 is_x86_feature(x86_featureset
, X86FSET_ASYSC
)) {
174 * The syscall instruction imposes a certain ordering on
175 * segment selectors, so we double-check that ordering
178 CTASSERT(KDS_SEL
== KCS_SEL
+ 8);
179 CTASSERT(UDS_SEL
== U32CS_SEL
+ 8);
180 CTASSERT(UCS_SEL
== U32CS_SEL
+ 16);
183 * Turn syscall/sysret extensions on.
188 * Program the magic registers ..
191 ((uint64_t)(U32CS_SEL
<< 16 | KCS_SEL
)) << 32);
192 if (kpti_enable
== 1) {
194 (uint64_t)(uintptr_t)tr_sys_syscall
);
196 (uint64_t)(uintptr_t)tr_sys_syscall32
);
199 (uint64_t)(uintptr_t)sys_syscall
);
201 (uint64_t)(uintptr_t)sys_syscall32
);
205 * This list of flags is masked off the incoming
206 * %rfl when we enter the kernel.
208 flags
= PS_IE
| PS_T
;
209 if (is_x86_feature(x86_featureset
, X86FSET_SMAP
) == B_TRUE
)
211 wrmsr(MSR_AMD_SFMASK
, flags
);
215 * On 64-bit kernels on Nocona machines, the 32-bit syscall
216 * variant isn't available to 32-bit applications, but sysenter is.
218 if (is_x86_feature(x86_featureset
, X86FSET_MSR
) &&
219 is_x86_feature(x86_featureset
, X86FSET_SEP
)) {
222 * The sysenter instruction imposes a certain ordering on
223 * segment selectors, so we double-check that ordering
224 * here. See "sysenter" in Intel document 245471-012, "IA-32
225 * Intel Architecture Software Developer's Manual Volume 2:
226 * Instruction Set Reference"
228 CTASSERT(KDS_SEL
== KCS_SEL
+ 8);
230 CTASSERT(U32CS_SEL
== ((KCS_SEL
+ 16) | 3));
231 CTASSERT(UDS_SEL
== U32CS_SEL
+ 8);
236 * resume() sets this value to the base of the threads stack
237 * via a context handler.
239 wrmsr(MSR_INTC_SEP_ESP
, 0);
241 if (kpti_enable
== 1) {
242 wrmsr(MSR_INTC_SEP_EIP
,
243 (uint64_t)(uintptr_t)tr_sys_sysenter
);
245 wrmsr(MSR_INTC_SEP_EIP
,
246 (uint64_t)(uintptr_t)sys_sysenter
);
254 * Configure per-cpu ID GDT
257 init_cpu_id_gdt(struct cpu
*cp
)
259 /* Write cpu_id into limit field of GDT for usermode retrieval */
261 set_usegd(&cp
->cpu_gdt
[GDT_CPUID
], SDP_SHORT
, NULL
, cp
->cpu_id
,
262 SDT_MEMRODA
, SEL_UPL
, SDP_BYTES
, SDP_OP32
);
263 #elif defined(__i386)
264 set_usegd(&cp
->cpu_gdt
[GDT_CPUID
], NULL
, cp
->cpu_id
, SDT_MEMRODA
,
265 SEL_UPL
, SDP_BYTES
, SDP_OP32
);
270 * Multiprocessor initialization.
272 * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the
273 * startup and idle threads for the specified CPU.
274 * Parameter boot is true for boot time operations and is false for CPU
278 mp_cpu_configure_common(int cpun
, boolean_t boot
)
284 extern int idle_cpu_prefer_mwait
;
285 extern void cpu_idle_mwait();
287 extern void cpu_idle();
290 trap_trace_ctl_t
*ttc
= &trap_trace_ctl
[cpun
];
293 ASSERT(MUTEX_HELD(&cpu_lock
));
294 ASSERT(cpun
< NCPU
&& cpu
[cpun
] == NULL
);
296 if (cpu_free_list
== NULL
) {
297 cp
= kmem_zalloc(sizeof (*cp
), KM_SLEEP
);
300 cpu_free_list
= cp
->cpu_next_free
;
303 cp
->cpu_m
.mcpu_istamp
= cpun
<< 16;
305 /* Create per CPU specific threads in the process p0. */
309 * Initialize the dispatcher first.
313 cpu_vm_data_init(cp
);
316 * Allocate and initialize the startup thread for this CPU.
317 * Interrupt and process switch stacks get allocated later
318 * when the CPU starts running.
320 tp
= thread_create(NULL
, 0, NULL
, NULL
, 0, procp
,
321 TS_STOPPED
, maxclsyspri
);
324 * Set state to TS_ONPROC since this thread will start running
325 * as soon as the CPU comes online.
327 * All the other fields of the thread structure are setup by
330 THREAD_ONPROC(tp
, cp
);
332 tp
->t_bound_cpu
= cp
;
333 tp
->t_affinitycnt
= 1;
335 tp
->t_disp_queue
= cp
->cpu_disp
;
338 * Setup thread to start in mp_startup_common.
341 tp
->t_sp
= (uintptr_t)(sp
- MINFRAME
);
343 tp
->t_sp
-= STACK_ENTRY_ALIGN
; /* fake a call */
346 * Setup thread start entry point for boot or hotplug.
349 tp
->t_pc
= (uintptr_t)mp_startup_boot
;
351 tp
->t_pc
= (uintptr_t)mp_startup_hotplug
;
358 cp
->cpu_dispthread
= tp
;
359 cp
->cpu_dispatch_pri
= DISP_PRIO(tp
);
362 * cpu_base_spl must be set explicitly here to prevent any blocking
363 * operations in mp_startup_common from causing the spl of the cpu
364 * to drop to 0 (allowing device interrupts before we're ready) in
366 * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY.
367 * As an extra bit of security on DEBUG kernels, this is enforced with
368 * an assertion in mp_startup_common() -- before cpu_base_spl is set
369 * to its proper value.
371 cp
->cpu_base_spl
= ipltospl(LOCK_LEVEL
);
374 * Now, initialize per-CPU idle thread for this CPU.
376 tp
= thread_create(NULL
, PAGESIZE
, idle
, NULL
, 0, procp
, TS_ONPROC
, -1);
378 cp
->cpu_idle_thread
= tp
;
381 tp
->t_bound_cpu
= cp
;
382 tp
->t_affinitycnt
= 1;
384 tp
->t_disp_queue
= cp
->cpu_disp
;
387 * Bootstrap the CPU's PG data
389 pg_cpu_bootstrap(cp
);
392 * Perform CPC initialization on the new CPU.
397 * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2
400 setup_vaddr_for_ppcopy(cp
);
403 * Allocate page for new GDT and initialize from current GDT.
405 ASSERT((sizeof (*cp
->cpu_gdt
) * NGDT
) <= PAGESIZE
);
406 cp
->cpu_gdt
= kmem_zalloc(PAGESIZE
, KM_SLEEP
);
407 bcopy(CPU
->cpu_gdt
, cp
->cpu_gdt
, (sizeof (*cp
->cpu_gdt
) * NGDT
));
413 set_usegd(&cp
->cpu_gdt
[GDT_GS
], cp
, sizeof (struct cpu
) -1, SDT_MEMRWA
,
418 * Allocate pages for the CPU LDT.
420 cp
->cpu_m
.mcpu_ldt
= kmem_zalloc(LDT_CPU_SIZE
, KM_SLEEP
);
421 cp
->cpu_m
.mcpu_ldt_len
= 0;
424 * Allocate a per-CPU IDT and initialize the new IDT to the currently
427 ASSERT((sizeof (*CPU
->cpu_idt
) * NIDT
) <= PAGESIZE
);
428 cp
->cpu_idt
= kmem_alloc(PAGESIZE
, KM_SLEEP
);
429 bcopy(CPU
->cpu_idt
, cp
->cpu_idt
, PAGESIZE
);
432 * alloc space for cpuid info
434 cpuid_alloc_space(cp
);
436 if (is_x86_feature(x86_featureset
, X86FSET_MWAIT
) &&
437 idle_cpu_prefer_mwait
) {
438 VERIFY0(cpuid_mwait_alloc(cp
));
439 cp
->cpu_m
.mcpu_idle_cpu
= cpu_idle_mwait
;
441 cp
->cpu_m
.mcpu_idle_cpu
= cpu_idle
;
448 * alloc space for ucode_info
450 ucode_alloc_space(cp
);
456 * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers
458 ttc
->ttc_first
= (uintptr_t)kmem_zalloc(trap_trace_bufsize
, KM_SLEEP
);
459 ttc
->ttc_next
= ttc
->ttc_first
;
460 ttc
->ttc_limit
= ttc
->ttc_first
+ trap_trace_bufsize
;
464 * Record that we have another CPU.
467 * Initialize the interrupt threads for this CPU
469 cpu_intr_alloc(cp
, NINTR_THREADS
);
471 cp
->cpu_flags
= CPU_OFFLINE
| CPU_QUIESCED
| CPU_POWEROFF
;
475 * Add CPU to list of available CPUs. It'll be on the active list
476 * after mp_startup_common().
484 * Undo what was done in mp_cpu_configure_common
487 mp_cpu_unconfigure_common(struct cpu
*cp
, int error
)
489 ASSERT(MUTEX_HELD(&cpu_lock
));
492 * Remove the CPU from the list of available CPUs.
494 cpu_del_unit(cp
->cpu_id
);
496 if (error
== ETIMEDOUT
) {
498 * The cpu was started, but never *seemed* to run any
499 * code in the kernel; it's probably off spinning in its
500 * own private world, though with potential references to
501 * our kmem-allocated IDTs and GDTs (for example).
503 * Worse still, it may actually wake up some time later,
504 * so rather than guess what it might or might not do, we
505 * leave the fundamental data structures intact.
512 * At this point, the only threads bound to this CPU should
513 * special per-cpu threads: it's idle thread, it's pause threads,
514 * and it's interrupt threads. Clean these up.
516 cpu_destroy_bound_threads(cp
);
517 cp
->cpu_idle_thread
= NULL
;
520 * Free the interrupt stack.
523 cp
->cpu_intr_stack
- (INTR_STACK_SIZE
- SA(MINFRAME
)));
524 cp
->cpu_intr_stack
= NULL
;
528 * Discard the trap trace buffer
531 trap_trace_ctl_t
*ttc
= &trap_trace_ctl
[cp
->cpu_id
];
533 kmem_free((void *)ttc
->ttc_first
, trap_trace_bufsize
);
534 ttc
->ttc_first
= (uintptr_t)NULL
;
540 ucode_free_space(cp
);
542 /* Free CPU ID string and brand string. */
544 kmem_free(cp
->cpu_idstr
, CPU_IDSTRLEN
);
545 cp
->cpu_idstr
= NULL
;
547 if (cp
->cpu_brandstr
) {
548 kmem_free(cp
->cpu_brandstr
, CPU_IDSTRLEN
);
549 cp
->cpu_brandstr
= NULL
;
552 if (cp
->cpu_m
.mcpu_mwait
!= NULL
) {
553 cpuid_mwait_free(cp
);
554 cp
->cpu_m
.mcpu_mwait
= NULL
;
556 cpuid_free_space(cp
);
558 if (cp
->cpu_idt
!= CPU
->cpu_idt
)
559 kmem_free(cp
->cpu_idt
, PAGESIZE
);
562 kmem_free(cp
->cpu_m
.mcpu_ldt
, LDT_CPU_SIZE
);
563 cp
->cpu_m
.mcpu_ldt
= NULL
;
564 cp
->cpu_m
.mcpu_ldt_len
= 0;
566 kmem_free(cp
->cpu_gdt
, PAGESIZE
);
569 if (cp
->cpu_supp_freqs
!= NULL
) {
570 size_t len
= strlen(cp
->cpu_supp_freqs
) + 1;
571 kmem_free(cp
->cpu_supp_freqs
, len
);
572 cp
->cpu_supp_freqs
= NULL
;
575 teardown_vaddr_for_ppcopy(cp
);
579 cp
->cpu_dispthread
= NULL
;
580 cp
->cpu_thread
= NULL
; /* discarded by cpu_destroy_bound_threads() */
582 cpu_vm_data_destroy(cp
);
588 bzero(cp
, sizeof (*cp
));
589 cp
->cpu_next_free
= cpu_free_list
;
594 * Apply workarounds for known errata, and warn about those that are absent.
596 * System vendors occasionally create configurations which contain different
597 * revisions of the CPUs that are almost but not exactly the same. At the
598 * time of writing, this meant that their clock rates were the same, their
599 * feature sets were the same, but the required workaround were -not-
600 * necessarily the same. So, this routine is invoked on -every- CPU soon
601 * after starting to make sure that the resulting system contains the most
602 * pessimal set of workarounds needed to cope with *any* of the CPUs in the
605 * workaround_errata is invoked early in mlsetup() for CPU 0, and in
606 * mp_startup_common() for all slave CPUs. Slaves process workaround_errata
607 * prior to acknowledging their readiness to the master, so this routine will
608 * never be executed by multiple CPUs in parallel, thus making updates to
611 * These workarounds are based on Rev 3.57 of the Revision Guide for
612 * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005.
615 #if defined(OPTERON_ERRATUM_88)
616 int opteron_erratum_88
; /* if non-zero -> at least one cpu has it */
619 #if defined(OPTERON_ERRATUM_91)
620 int opteron_erratum_91
; /* if non-zero -> at least one cpu has it */
623 #if defined(OPTERON_ERRATUM_93)
624 int opteron_erratum_93
; /* if non-zero -> at least one cpu has it */
627 #if defined(OPTERON_ERRATUM_95)
628 int opteron_erratum_95
; /* if non-zero -> at least one cpu has it */
631 #if defined(OPTERON_ERRATUM_100)
632 int opteron_erratum_100
; /* if non-zero -> at least one cpu has it */
635 #if defined(OPTERON_ERRATUM_108)
636 int opteron_erratum_108
; /* if non-zero -> at least one cpu has it */
639 #if defined(OPTERON_ERRATUM_109)
640 int opteron_erratum_109
; /* if non-zero -> at least one cpu has it */
643 #if defined(OPTERON_ERRATUM_121)
644 int opteron_erratum_121
; /* if non-zero -> at least one cpu has it */
647 #if defined(OPTERON_ERRATUM_122)
648 int opteron_erratum_122
; /* if non-zero -> at least one cpu has it */
651 #if defined(OPTERON_ERRATUM_123)
652 int opteron_erratum_123
; /* if non-zero -> at least one cpu has it */
655 #if defined(OPTERON_ERRATUM_131)
656 int opteron_erratum_131
; /* if non-zero -> at least one cpu has it */
659 #if defined(OPTERON_WORKAROUND_6336786)
660 int opteron_workaround_6336786
; /* non-zero -> WA relevant and applied */
661 int opteron_workaround_6336786_UP
= 0; /* Not needed for UP */
664 #if defined(OPTERON_WORKAROUND_6323525)
665 int opteron_workaround_6323525
; /* if non-zero -> at least one cpu has it */
668 #if defined(OPTERON_ERRATUM_298)
669 int opteron_erratum_298
;
672 #if defined(OPTERON_ERRATUM_721)
673 int opteron_erratum_721
;
677 workaround_warning(cpu_t
*cp
, uint_t erratum
)
679 cmn_err(CE_WARN
, "cpu%d: no workaround for erratum %u",
680 cp
->cpu_id
, erratum
);
684 workaround_applied(uint_t erratum
)
686 if (erratum
> 1000000)
687 cmn_err(CE_CONT
, "?workaround applied for cpu issue #%d\n",
690 cmn_err(CE_CONT
, "?workaround applied for cpu erratum #%d\n",
695 msr_warning(cpu_t
*cp
, const char *rw
, uint_t msr
, int error
)
697 cmn_err(CE_WARN
, "cpu%d: couldn't %smsr 0x%x, error %d",
698 cp
->cpu_id
, rw
, msr
, error
);
702 * Determine the number of nodes in a Hammer / Greyhound / Griffin family
706 opteron_get_nnodes(void)
708 static uint_t nnodes
= 0;
715 * This routine uses a PCI config space based mechanism
716 * for retrieving the number of nodes in the system.
717 * Device 24, function 0, offset 0x60 as used here is not
718 * AMD processor architectural, and may not work on processor
719 * families other than those listed below.
721 * Callers of this routine must ensure that we're running on
722 * a processor which supports this mechanism.
723 * The assertion below is meant to catch calls on unsupported
726 family
= cpuid_getfamily(CPU
);
727 ASSERT(family
== 0xf || family
== 0x10 || family
== 0x11);
731 * Obtain the number of nodes in the system from
732 * bits [6:4] of the Node ID register on node 0.
734 * The actual node count is NodeID[6:4] + 1
736 * The Node ID register is accessed via function 0,
737 * offset 0x60. Node 0 is device 24.
739 nnodes
= ((pci_getl_func(0, 24, 0, 0x60) & 0x70) >> 4) + 1;
745 do_erratum_298(struct cpu
*cpu
)
747 static int osvwrc
= -3;
748 extern int osvw_opteron_erratum(cpu_t
*, uint_t
);
751 * L2 Eviction May Occur During Processor Operation To Set
752 * Accessed or Dirty Bit.
755 osvwrc
= osvw_opteron_erratum(cpu
, 298);
757 /* osvw return codes should be consistent for all cpus */
758 ASSERT(osvwrc
== osvw_opteron_erratum(cpu
, 298));
762 case 0: /* erratum is not present: do nothing */
764 case 1: /* erratum is present: BIOS workaround applied */
766 * check if workaround is actually in place and issue warning
769 if (((rdmsr(MSR_AMD_HWCR
) & AMD_HWCR_TLBCACHEDIS
) == 0) ||
770 ((rdmsr(MSR_AMD_BU_CFG
) & AMD_BU_CFG_E298
) == 0)) {
771 #if defined(OPTERON_ERRATUM_298)
772 opteron_erratum_298
++;
774 workaround_warning(cpu
, 298);
779 case -1: /* cannot determine via osvw: check cpuid */
780 if ((cpuid_opteron_erratum(cpu
, 298) > 0) &&
781 (((rdmsr(MSR_AMD_HWCR
) & AMD_HWCR_TLBCACHEDIS
) == 0) ||
782 ((rdmsr(MSR_AMD_BU_CFG
) & AMD_BU_CFG_E298
) == 0))) {
783 #if defined(OPTERON_ERRATUM_298)
784 opteron_erratum_298
++;
786 workaround_warning(cpu
, 298);
796 workaround_errata(struct cpu
*cpu
)
803 if (cpuid_opteron_erratum(cpu
, 88) > 0) {
805 * SWAPGS May Fail To Read Correct GS Base
807 #if defined(OPTERON_ERRATUM_88)
809 * The workaround is an mfence in the relevant assembler code
811 opteron_erratum_88
++;
813 workaround_warning(cpu
, 88);
818 if (cpuid_opteron_erratum(cpu
, 91) > 0) {
820 * Software Prefetches May Report A Page Fault
822 #if defined(OPTERON_ERRATUM_91)
826 opteron_erratum_91
++;
828 workaround_warning(cpu
, 91);
833 if (cpuid_opteron_erratum(cpu
, 93) > 0) {
835 * RSM Auto-Halt Restart Returns to Incorrect RIP
837 #if defined(OPTERON_ERRATUM_93)
841 opteron_erratum_93
++;
843 workaround_warning(cpu
, 93);
849 if (cpuid_opteron_erratum(cpu
, 95) > 0) {
851 * RET Instruction May Return to Incorrect EIP
853 #if defined(OPTERON_ERRATUM_95)
856 * Workaround this by ensuring that 32-bit user code and
857 * 64-bit kernel code never occupy the same address
860 if (_userlimit32
> 0xc0000000ul
)
861 *(uintptr_t *)&_userlimit32
= 0xc0000000ul
;
864 ASSERT((uint32_t)COREHEAP_BASE
== 0xc0000000u
);
865 opteron_erratum_95
++;
868 workaround_warning(cpu
, 95);
873 if (cpuid_opteron_erratum(cpu
, 100) > 0) {
875 * Compatibility Mode Branches Transfer to Illegal Address
877 #if defined(OPTERON_ERRATUM_100)
881 opteron_erratum_100
++;
883 workaround_warning(cpu
, 100);
889 if (cpuid_opteron_erratum(cpu
, 108) > 0) {
891 * CPUID Instruction May Return Incorrect Model Number In
894 #if defined(OPTERON_ERRATUM_108)
896 * (Our cpuid-handling code corrects the model number on
900 workaround_warning(cpu
, 108);
906 if (cpuid_opteron_erratum(cpu
, 109) > 0) do {
908 * Certain Reverse REP MOVS May Produce Unpredictable Behavior
910 #if defined(OPTERON_ERRATUM_109)
912 * The "workaround" is to print a warning to upgrade the BIOS
915 const uint_t msr
= MSR_AMD_PATCHLEVEL
;
918 if ((err
= checked_rdmsr(msr
, &value
)) != 0) {
919 msr_warning(cpu
, "rd", msr
, err
);
920 workaround_warning(cpu
, 109);
924 opteron_erratum_109
++;
926 workaround_warning(cpu
, 109);
929 /*CONSTANTCONDITION*/
933 if (cpuid_opteron_erratum(cpu
, 121) > 0) {
935 * Sequential Execution Across Non_Canonical Boundary Caused
938 #if defined(OPTERON_ERRATUM_121)
941 * Erratum 121 is only present in long (64 bit) mode.
942 * Workaround is to include the page immediately before the
943 * va hole to eliminate the possibility of system hangs due to
944 * sequential execution across the va hole boundary.
946 if (opteron_erratum_121
)
947 opteron_erratum_121
++;
950 hole_start
-= PAGESIZE
;
953 * hole_start not yet initialized by
954 * mmu_init. Initialize hole_start
955 * with value to be subtracted.
957 hole_start
= PAGESIZE
;
959 opteron_erratum_121
++;
963 workaround_warning(cpu
, 121);
969 if (cpuid_opteron_erratum(cpu
, 122) > 0) do {
971 * TLB Flush Filter May Cause Coherency Problem in
972 * Multiprocessor Systems
974 #if defined(OPTERON_ERRATUM_122)
976 const uint_t msr
= MSR_AMD_HWCR
;
980 * Erratum 122 is only present in MP configurations (multi-core
981 * or multi-processor).
984 if (!DOMAIN_IS_INITDOMAIN(xen_info
))
986 if (!opteron_erratum_122
&& xpv_nr_phys_cpus() == 1)
989 if (!opteron_erratum_122
&& opteron_get_nnodes() == 1 &&
990 cpuid_get_ncpu_per_chip(cpu
) == 1)
993 /* disable TLB Flush Filter */
995 if ((error
= checked_rdmsr(msr
, &value
)) != 0) {
996 msr_warning(cpu
, "rd", msr
, error
);
997 workaround_warning(cpu
, 122);
1000 value
|= (uint64_t)AMD_HWCR_FFDIS
;
1001 if ((error
= checked_wrmsr(msr
, value
)) != 0) {
1002 msr_warning(cpu
, "wr", msr
, error
);
1003 workaround_warning(cpu
, 122);
1007 opteron_erratum_122
++;
1009 workaround_warning(cpu
, 122);
1012 /*CONSTANTCONDITION*/
1016 if (cpuid_opteron_erratum(cpu
, 123) > 0) do {
1018 * Bypassed Reads May Cause Data Corruption of System Hang in
1019 * Dual Core Processors
1021 #if defined(OPTERON_ERRATUM_123)
1023 const uint_t msr
= MSR_AMD_PATCHLEVEL
;
1027 * Erratum 123 applies only to multi-core cpus.
1029 if (cpuid_get_ncpu_per_chip(cpu
) < 2)
1032 if (!DOMAIN_IS_INITDOMAIN(xen_info
))
1036 * The "workaround" is to print a warning to upgrade the BIOS
1038 if ((err
= checked_rdmsr(msr
, &value
)) != 0) {
1039 msr_warning(cpu
, "rd", msr
, err
);
1040 workaround_warning(cpu
, 123);
1044 opteron_erratum_123
++;
1046 workaround_warning(cpu
, 123);
1050 /*CONSTANTCONDITION*/
1054 if (cpuid_opteron_erratum(cpu
, 131) > 0) do {
1056 * Multiprocessor Systems with Four or More Cores May Deadlock
1057 * Waiting for a Probe Response
1059 #if defined(OPTERON_ERRATUM_131)
1061 const uint_t msr
= MSR_AMD_NB_CFG
;
1062 const uint64_t wabits
=
1063 AMD_NB_CFG_SRQ_HEARTBEAT
| AMD_NB_CFG_SRQ_SPR
;
1067 * Erratum 131 applies to any system with four or more cores.
1069 if (opteron_erratum_131
)
1072 if (!DOMAIN_IS_INITDOMAIN(xen_info
))
1074 if (xpv_nr_phys_cpus() < 4)
1077 if (opteron_get_nnodes() * cpuid_get_ncpu_per_chip(cpu
) < 4)
1081 * Print a warning if neither of the workarounds for
1082 * erratum 131 is present.
1084 if ((error
= checked_rdmsr(msr
, &nbcfg
)) != 0) {
1085 msr_warning(cpu
, "rd", msr
, error
);
1086 workaround_warning(cpu
, 131);
1088 } else if ((nbcfg
& wabits
) == 0) {
1089 opteron_erratum_131
++;
1091 /* cannot have both workarounds set */
1092 ASSERT((nbcfg
& wabits
) != wabits
);
1095 workaround_warning(cpu
, 131);
1098 /*CONSTANTCONDITION*/
1102 * This isn't really an erratum, but for convenience the
1103 * detection/workaround code lives here and in cpuid_opteron_erratum.
1105 if (cpuid_opteron_erratum(cpu
, 6336786) > 0) {
1106 #if defined(OPTERON_WORKAROUND_6336786)
1108 * Disable C1-Clock ramping on multi-core/multi-processor
1109 * K8 platforms to guard against TSC drift.
1111 if (opteron_workaround_6336786
) {
1112 opteron_workaround_6336786
++;
1114 } else if ((DOMAIN_IS_INITDOMAIN(xen_info
) &&
1115 xpv_nr_phys_cpus() > 1) ||
1116 opteron_workaround_6336786_UP
) {
1118 * XXPV Hmm. We can't walk the Northbridges on
1119 * the hypervisor; so just complain and drive
1120 * on. This probably needs to be fixed in
1121 * the hypervisor itself.
1123 opteron_workaround_6336786
++;
1124 workaround_warning(cpu
, 6336786);
1126 } else if ((opteron_get_nnodes() *
1127 cpuid_get_ncpu_per_chip(cpu
) > 1) ||
1128 opteron_workaround_6336786_UP
) {
1130 uint_t node
, nnodes
;
1133 nnodes
= opteron_get_nnodes();
1134 for (node
= 0; node
< nnodes
; node
++) {
1136 * Clear PMM7[1:0] (function 3, offset 0x87)
1137 * Northbridge device is the node id + 24.
1139 data
= pci_getb_func(0, node
+ 24, 3, 0x87);
1141 pci_putb_func(0, node
+ 24, 3, 0x87, data
);
1143 opteron_workaround_6336786
++;
1147 workaround_warning(cpu
, 6336786);
1154 * Mutex primitives don't work as expected.
1156 if (cpuid_opteron_erratum(cpu
, 6323525) > 0) {
1157 #if defined(OPTERON_WORKAROUND_6323525)
1159 * This problem only occurs with 2 or more cores. If bit in
1160 * MSR_AMD_BU_CFG set, then not applicable. The workaround
1161 * is to patch the semaphone routines with the lfence
1162 * instruction to provide necessary load memory barrier with
1163 * possible subsequent read-modify-write ops.
1165 * It is too early in boot to call the patch routine so
1166 * set erratum variable to be done in startup_end().
1168 if (opteron_workaround_6323525
) {
1169 opteron_workaround_6323525
++;
1171 } else if (is_x86_feature(x86_featureset
, X86FSET_SSE2
)) {
1172 if (DOMAIN_IS_INITDOMAIN(xen_info
)) {
1174 * XXPV Use dom0_msr here when extended
1175 * operations are supported?
1177 if (xpv_nr_phys_cpus() > 1)
1178 opteron_workaround_6323525
++;
1181 * We have no way to tell how many physical
1182 * cpus there are, or even if this processor
1183 * has the problem, so enable the workaround
1184 * unconditionally (at some performance cost).
1186 opteron_workaround_6323525
++;
1189 } else if (is_x86_feature(x86_featureset
, X86FSET_SSE2
) &&
1190 ((opteron_get_nnodes() *
1191 cpuid_get_ncpu_per_chip(cpu
)) > 1)) {
1192 if ((xrdmsr(MSR_AMD_BU_CFG
) & (UINT64_C(1) << 33)) == 0)
1193 opteron_workaround_6323525
++;
1197 workaround_warning(cpu
, 6323525);
1202 missing
+= do_erratum_298(cpu
);
1204 if (cpuid_opteron_erratum(cpu
, 721) > 0) {
1205 #if defined(OPTERON_ERRATUM_721)
1208 if (!on_trap(&otd
, OT_DATA_ACCESS
))
1209 wrmsr(MSR_AMD_DE_CFG
,
1210 rdmsr(MSR_AMD_DE_CFG
) | AMD_DE_CFG_E721
);
1213 opteron_erratum_721
++;
1215 workaround_warning(cpu
, 721);
1224 workaround_errata_end()
1226 #if defined(OPTERON_ERRATUM_88)
1227 if (opteron_erratum_88
)
1228 workaround_applied(88);
1230 #if defined(OPTERON_ERRATUM_91)
1231 if (opteron_erratum_91
)
1232 workaround_applied(91);
1234 #if defined(OPTERON_ERRATUM_93)
1235 if (opteron_erratum_93
)
1236 workaround_applied(93);
1238 #if defined(OPTERON_ERRATUM_95)
1239 if (opteron_erratum_95
)
1240 workaround_applied(95);
1242 #if defined(OPTERON_ERRATUM_100)
1243 if (opteron_erratum_100
)
1244 workaround_applied(100);
1246 #if defined(OPTERON_ERRATUM_108)
1247 if (opteron_erratum_108
)
1248 workaround_applied(108);
1250 #if defined(OPTERON_ERRATUM_109)
1251 if (opteron_erratum_109
) {
1253 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1254 " processor\nerratum 109 was not detected; updating your"
1255 " system's BIOS to a version\ncontaining this"
1256 " microcode patch is HIGHLY recommended or erroneous"
1257 " system\noperation may occur.\n");
1260 #if defined(OPTERON_ERRATUM_121)
1261 if (opteron_erratum_121
)
1262 workaround_applied(121);
1264 #if defined(OPTERON_ERRATUM_122)
1265 if (opteron_erratum_122
)
1266 workaround_applied(122);
1268 #if defined(OPTERON_ERRATUM_123)
1269 if (opteron_erratum_123
) {
1271 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1272 " processor\nerratum 123 was not detected; updating your"
1273 " system's BIOS to a version\ncontaining this"
1274 " microcode patch is HIGHLY recommended or erroneous"
1275 " system\noperation may occur.\n");
1278 #if defined(OPTERON_ERRATUM_131)
1279 if (opteron_erratum_131
) {
1281 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1282 " processor\nerratum 131 was not detected; updating your"
1283 " system's BIOS to a version\ncontaining this"
1284 " microcode patch is HIGHLY recommended or erroneous"
1285 " system\noperation may occur.\n");
1288 #if defined(OPTERON_WORKAROUND_6336786)
1289 if (opteron_workaround_6336786
)
1290 workaround_applied(6336786);
1292 #if defined(OPTERON_WORKAROUND_6323525)
1293 if (opteron_workaround_6323525
)
1294 workaround_applied(6323525);
1296 #if defined(OPTERON_ERRATUM_298)
1297 if (opteron_erratum_298
) {
1299 "BIOS microcode patch for AMD 64/Opteron(tm)"
1300 " processor\nerratum 298 was not detected; updating your"
1301 " system's BIOS to a version\ncontaining this"
1302 " microcode patch is HIGHLY recommended or erroneous"
1303 " system\noperation may occur.\n");
1306 #if defined(OPTERON_ERRATUM_721)
1307 if (opteron_erratum_721
)
1308 workaround_applied(721);
1313 * The procset_slave and procset_master are used to synchronize
1314 * between the control CPU and the target CPU when starting CPUs.
1316 static cpuset_t procset_slave
, procset_master
;
1319 mp_startup_wait(cpuset_t
*sp
, processorid_t cpuid
)
1323 for (tempset
= *sp
; !CPU_IN_SET(tempset
, cpuid
);
1324 tempset
= *(volatile cpuset_t
*)sp
) {
1327 CPUSET_ATOMIC_DEL(*(cpuset_t
*)sp
, cpuid
);
1331 mp_startup_signal(cpuset_t
*sp
, processorid_t cpuid
)
1335 CPUSET_ATOMIC_ADD(*(cpuset_t
*)sp
, cpuid
);
1336 for (tempset
= *sp
; CPU_IN_SET(tempset
, cpuid
);
1337 tempset
= *(volatile cpuset_t
*)sp
) {
1343 mp_start_cpu_common(cpu_t
*cp
, boolean_t boot
)
1345 _NOTE(ARGUNUSED(boot
));
1351 processorid_t cpuid
;
1352 extern void cpupm_init(cpu_t
*);
1356 ctx
= mach_cpucontext_alloc(cp
);
1359 "cpu%d: failed to allocate context", cp
->cpu_id
);
1362 error
= mach_cpu_start(cp
, ctx
);
1365 "cpu%d: failed to start, error %d", cp
->cpu_id
, error
);
1366 mach_cpucontext_free(cp
, ctx
, error
);
1370 for (delays
= 0, tempset
= procset_slave
; !CPU_IN_SET(tempset
, cpuid
);
1372 if (delays
== 500) {
1374 * After five seconds, things are probably looking
1375 * a bit bleak - explain the hang.
1377 cmn_err(CE_NOTE
, "cpu%d: started, "
1378 "but not running in the kernel yet", cpuid
);
1379 } else if (delays
> 2000) {
1381 * We waited at least 20 seconds, bail ..
1384 cmn_err(CE_WARN
, "cpu%d: timed out", cpuid
);
1385 mach_cpucontext_free(cp
, ctx
, error
);
1390 * wait at least 10ms, then check again..
1392 delay(USEC_TO_TICK_ROUNDUP(10000));
1393 tempset
= *((volatile cpuset_t
*)&procset_slave
);
1395 CPUSET_ATOMIC_DEL(procset_slave
, cpuid
);
1397 mach_cpucontext_free(cp
, ctx
, 0);
1399 if (tsc_gethrtime_enable
)
1400 tsc_sync_master(cpuid
);
1402 if (dtrace_cpu_init
!= NULL
) {
1403 (*dtrace_cpu_init
)(cpuid
);
1407 * During CPU DR operations, the cpu_lock is held by current
1408 * (the control) thread. We can't release the cpu_lock here
1409 * because that will break the CPU DR logic.
1410 * On the other hand, CPUPM and processor group initialization
1411 * routines need to access the cpu_lock. So we invoke those
1412 * routines here on behalf of mp_startup_common().
1414 * CPUPM and processor group initialization routines depend
1415 * on the cpuid probing results. Wait for mp_startup_common()
1416 * to signal that cpuid probing is done.
1418 mp_startup_wait(&procset_slave
, cpuid
);
1420 (void) pg_cpu_init(cp
, B_FALSE
);
1422 mp_startup_signal(&procset_master
, cpuid
);
1428 * Start a single cpu, assuming that the kernel context is available
1429 * to successfully start another cpu.
1431 * (For example, real mode code is mapped into the right place
1432 * in memory and is ready to be run.)
1435 start_cpu(processorid_t who
)
1444 * Check if there's at least a Mbyte of kmem available
1445 * before attempting to start the cpu.
1447 if (kmem_avail() < 1024 * 1024) {
1449 * Kick off a reap in case that helps us with
1457 * First configure cpu.
1459 cp
= mp_cpu_configure_common(who
, B_TRUE
);
1465 error
= mp_start_cpu_common(cp
, B_TRUE
);
1467 mp_cpu_unconfigure_common(cp
, error
);
1471 mutex_exit(&cpu_lock
);
1472 tempset
= cpu_ready_set
;
1473 while (!CPU_IN_SET(tempset
, who
)) {
1475 tempset
= *((volatile cpuset_t
*)&cpu_ready_set
);
1477 mutex_enter(&cpu_lock
);
1483 start_other_cpus(int cprboot
)
1485 _NOTE(ARGUNUSED(cprboot
));
1488 uint_t bootcpuid
= 0;
1491 * Initialize our own cpu_info.
1495 init_cpu_id_gdt(CPU
);
1497 cmn_err(CE_CONT
, "?cpu%d: %s\n", CPU
->cpu_id
, CPU
->cpu_idstr
);
1498 cmn_err(CE_CONT
, "?cpu%d: %s\n", CPU
->cpu_id
, CPU
->cpu_brandstr
);
1501 * KPTI initialisation happens very early in boot, before logging is
1502 * set up. Output a status message now as the boot CPU comes online.
1504 cmn_err(CE_CONT
, "?KPTI %s (PCID %s, INVPCID %s)\n",
1505 kpti_enable
? "enabled" : "disabled",
1506 x86_use_pcid
== 1 ? "in use" :
1507 (is_x86_feature(x86_featureset
, X86FSET_PCID
) ? "disabled" :
1509 x86_use_pcid
== 1 && x86_use_invpcid
== 1 ? "in use" :
1510 (is_x86_feature(x86_featureset
, X86FSET_INVPCID
) ? "disabled" :
1514 * Initialize our syscall handlers
1516 init_cpu_syscall(CPU
);
1519 * Take the boot cpu out of the mp_cpus set because we know
1520 * it's already running. Add it to the cpu_ready_set for
1521 * precisely the same reason.
1523 CPUSET_DEL(mp_cpus
, bootcpuid
);
1524 CPUSET_ADD(cpu_ready_set
, bootcpuid
);
1527 * skip the rest of this if
1528 * . only 1 cpu dectected and system isn't hotplug-capable
1531 if ((CPUSET_ISNULL(mp_cpus
) && plat_dr_support_cpu() == 0) ||
1534 cmn_err(CE_CONT
, "?***** Not in MP mode\n");
1539 * perform such initialization as is needed
1540 * to be able to take CPUs on- and off-line.
1544 xc_init_cpu(CPU
); /* initialize processor crosscalls */
1546 if (mach_cpucontext_init() != 0)
1549 flushes_require_xcalls
= 1;
1552 * We lock our affinity to the master CPU to ensure that all slave CPUs
1553 * do their TSC syncs with the same CPU.
1555 affinity_set(CPU_CURRENT
);
1557 for (who
= 0; who
< NCPU
; who
++) {
1558 if (!CPU_IN_SET(mp_cpus
, who
))
1560 ASSERT(who
!= bootcpuid
);
1562 mutex_enter(&cpu_lock
);
1563 if (start_cpu(who
) != 0)
1564 CPUSET_DEL(mp_cpus
, who
);
1565 cpu_state_change_notify(who
, CPU_SETUP
);
1566 mutex_exit(&cpu_lock
);
1569 /* Free the space allocated to hold the microcode file */
1574 mach_cpucontext_fini();
1577 if (get_hwenv() == HW_NATIVE
)
1578 workaround_errata_end();
1579 cmi_post_mpstartup();
1581 if (use_mp
&& ncpus
!= boot_max_ncpus
) {
1583 "System detected %d cpus, but "
1584 "only %d cpu(s) were enabled during boot.",
1585 boot_max_ncpus
, ncpus
);
1587 "Use \"boot-ncpus\" parameter to enable more CPU(s). "
1593 mp_cpu_configure(int cpuid
)
1597 if (use_mp
== 0 || plat_dr_support_cpu() == 0) {
1601 cp
= cpu_get(cpuid
);
1607 * Check if there's at least a Mbyte of kmem available
1608 * before attempting to start the cpu.
1610 if (kmem_avail() < 1024 * 1024) {
1612 * Kick off a reap in case that helps us with
1619 cp
= mp_cpu_configure_common(cpuid
, B_FALSE
);
1620 ASSERT(cp
!= NULL
&& cpu_get(cpuid
) == cp
);
1622 return (cp
!= NULL
? 0 : EAGAIN
);
1626 mp_cpu_unconfigure(int cpuid
)
1630 if (use_mp
== 0 || plat_dr_support_cpu() == 0) {
1632 } else if (cpuid
< 0 || cpuid
>= max_ncpus
) {
1636 cp
= cpu_get(cpuid
);
1640 mp_cpu_unconfigure_common(cp
, 0);
1646 * Startup function for 'other' CPUs (besides boot cpu).
1647 * Called from real_mode_start.
1649 * WARNING: until CPU_READY is set, mp_startup_common and routines called by
1650 * mp_startup_common should not call routines (e.g. kmem_free) that could call
1651 * hat_unload which requires CPU_READY to be set.
1654 mp_startup_common(boolean_t boot
)
1657 uchar_t new_x86_featureset
[BT_SIZEOFMAP(NUM_X86_FEATURES
)];
1658 extern void cpu_event_init_cpu(cpu_t
*);
1661 * We need to get TSC on this proc synced (i.e., any delta
1662 * from cpu0 accounted for) as soon as we can, because many
1663 * many things use gethrtime/pc_gethrestime, including
1664 * interrupts, cmn_err, etc. Before we can do that, we want to
1665 * clear TSC if we're on a buggy Sandy/Ivy Bridge CPU, so do that
1668 bzero(new_x86_featureset
, BT_SIZEOFMAP(NUM_X86_FEATURES
));
1669 cpuid_pass1(cp
, new_x86_featureset
);
1671 if (boot
&& get_hwenv() == HW_NATIVE
&&
1672 cpuid_getvendor(CPU
) == X86_VENDOR_Intel
&&
1673 cpuid_getfamily(CPU
) == 6 &&
1674 (cpuid_getmodel(CPU
) == 0x2d || cpuid_getmodel(CPU
) == 0x3e) &&
1675 is_x86_feature(new_x86_featureset
, X86FSET_TSC
)) {
1676 (void) wrmsr(REG_TSC
, 0UL);
1679 /* Let the control CPU continue into tsc_sync_master() */
1680 mp_startup_signal(&procset_slave
, cp
->cpu_id
);
1682 if (tsc_gethrtime_enable
)
1686 * Once this was done from assembly, but it's safer here; if
1687 * it blocks, we need to be able to swtch() to and from, and
1688 * since we get here by calling t_pc, we need to do that call
1689 * before swtch() overwrites it.
1691 (void) (*ap_mlsetup
)();
1694 * Program this cpu's PAT
1699 * Set up TSC_AUX to contain the cpuid for this processor
1700 * for the rdtscp instruction.
1702 if (is_x86_feature(x86_featureset
, X86FSET_TSCP
))
1703 (void) wrmsr(MSR_AMD_TSCAUX
, cp
->cpu_id
);
1706 * Initialize this CPU's syscall handlers
1708 init_cpu_syscall(cp
);
1711 * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the
1712 * highest level at which a routine is permitted to block on
1713 * an adaptive mutex (allows for cpu poke interrupt in case
1714 * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks
1715 * device interrupts that may end up in the hat layer issuing cross
1716 * calls before CPU_READY is set.
1718 splx(ipltospl(LOCK_LEVEL
));
1722 * There exists a small subset of systems which expose differing
1723 * MWAIT/MONITOR support between CPUs. If MWAIT support is absent from
1724 * the boot CPU, but is found on a later CPU, the system continues to
1725 * operate as if no MWAIT support is available.
1727 * The reverse case, where MWAIT is available on the boot CPU but not
1728 * on a subsequently initialized CPU, is not presently allowed and will
1729 * result in a panic.
1731 if (is_x86_feature(x86_featureset
, X86FSET_MWAIT
) !=
1732 is_x86_feature(new_x86_featureset
, X86FSET_MWAIT
)) {
1733 if (!is_x86_feature(x86_featureset
, X86FSET_MWAIT
)) {
1734 remove_x86_feature(new_x86_featureset
, X86FSET_MWAIT
);
1736 panic("unsupported mixed cpu mwait support detected");
1741 * We could be more sophisticated here, and just mark the CPU
1742 * as "faulted" but at this point we'll opt for the easier
1743 * answer of dying horribly. Provided the boot cpu is ok,
1744 * the system can be recovered by booting with use_mp set to zero.
1746 if (workaround_errata(cp
) != 0)
1747 panic("critical workaround(s) missing for cpu%d", cp
->cpu_id
);
1750 * We can touch cpu_flags here without acquiring the cpu_lock here
1751 * because the cpu_lock is held by the control CPU which is running
1752 * mp_start_cpu_common().
1753 * Need to clear CPU_QUIESCED flag before calling any function which
1754 * may cause thread context switching, such as kmem_alloc() etc.
1755 * The idle thread checks for CPU_QUIESCED flag and loops for ever if
1756 * it's set. So the startup thread may have no chance to switch back
1757 * again if it's switched away with CPU_QUIESCED set.
1759 cp
->cpu_flags
&= ~(CPU_POWEROFF
| CPU_QUIESCED
);
1764 * Setup this processor for XSAVE.
1766 if (fp_save_mech
== FP_XSAVE
) {
1767 xsave_setup_msr(cp
);
1772 cpuid_pass4(cp
, NULL
);
1775 * Correct cpu_idstr and cpu_brandstr on target CPU after
1776 * cpuid_pass1() is done.
1778 (void) cpuid_getidstr(cp
, cp
->cpu_idstr
, CPU_IDSTRLEN
);
1779 (void) cpuid_getbrandstr(cp
, cp
->cpu_brandstr
, CPU_IDSTRLEN
);
1781 cp
->cpu_flags
|= CPU_RUNNING
| CPU_READY
| CPU_EXISTS
;
1783 post_startup_cpu_fixups();
1785 cpu_event_init_cpu(cp
);
1788 * Enable preemption here so that contention for any locks acquired
1789 * later in mp_startup_common may be preempted if the thread owning
1790 * those locks is continuously executing on other CPUs (for example,
1791 * this CPU must be preemptible to allow other CPUs to pause it during
1792 * their startup phases). It's safe to enable preemption here because
1793 * the CPU state is pretty-much fully constructed.
1795 curthread
->t_preempt
= 0;
1797 /* The base spl should still be at LOCK LEVEL here */
1798 ASSERT(cp
->cpu_base_spl
== ipltospl(LOCK_LEVEL
));
1799 set_base_spl(); /* Restore the spl to its proper value */
1801 pghw_physid_create(cp
);
1803 * Delegate initialization tasks, which need to access the cpu_lock,
1804 * to mp_start_cpu_common() because we can't acquire the cpu_lock here
1805 * during CPU DR operations.
1807 mp_startup_signal(&procset_slave
, cp
->cpu_id
);
1808 mp_startup_wait(&procset_master
, cp
->cpu_id
);
1809 pg_cmt_cpu_startup(cp
);
1812 mutex_enter(&cpu_lock
);
1813 cp
->cpu_flags
&= ~CPU_OFFLINE
;
1814 cpu_enable_intr(cp
);
1816 mutex_exit(&cpu_lock
);
1819 /* Enable interrupts */
1823 * Fill out cpu_ucode_info. Update microcode if necessary.
1826 cpuid_pass_ucode(cp
, new_x86_featureset
);
1829 * Do a sanity check to make sure this new CPU is a sane thing
1830 * to add to the collection of processors running this system.
1832 * XXX Clearly this needs to get more sophisticated, if x86
1833 * systems start to get built out of heterogenous CPUs; as is
1834 * likely to happen once the number of processors in a configuration
1835 * gets large enough.
1837 if (compare_x86_featureset(x86_featureset
, new_x86_featureset
) ==
1839 cmn_err(CE_CONT
, "cpu%d: featureset\n", cp
->cpu_id
);
1840 print_x86_featureset(new_x86_featureset
);
1841 cmn_err(CE_WARN
, "cpu%d feature mismatch", cp
->cpu_id
);
1846 * Set up the CPU module for this CPU. This can't be done
1847 * before this CPU is made CPU_READY, because we may (in
1848 * heterogeneous systems) need to go load another CPU module.
1849 * The act of attempting to load a module may trigger a
1850 * cross-call, which will ASSERT unless this cpu is CPU_READY.
1854 if ((hdl
= cmi_init(CMI_HDL_NATIVE
, cmi_ntv_hwchipid(CPU
),
1855 cmi_ntv_hwcoreid(CPU
), cmi_ntv_hwstrandid(CPU
))) != NULL
) {
1856 if (is_x86_feature(x86_featureset
, X86FSET_MCA
))
1858 cp
->cpu_m
.mcpu_cmi_hdl
= hdl
;
1862 if (boothowto
& RB_DEBUG
)
1865 (void) mach_cpu_create_device_node(cp
, NULL
);
1868 * Setting the bit in cpu_ready_set must be the last operation in
1869 * processor initialization; the boot CPU will continue to boot once
1870 * it sees this bit set for all active CPUs.
1872 CPUSET_ATOMIC_ADD(cpu_ready_set
, cp
->cpu_id
);
1874 cmn_err(CE_CONT
, "?cpu%d: %s\n", cp
->cpu_id
, cp
->cpu_idstr
);
1875 cmn_err(CE_CONT
, "?cpu%d: %s\n", cp
->cpu_id
, cp
->cpu_brandstr
);
1876 cmn_err(CE_CONT
, "?cpu%d initialization complete - online\n",
1880 * Now we are done with the startup thread, so free it up.
1883 panic("mp_startup: cannot return");
1888 * Startup function for 'other' CPUs at boot time (besides boot cpu).
1891 mp_startup_boot(void)
1893 mp_startup_common(B_TRUE
);
1897 * Startup function for hotplug CPUs at runtime.
1900 mp_startup_hotplug(void)
1902 mp_startup_common(B_FALSE
);
1906 * Start CPU on user request.
1910 mp_cpu_start(struct cpu
*cp
)
1912 ASSERT(MUTEX_HELD(&cpu_lock
));
1917 * Stop CPU on user request.
1920 mp_cpu_stop(struct cpu
*cp
)
1922 extern int cbe_psm_timer_mode
;
1923 ASSERT(MUTEX_HELD(&cpu_lock
));
1927 * If TIMER_PERIODIC mode is used, CPU0 is the one running it;
1928 * can't stop it. (This is true only for machines with no TSC.)
1931 if ((cbe_psm_timer_mode
== TIMER_PERIODIC
) && (cp
->cpu_id
== 0))
1938 * Take the specified CPU out of participation in interrupts.
1941 cpu_disable_intr(struct cpu
*cp
)
1943 if (psm_disable_intr(cp
->cpu_id
) != DDI_SUCCESS
)
1946 cp
->cpu_flags
&= ~CPU_ENABLE
;
1951 * Allow the specified CPU to participate in interrupts.
1954 cpu_enable_intr(struct cpu
*cp
)
1956 ASSERT(MUTEX_HELD(&cpu_lock
));
1957 cp
->cpu_flags
|= CPU_ENABLE
;
1958 psm_enable_intr(cp
->cpu_id
);
1962 mp_cpu_faulted_enter(struct cpu
*cp
)
1964 cmi_hdl_t hdl
= cp
->cpu_m
.mcpu_cmi_hdl
;
1969 hdl
= cmi_hdl_lookup(CMI_HDL_NATIVE
, cmi_ntv_hwchipid(cp
),
1970 cmi_ntv_hwcoreid(cp
), cmi_ntv_hwstrandid(cp
));
1973 cmi_faulted_enter(hdl
);
1979 mp_cpu_faulted_exit(struct cpu
*cp
)
1981 cmi_hdl_t hdl
= cp
->cpu_m
.mcpu_cmi_hdl
;
1986 hdl
= cmi_hdl_lookup(CMI_HDL_NATIVE
, cmi_ntv_hwchipid(cp
),
1987 cmi_ntv_hwcoreid(cp
), cmi_ntv_hwstrandid(cp
));
1990 cmi_faulted_exit(hdl
);
1996 * The following two routines are used as context operators on threads belonging
1997 * to processes with a private LDT (see sysi86). Due to the rarity of such
1998 * processes, these routines are currently written for best code readability and
1999 * organization rather than speed. We could avoid checking x86_featureset at
2000 * every context switch by installing different context ops, depending on
2001 * x86_featureset, at LDT creation time -- one for each combination of fast
2006 cpu_fast_syscall_disable(void)
2008 if (is_x86_feature(x86_featureset
, X86FSET_MSR
) &&
2009 is_x86_feature(x86_featureset
, X86FSET_SEP
))
2011 if (is_x86_feature(x86_featureset
, X86FSET_MSR
) &&
2012 is_x86_feature(x86_featureset
, X86FSET_ASYSC
))
2013 cpu_asysc_disable();
2017 cpu_fast_syscall_enable(void)
2019 if (is_x86_feature(x86_featureset
, X86FSET_MSR
) &&
2020 is_x86_feature(x86_featureset
, X86FSET_SEP
))
2022 if (is_x86_feature(x86_featureset
, X86FSET_MSR
) &&
2023 is_x86_feature(x86_featureset
, X86FSET_ASYSC
))
2028 cpu_sep_enable(void)
2030 ASSERT(is_x86_feature(x86_featureset
, X86FSET_SEP
));
2031 ASSERT(curthread
->t_preempt
|| getpil() >= LOCK_LEVEL
);
2033 wrmsr(MSR_INTC_SEP_CS
, (uint64_t)(uintptr_t)KCS_SEL
);
2037 cpu_sep_disable(void)
2039 ASSERT(is_x86_feature(x86_featureset
, X86FSET_SEP
));
2040 ASSERT(curthread
->t_preempt
|| getpil() >= LOCK_LEVEL
);
2043 * Setting the SYSENTER_CS_MSR register to 0 causes software executing
2044 * the sysenter or sysexit instruction to trigger a #gp fault.
2046 wrmsr(MSR_INTC_SEP_CS
, 0);
2050 cpu_asysc_enable(void)
2052 ASSERT(is_x86_feature(x86_featureset
, X86FSET_ASYSC
));
2053 ASSERT(curthread
->t_preempt
|| getpil() >= LOCK_LEVEL
);
2055 wrmsr(MSR_AMD_EFER
, rdmsr(MSR_AMD_EFER
) |
2056 (uint64_t)(uintptr_t)AMD_EFER_SCE
);
2060 cpu_asysc_disable(void)
2062 ASSERT(is_x86_feature(x86_featureset
, X86FSET_ASYSC
));
2063 ASSERT(curthread
->t_preempt
|| getpil() >= LOCK_LEVEL
);
2066 * Turn off the SCE (syscall enable) bit in the EFER register. Software
2067 * executing syscall or sysret with this bit off will incur a #ud trap.
2069 wrmsr(MSR_AMD_EFER
, rdmsr(MSR_AMD_EFER
) &
2070 ~((uint64_t)(uintptr_t)AMD_EFER_SCE
));