?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
MINI2440: Removed unneeded dependency
[u-boot-openmoko/mini2440.git] / include / s3c24x0.h
blob68770bd0e12eda8a436ddb77a9a4b7dbe9fcf1e5
1 /*
2 * (C) Copyright 2003
3 * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 /************************************************
25 * NAME : s3c24x0.h
26 * Version : 31.3.2003
27 *
28 * common stuff for SAMSUNG S3C24X0 SoC
29 ************************************************/
30
31 #ifndef __S3C24X0_H__
32 #define __S3C24X0_H__
33
34 typedef volatile u8 S3C24X0_REG8;
35 typedef volatile u16 S3C24X0_REG16;
36 typedef volatile u32 S3C24X0_REG32;
37
38 /* Memory controller (see manual chapter 5) */
39 typedef struct {
40 S3C24X0_REG32 BWSCON;
41 S3C24X0_REG32 BANKCON[8];
42 S3C24X0_REG32 REFRESH;
43 S3C24X0_REG32 BANKSIZE;
44 S3C24X0_REG32 MRSRB6;
45 S3C24X0_REG32 MRSRB7;
46 } /*__attribute__((__packed__))*/ S3C24X0_MEMCTL;
47
48
49 /* USB HOST (see manual chapter 12) */
50 typedef struct {
51 S3C24X0_REG32 HcRevision;
52 S3C24X0_REG32 HcControl;
53 S3C24X0_REG32 HcCommonStatus;
54 S3C24X0_REG32 HcInterruptStatus;
55 S3C24X0_REG32 HcInterruptEnable;
56 S3C24X0_REG32 HcInterruptDisable;
57 S3C24X0_REG32 HcHCCA;
58 S3C24X0_REG32 HcPeriodCuttendED;
59 S3C24X0_REG32 HcControlHeadED;
60 S3C24X0_REG32 HcControlCurrentED;
61 S3C24X0_REG32 HcBulkHeadED;
62 S3C24X0_REG32 HcBuldCurrentED;
63 S3C24X0_REG32 HcDoneHead;
64 S3C24X0_REG32 HcRmInterval;
65 S3C24X0_REG32 HcFmRemaining;
66 S3C24X0_REG32 HcFmNumber;
67 S3C24X0_REG32 HcPeriodicStart;
68 S3C24X0_REG32 HcLSThreshold;
69 S3C24X0_REG32 HcRhDescriptorA;
70 S3C24X0_REG32 HcRhDescriptorB;
71 S3C24X0_REG32 HcRhStatus;
72 S3C24X0_REG32 HcRhPortStatus1;
73 S3C24X0_REG32 HcRhPortStatus2;
74 } /*__attribute__((__packed__))*/ S3C24X0_USB_HOST;
75
76
77 /* INTERRUPT (see manual chapter 14) */
78 typedef struct {
79 S3C24X0_REG32 SRCPND;
80 S3C24X0_REG32 INTMOD;
81 S3C24X0_REG32 INTMSK;
82 S3C24X0_REG32 PRIORITY;
83 S3C24X0_REG32 INTPND;
84 S3C24X0_REG32 INTOFFSET;
85 #if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
86 defined(CONFIG_S3C2442)
87 S3C24X0_REG32 SUBSRCPND;
88 S3C24X0_REG32 INTSUBMSK;
89 #endif
90 } /*__attribute__((__packed__))*/ S3C24X0_INTERRUPT;
91
92
93 /* DMAS (see manual chapter 8) */
94 typedef struct {
95 S3C24X0_REG32 DISRC;
96 #if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
97 defined(CONFIG_S3C2442)
98 S3C24X0_REG32 DISRCC;
99 #endif
100 S3C24X0_REG32 DIDST;
101 #if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
102 defined(CONFIG_S3C2442)
103 S3C24X0_REG32 DIDSTC;
104 #endif
105 S3C24X0_REG32 DCON;
106 S3C24X0_REG32 DSTAT;
107 S3C24X0_REG32 DCSRC;
108 S3C24X0_REG32 DCDST;
109 S3C24X0_REG32 DMASKTRIG;
110 #ifdef CONFIG_S3C2400
111 S3C24X0_REG32 res[1];
112 #endif
113 #if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
114 defined(CONFIG_S3C2442)
115 S3C24X0_REG32 res[7];
116 #endif
117 } /*__attribute__((__packed__))*/ S3C24X0_DMA;
118
119 typedef struct {
120 S3C24X0_DMA dma[4];
121 } /*__attribute__((__packed__))*/ S3C24X0_DMAS;
122
123
124 /* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
125 /* (see S3C2410 manual chapter 7) */
126 typedef struct {
127 S3C24X0_REG32 LOCKTIME;
128 S3C24X0_REG32 MPLLCON;
129 S3C24X0_REG32 UPLLCON;
130 S3C24X0_REG32 CLKCON;
131 S3C24X0_REG32 CLKSLOW;
132 S3C24X0_REG32 CLKDIVN;
133 #if defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
134 S3C24X0_REG32 CAMDIVN;
135 #endif
136 } /*__attribute__((__packed__))*/ S3C24X0_CLOCK_POWER;
137
138
139 /* LCD CONTROLLER (see manual chapter 15) */
140 typedef struct {
141 S3C24X0_REG32 LCDCON1;
142 S3C24X0_REG32 LCDCON2;
143 S3C24X0_REG32 LCDCON3;
144 S3C24X0_REG32 LCDCON4;
145 S3C24X0_REG32 LCDCON5;
146 S3C24X0_REG32 LCDSADDR1;
147 S3C24X0_REG32 LCDSADDR2;
148 S3C24X0_REG32 LCDSADDR3;
149 S3C24X0_REG32 REDLUT;
150 S3C24X0_REG32 GREENLUT;
151 S3C24X0_REG32 BLUELUT;
152 S3C24X0_REG32 res[8];
153 S3C24X0_REG32 DITHMODE;
154 S3C24X0_REG32 TPAL;
155 #if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
156 defined(CONFIG_S3C2442)
157 S3C24X0_REG32 LCDINTPND;
158 S3C24X0_REG32 LCDSRCPND;
159 S3C24X0_REG32 LCDINTMSK;
160 S3C24X0_REG32 LPCSEL;
161 #endif
162 } /*__attribute__((__packed__))*/ S3C24X0_LCD;
163
164
165 /* NAND FLASH (see S3C2410 manual chapter 6) */
166 typedef struct {
167 S3C24X0_REG32 NFCONF;
168 #if defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
169 S3C24X0_REG32 NFCONT;
170 #endif
171 S3C24X0_REG32 NFCMD;
172 S3C24X0_REG32 NFADDR;
173 S3C24X0_REG32 NFDATA;
174 S3C24X0_REG32 NFSTAT;
175 S3C24X0_REG32 NFECC;
176 } /*__attribute__((__packed__))*/ S3C2410_NAND;
177
178 /* NAND FLASH (see S3C2440 manual chapter 6) */
179 typedef struct {
180 S3C24X0_REG32 NFCONF;
181 S3C24X0_REG32 NFCMD;
182 S3C24X0_REG32 NFADDR;
183 S3C24X0_REG32 NFDATA;
184 S3C24X0_REG32 NFSTAT;
185 S3C24X0_REG32 NFECC;
186 } /*__attribute__((__packed__))*/ S3C2440_NAND;
187
188 /* UART (see manual chapter 11) */
189 typedef struct {
190 S3C24X0_REG32 ULCON;
191 S3C24X0_REG32 UCON;
192 S3C24X0_REG32 UFCON;
193 S3C24X0_REG32 UMCON;
194 S3C24X0_REG32 UTRSTAT;
195 S3C24X0_REG32 UERSTAT;
196 S3C24X0_REG32 UFSTAT;
197 S3C24X0_REG32 UMSTAT;
198 #ifdef __BIG_ENDIAN
199 S3C24X0_REG8 res1[3];
200 S3C24X0_REG8 UTXH;
201 S3C24X0_REG8 res2[3];
202 S3C24X0_REG8 URXH;
203 #else /* Little Endian */
204 S3C24X0_REG8 UTXH;
205 S3C24X0_REG8 res1[3];
206 S3C24X0_REG8 URXH;
207 S3C24X0_REG8 res2[3];
208 #endif
209 S3C24X0_REG32 UBRDIV;
210 } /*__attribute__((__packed__))*/ S3C24X0_UART;
211
212
213 /* PWM TIMER (see manual chapter 10) */
214 typedef struct {
215 S3C24X0_REG32 TCNTB;
216 S3C24X0_REG32 TCMPB;
217 S3C24X0_REG32 TCNTO;
218 } /*__attribute__((__packed__))*/ S3C24X0_TIMER;
219
220 typedef struct {
221 S3C24X0_REG32 TCFG0;
222 S3C24X0_REG32 TCFG1;
223 S3C24X0_REG32 TCON;
224 S3C24X0_TIMER ch[4];
225 S3C24X0_REG32 TCNTB4;
226 S3C24X0_REG32 TCNTO4;
227 } /*__attribute__((__packed__))*/ S3C24X0_TIMERS;
228
229
230 /* USB DEVICE (see manual chapter 13) */
231 typedef struct {
232 #ifdef __BIG_ENDIAN
233 S3C24X0_REG8 res[3];
234 S3C24X0_REG8 EP_FIFO_REG;
235 #else /* little endian */
236 S3C24X0_REG8 EP_FIFO_REG;
237 S3C24X0_REG8 res[3];
238 #endif
239 } /*__attribute__((__packed__))*/ S3C24X0_USB_DEV_FIFOS;
240
241 typedef struct {
242 #ifdef __BIG_ENDIAN
243 S3C24X0_REG8 res1[3];
244 S3C24X0_REG8 EP_DMA_CON;
245 S3C24X0_REG8 res2[3];
246 S3C24X0_REG8 EP_DMA_UNIT;
247 S3C24X0_REG8 res3[3];
248 S3C24X0_REG8 EP_DMA_FIFO;
249 S3C24X0_REG8 res4[3];
250 S3C24X0_REG8 EP_DMA_TTC_L;
251 S3C24X0_REG8 res5[3];
252 S3C24X0_REG8 EP_DMA_TTC_M;
253 S3C24X0_REG8 res6[3];
254 S3C24X0_REG8 EP_DMA_TTC_H;
255 #else /* little endian */
256 S3C24X0_REG8 EP_DMA_CON;
257 S3C24X0_REG8 res1[3];
258 S3C24X0_REG8 EP_DMA_UNIT;
259 S3C24X0_REG8 res2[3];
260 S3C24X0_REG8 EP_DMA_FIFO;
261 S3C24X0_REG8 res3[3];
262 S3C24X0_REG8 EP_DMA_TTC_L;
263 S3C24X0_REG8 res4[3];
264 S3C24X0_REG8 EP_DMA_TTC_M;
265 S3C24X0_REG8 res5[3];
266 S3C24X0_REG8 EP_DMA_TTC_H;
267 S3C24X0_REG8 res6[3];
268 #endif
269 } /*__attribute__((__packed__))*/ S3C24X0_USB_DEV_DMAS;
270
271 typedef struct {
272 #ifdef __BIG_ENDIAN
273 S3C24X0_REG8 res1[3];
274 S3C24X0_REG8 FUNC_ADDR_REG;
275 S3C24X0_REG8 res2[3];
276 S3C24X0_REG8 PWR_REG;
277 S3C24X0_REG8 res3[3];
278 S3C24X0_REG8 EP_INT_REG;
279 S3C24X0_REG8 res4[15];
280 S3C24X0_REG8 USB_INT_REG;
281 S3C24X0_REG8 res5[3];
282 S3C24X0_REG8 EP_INT_EN_REG;
283 S3C24X0_REG8 res6[15];
284 S3C24X0_REG8 USB_INT_EN_REG;
285 S3C24X0_REG8 res7[3];
286 S3C24X0_REG8 FRAME_NUM1_REG;
287 S3C24X0_REG8 res8[3];
288 S3C24X0_REG8 FRAME_NUM2_REG;
289 S3C24X0_REG8 res9[3];
290 S3C24X0_REG8 INDEX_REG;
291 S3C24X0_REG8 res10[7];
292 S3C24X0_REG8 MAXP_REG;
293 S3C24X0_REG8 res11[3];
294 S3C24X0_REG8 EP0_CSR_IN_CSR1_REG;
295 S3C24X0_REG8 res12[3];
296 S3C24X0_REG8 IN_CSR2_REG;
297 S3C24X0_REG8 res13[7];
298 S3C24X0_REG8 OUT_CSR1_REG;
299 S3C24X0_REG8 res14[3];
300 S3C24X0_REG8 OUT_CSR2_REG;
301 S3C24X0_REG8 res15[3];
302 S3C24X0_REG8 OUT_FIFO_CNT1_REG;
303 S3C24X0_REG8 res16[3];
304 S3C24X0_REG8 OUT_FIFO_CNT2_REG;
305 #else /* little endian */
306 S3C24X0_REG8 FUNC_ADDR_REG;
307 S3C24X0_REG8 res1[3];
308 S3C24X0_REG8 PWR_REG;
309 S3C24X0_REG8 res2[3];
310 S3C24X0_REG8 EP_INT_REG;
311 S3C24X0_REG8 res3[15];
312 S3C24X0_REG8 USB_INT_REG;
313 S3C24X0_REG8 res4[3];
314 S3C24X0_REG8 EP_INT_EN_REG;
315 S3C24X0_REG8 res5[15];
316 S3C24X0_REG8 USB_INT_EN_REG;
317 S3C24X0_REG8 res6[3];
318 S3C24X0_REG8 FRAME_NUM1_REG;
319 S3C24X0_REG8 res7[3];
320 S3C24X0_REG8 FRAME_NUM2_REG;
321 S3C24X0_REG8 res8[3];
322 S3C24X0_REG8 INDEX_REG;
323 S3C24X0_REG8 res9[7];
324 S3C24X0_REG8 MAXP_REG;
325 S3C24X0_REG8 res10[7];
326 S3C24X0_REG8 EP0_CSR_IN_CSR1_REG;
327 S3C24X0_REG8 res11[3];
328 S3C24X0_REG8 IN_CSR2_REG;
329 S3C24X0_REG8 res12[3];
330 S3C24X0_REG8 OUT_CSR1_REG;
331 S3C24X0_REG8 res13[7];
332 S3C24X0_REG8 OUT_CSR2_REG;
333 S3C24X0_REG8 res14[3];
334 S3C24X0_REG8 OUT_FIFO_CNT1_REG;
335 S3C24X0_REG8 res15[3];
336 S3C24X0_REG8 OUT_FIFO_CNT2_REG;
337 S3C24X0_REG8 res16[3];
338 #endif /* __BIG_ENDIAN */
339 S3C24X0_USB_DEV_FIFOS fifo[5];
340 S3C24X0_USB_DEV_DMAS dma[5];
341 } /*__attribute__((__packed__))*/ S3C24X0_USB_DEVICE;
342
343
344 /* WATCH DOG TIMER (see manual chapter 18) */
345 typedef struct {
346 S3C24X0_REG32 WTCON;
347 S3C24X0_REG32 WTDAT;
348 S3C24X0_REG32 WTCNT;
349 } /*__attribute__((__packed__))*/ S3C24X0_WATCHDOG;
350
351
352 /* IIC (see manual chapter 20) */
353 typedef struct {
354 S3C24X0_REG32 IICCON;
355 S3C24X0_REG32 IICSTAT;
356 S3C24X0_REG32 IICADD;
357 S3C24X0_REG32 IICDS;
358 } /*__attribute__((__packed__))*/ S3C24X0_I2C;
359
360
361 /* IIS (see manual chapter 21) */
362 typedef struct {
363 #ifdef __BIG_ENDIAN
364 S3C24X0_REG16 res1;
365 S3C24X0_REG16 IISCON;
366 S3C24X0_REG16 res2;
367 S3C24X0_REG16 IISMOD;
368 S3C24X0_REG16 res3;
369 S3C24X0_REG16 IISPSR;
370 S3C24X0_REG16 res4;
371 S3C24X0_REG16 IISFCON;
372 S3C24X0_REG16 res5;
373 S3C24X0_REG16 IISFIFO;
374 #else /* little endian */
375 S3C24X0_REG16 IISCON;
376 S3C24X0_REG16 res1;
377 S3C24X0_REG16 IISMOD;
378 S3C24X0_REG16 res2;
379 S3C24X0_REG16 IISPSR;
380 S3C24X0_REG16 res3;
381 S3C24X0_REG16 IISFCON;
382 S3C24X0_REG16 res4;
383 S3C24X0_REG16 IISFIFO;
384 S3C24X0_REG16 res5;
385 #endif
386 } /*__attribute__((__packed__))*/ S3C24X0_I2S;
387
388
389 /* I/O PORT (see manual chapter 9) */
390 typedef struct {
391 #ifdef CONFIG_S3C2400
392 S3C24X0_REG32 PACON;
393 S3C24X0_REG32 PADAT;
394
395 S3C24X0_REG32 PBCON;
396 S3C24X0_REG32 PBDAT;
397 S3C24X0_REG32 PBUP;
398
399 S3C24X0_REG32 PCCON;
400 S3C24X0_REG32 PCDAT;
401 S3C24X0_REG32 PCUP;
402
403 S3C24X0_REG32 PDCON;
404 S3C24X0_REG32 PDDAT;
405 S3C24X0_REG32 PDUP;
406
407 S3C24X0_REG32 PECON;
408 S3C24X0_REG32 PEDAT;
409 S3C24X0_REG32 PEUP;
410
411 S3C24X0_REG32 PFCON;
412 S3C24X0_REG32 PFDAT;
413 S3C24X0_REG32 PFUP;
414
415 S3C24X0_REG32 PGCON;
416 S3C24X0_REG32 PGDAT;
417 S3C24X0_REG32 PGUP;
418
419 S3C24X0_REG32 OPENCR;
420
421 S3C24X0_REG32 MISCCR;
422 S3C24X0_REG32 EXTINT;
423 #endif
424 #ifdef CONFIG_S3C2410
425 S3C24X0_REG32 GPACON;
426 S3C24X0_REG32 GPADAT;
427 S3C24X0_REG32 res1[2];
428 S3C24X0_REG32 GPBCON;
429 S3C24X0_REG32 GPBDAT;
430 S3C24X0_REG32 GPBUP;
431 S3C24X0_REG32 res2;
432 S3C24X0_REG32 GPCCON;
433 S3C24X0_REG32 GPCDAT;
434 S3C24X0_REG32 GPCUP;
435 S3C24X0_REG32 res3;
436 S3C24X0_REG32 GPDCON;
437 S3C24X0_REG32 GPDDAT;
438 S3C24X0_REG32 GPDUP;
439 S3C24X0_REG32 res4;
440 S3C24X0_REG32 GPECON;
441 S3C24X0_REG32 GPEDAT;
442 S3C24X0_REG32 GPEUP;
443 S3C24X0_REG32 res5;
444 S3C24X0_REG32 GPFCON;
445 S3C24X0_REG32 GPFDAT;
446 S3C24X0_REG32 GPFUP;
447 S3C24X0_REG32 res6;
448 S3C24X0_REG32 GPGCON;
449 S3C24X0_REG32 GPGDAT;
450 S3C24X0_REG32 GPGUP;
451 S3C24X0_REG32 res7;
452 S3C24X0_REG32 GPHCON;
453 S3C24X0_REG32 GPHDAT;
454 S3C24X0_REG32 GPHUP;
455 S3C24X0_REG32 res8;
456
457 S3C24X0_REG32 MISCCR;
458 S3C24X0_REG32 DCLKCON;
459 S3C24X0_REG32 EXTINT0;
460 S3C24X0_REG32 EXTINT1;
461 S3C24X0_REG32 EXTINT2;
462 S3C24X0_REG32 EINTFLT0;
463 S3C24X0_REG32 EINTFLT1;
464 S3C24X0_REG32 EINTFLT2;
465 S3C24X0_REG32 EINTFLT3;
466 S3C24X0_REG32 EINTMASK;
467 S3C24X0_REG32 EINTPEND;
468 S3C24X0_REG32 GSTATUS0;
469 S3C24X0_REG32 GSTATUS1;
470 S3C24X0_REG32 GSTATUS2;
471 S3C24X0_REG32 GSTATUS3;
472 S3C24X0_REG32 GSTATUS4;
473 #endif
474 #if defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
475 S3C24X0_REG32 GPACON;
476 S3C24X0_REG32 GPADAT;
477 S3C24X0_REG32 res1[2];
478 S3C24X0_REG32 GPBCON;
479 S3C24X0_REG32 GPBDAT;
480 S3C24X0_REG32 GPBUP;
481 S3C24X0_REG32 res2;
482 S3C24X0_REG32 GPCCON;
483 S3C24X0_REG32 GPCDAT;
484 S3C24X0_REG32 GPCUP;
485 S3C24X0_REG32 res3;
486 S3C24X0_REG32 GPDCON;
487 S3C24X0_REG32 GPDDAT;
488 S3C24X0_REG32 GPDUP;
489 S3C24X0_REG32 res4;
490 S3C24X0_REG32 GPECON;
491 S3C24X0_REG32 GPEDAT;
492 S3C24X0_REG32 GPEUP;
493 S3C24X0_REG32 res5;
494 S3C24X0_REG32 GPFCON;
495 S3C24X0_REG32 GPFDAT;
496 S3C24X0_REG32 GPFUP;
497 S3C24X0_REG32 res6;
498 S3C24X0_REG32 GPGCON;
499 S3C24X0_REG32 GPGDAT;
500 S3C24X0_REG32 GPGUP;
501 S3C24X0_REG32 res7;
502 S3C24X0_REG32 GPHCON;
503 S3C24X0_REG32 GPHDAT;
504 S3C24X0_REG32 GPHUP;
505 S3C24X0_REG32 res8;
506
507 S3C24X0_REG32 MISCCR;
508 S3C24X0_REG32 DCLKCON;
509 S3C24X0_REG32 EXTINT0;
510 S3C24X0_REG32 EXTINT1;
511 S3C24X0_REG32 EXTINT2;
512 S3C24X0_REG32 EINTFLT0;
513 S3C24X0_REG32 EINTFLT1;
514 S3C24X0_REG32 EINTFLT2;
515 S3C24X0_REG32 EINTFLT3;
516 S3C24X0_REG32 EINTMASK;
517 S3C24X0_REG32 EINTPEND;
518 S3C24X0_REG32 GSTATUS0;
519 S3C24X0_REG32 GSTATUS1;
520 S3C24X0_REG32 GSTATUS2;
521 S3C24X0_REG32 GSTATUS3;
522 S3C24X0_REG32 GSTATUS4;
523
524 S3C24X0_REG32 res9;
525 S3C24X0_REG32 DSC0;
526 S3C24X0_REG32 DSC1;
527 S3C24X0_REG32 MSLCON;
528 S3C24X0_REG32 GPJCON;
529 S3C24X0_REG32 GPJDAT;
530 S3C24X0_REG32 GPJUP;
531 S3C24X0_REG32 res10;
532 #endif
533 } /*__attribute__((__packed__))*/ S3C24X0_GPIO;
534
535
536 /* RTC (see manual chapter 17) */
537 typedef struct {
538 #ifdef __BIG_ENDIAN
539 S3C24X0_REG8 res1[67];
540 S3C24X0_REG8 RTCCON;
541 S3C24X0_REG8 res2[3];
542 S3C24X0_REG8 TICNT;
543 S3C24X0_REG8 res3[11];
544 S3C24X0_REG8 RTCALM;
545 S3C24X0_REG8 res4[3];
546 S3C24X0_REG8 ALMSEC;
547 S3C24X0_REG8 res5[3];
548 S3C24X0_REG8 ALMMIN;
549 S3C24X0_REG8 res6[3];
550 S3C24X0_REG8 ALMHOUR;
551 S3C24X0_REG8 res7[3];
552 S3C24X0_REG8 ALMDATE;
553 S3C24X0_REG8 res8[3];
554 S3C24X0_REG8 ALMMON;
555 S3C24X0_REG8 res9[3];
556 S3C24X0_REG8 ALMYEAR;
557 S3C24X0_REG8 res10[3];
558 S3C24X0_REG8 RTCRST;
559 S3C24X0_REG8 res11[3];
560 S3C24X0_REG8 BCDSEC;
561 S3C24X0_REG8 res12[3];
562 S3C24X0_REG8 BCDMIN;
563 S3C24X0_REG8 res13[3];
564 S3C24X0_REG8 BCDHOUR;
565 S3C24X0_REG8 res14[3];
566 S3C24X0_REG8 BCDDATE;
567 S3C24X0_REG8 res15[3];
568 S3C24X0_REG8 BCDDAY;
569 S3C24X0_REG8 res16[3];
570 S3C24X0_REG8 BCDMON;
571 S3C24X0_REG8 res17[3];
572 S3C24X0_REG8 BCDYEAR;
573 #else /* little endian */
574 S3C24X0_REG8 res0[64];
575 S3C24X0_REG8 RTCCON;
576 S3C24X0_REG8 res1[3];
577 S3C24X0_REG8 TICNT;
578 S3C24X0_REG8 res2[11];
579 S3C24X0_REG8 RTCALM;
580 S3C24X0_REG8 res3[3];
581 S3C24X0_REG8 ALMSEC;
582 S3C24X0_REG8 res4[3];
583 S3C24X0_REG8 ALMMIN;
584 S3C24X0_REG8 res5[3];
585 S3C24X0_REG8 ALMHOUR;
586 S3C24X0_REG8 res6[3];
587 S3C24X0_REG8 ALMDATE;
588 S3C24X0_REG8 res7[3];
589 S3C24X0_REG8 ALMMON;
590 S3C24X0_REG8 res8[3];
591 S3C24X0_REG8 ALMYEAR;
592 S3C24X0_REG8 res9[3];
593 S3C24X0_REG8 RTCRST;
594 S3C24X0_REG8 res10[3];
595 S3C24X0_REG8 BCDSEC;
596 S3C24X0_REG8 res11[3];
597 S3C24X0_REG8 BCDMIN;
598 S3C24X0_REG8 res12[3];
599 S3C24X0_REG8 BCDHOUR;
600 S3C24X0_REG8 res13[3];
601 S3C24X0_REG8 BCDDATE;
602 S3C24X0_REG8 res14[3];
603 S3C24X0_REG8 BCDDAY;
604 S3C24X0_REG8 res15[3];
605 S3C24X0_REG8 BCDMON;
606 S3C24X0_REG8 res16[3];
607 S3C24X0_REG8 BCDYEAR;
608 S3C24X0_REG8 res17[3];
609 #endif
610 } /*__attribute__((__packed__))*/ S3C24X0_RTC;
611
612
613 /* ADC (see manual chapter 16) */
614 typedef struct {
615 S3C24X0_REG32 ADCCON;
616 S3C24X0_REG32 ADCDAT;
617 } /*__attribute__((__packed__))*/ S3C2400_ADC;
618
619
620 /* ADC (see manual chapter 16) */
621 typedef struct {
622 S3C24X0_REG32 ADCCON;
623 S3C24X0_REG32 ADCTSC;
624 S3C24X0_REG32 ADCDLY;
625 S3C24X0_REG32 ADCDAT0;
626 S3C24X0_REG32 ADCDAT1;
627 } /*__attribute__((__packed__))*/ S3C2410_ADC;
628
629
630 /* SPI (see manual chapter 22) */
631 typedef struct {
632 S3C24X0_REG32 SPCON;
633 S3C24X0_REG32 SPSTA;
634 S3C24X0_REG32 SPPIN;
635 S3C24X0_REG32 SPPRE;
636 S3C24X0_REG32 SPTDAT;
637 S3C24X0_REG32 SPRDAT;
638 S3C24X0_REG32 res[2];
639 } __attribute__((__packed__)) S3C24X0_SPI_CHANNEL;
640
641 typedef struct {
642 S3C24X0_SPI_CHANNEL ch[S3C24X0_SPI_CHANNELS];
643 } /*__attribute__((__packed__))*/ S3C24X0_SPI;
644
645
646 /* MMC INTERFACE (see S3C2400 manual chapter 19) */
647 typedef struct {
648 #ifdef __BIG_ENDIAN
649 S3C24X0_REG8 res1[3];
650 S3C24X0_REG8 MMCON;
651 S3C24X0_REG8 res2[3];
652 S3C24X0_REG8 MMCRR;
653 S3C24X0_REG8 res3[3];
654 S3C24X0_REG8 MMFCON;
655 S3C24X0_REG8 res4[3];
656 S3C24X0_REG8 MMSTA;
657 S3C24X0_REG16 res5;
658 S3C24X0_REG16 MMFSTA;
659 S3C24X0_REG8 res6[3];
660 S3C24X0_REG8 MMPRE;
661 S3C24X0_REG16 res7;
662 S3C24X0_REG16 MMLEN;
663 S3C24X0_REG8 res8[3];
664 S3C24X0_REG8 MMCR7;
665 S3C24X0_REG32 MMRSP[4];
666 S3C24X0_REG8 res9[3];
667 S3C24X0_REG8 MMCMD0;
668 S3C24X0_REG32 MMCMD1;
669 S3C24X0_REG16 res10;
670 S3C24X0_REG16 MMCR16;
671 S3C24X0_REG8 res11[3];
672 S3C24X0_REG8 MMDAT;
673 #else
674 S3C24X0_REG8 MMCON;
675 S3C24X0_REG8 res1[3];
676 S3C24X0_REG8 MMCRR;
677 S3C24X0_REG8 res2[3];
678 S3C24X0_REG8 MMFCON;
679 S3C24X0_REG8 res3[3];
680 S3C24X0_REG8 MMSTA;
681 S3C24X0_REG8 res4[3];
682 S3C24X0_REG16 MMFSTA;
683 S3C24X0_REG16 res5;
684 S3C24X0_REG8 MMPRE;
685 S3C24X0_REG8 res6[3];
686 S3C24X0_REG16 MMLEN;
687 S3C24X0_REG16 res7;
688 S3C24X0_REG8 MMCR7;
689 S3C24X0_REG8 res8[3];
690 S3C24X0_REG32 MMRSP[4];
691 S3C24X0_REG8 MMCMD0;
692 S3C24X0_REG8 res9[3];
693 S3C24X0_REG32 MMCMD1;
694 S3C24X0_REG16 MMCR16;
695 S3C24X0_REG16 res10;
696 S3C24X0_REG8 MMDAT;
697 S3C24X0_REG8 res11[3];
698 #endif
699 } /*__attribute__((__packed__))*/ S3C2400_MMC;
700
701
702 /* SD INTERFACE (see S3C2410 manual chapter 19) */
703 typedef struct {
704 S3C24X0_REG32 SDICON;
705 S3C24X0_REG32 SDIPRE;
706 S3C24X0_REG32 SDICARG;
707 S3C24X0_REG32 SDICCON;
708 S3C24X0_REG32 SDICSTA;
709 S3C24X0_REG32 SDIRSP0;
710 S3C24X0_REG32 SDIRSP1;
711 S3C24X0_REG32 SDIRSP2;
712 S3C24X0_REG32 SDIRSP3;
713 S3C24X0_REG32 SDIDTIMER;
714 S3C24X0_REG32 SDIBSIZE;
715 S3C24X0_REG32 SDIDCON;
716 S3C24X0_REG32 SDIDCNT;
717 S3C24X0_REG32 SDIDSTA;
718 S3C24X0_REG32 SDIFSTA;
719 #if defined(CONFIG_S3C2410)
720 S3C24X0_REG32 SDIDAT;
721 S3C24X0_REG32 SDIIMSK;
722 #elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
723 S3C24X0_REG32 SDIIMSK;
724 S3C24X0_REG32 SDIDAT;
725 #endif
726 } /*__attribute__((__packed__))*/ S3C2410_SDI;
727
728
729 #if 0
730 /* Memory control */
731 #define rBWSCON (*(volatile unsigned *)0x48000000)
732 #define rBANKCON0 (*(volatile unsigned *)0x48000004)
733 #define rBANKCON1 (*(volatile unsigned *)0x48000008)
734 #define rBANKCON2 (*(volatile unsigned *)0x4800000C)
735 #define rBANKCON3 (*(volatile unsigned *)0x48000010)
736 #define rBANKCON4 (*(volatile unsigned *)0x48000014)
737 #define rBANKCON5 (*(volatile unsigned *)0x48000018)
738 #define rBANKCON6 (*(volatile unsigned *)0x4800001C)
739 #define rBANKCON7 (*(volatile unsigned *)0x48000020)
740 #define rREFRESH (*(volatile unsigned *)0x48000024)
741 #define rBANKSIZE (*(volatile unsigned *)0x48000028)
742 #define rMRSRB6 (*(volatile unsigned *)0x4800002C)
743 #define rMRSRB7 (*(volatile unsigned *)0x48000030)
744
745
746 /* USB HOST */
747 #define rHcRevision (*(volatile unsigned *)0x49000000)
748 #define rHcControl (*(volatile unsigned *)0x49000004)
749 #define rHcCommonStatus (*(volatile unsigned *)0x49000008)
750 #define rHcInterruptStatus (*(volatile unsigned *)0x4900000C)
751 #define rHcInterruptEnable (*(volatile unsigned *)0x49000010)
752 #define rHcInterruptDisable (*(volatile unsigned *)0x49000014)
753 #define rHcHCCA (*(volatile unsigned *)0x49000018)
754 #define rHcPeriodCuttendED (*(volatile unsigned *)0x4900001C)
755 #define rHcControlHeadED (*(volatile unsigned *)0x49000020)
756 #define rHcControlCurrentED (*(volatile unsigned *)0x49000024)
757 #define rHcBulkHeadED (*(volatile unsigned *)0x49000028)
758 #define rHcBuldCurrentED (*(volatile unsigned *)0x4900002C)
759 #define rHcDoneHead (*(volatile unsigned *)0x49000030)
760 #define rHcRmInterval (*(volatile unsigned *)0x49000034)
761 #define rHcFmRemaining (*(volatile unsigned *)0x49000038)
762 #define rHcFmNumber (*(volatile unsigned *)0x4900003C)
763 #define rHcPeriodicStart (*(volatile unsigned *)0x49000040)
764 #define rHcLSThreshold (*(volatile unsigned *)0x49000044)
765 #define rHcRhDescriptorA (*(volatile unsigned *)0x49000048)
766 #define rHcRhDescriptorB (*(volatile unsigned *)0x4900004C)
767 #define rHcRhStatus (*(volatile unsigned *)0x49000050)
768 #define rHcRhPortStatus1 (*(volatile unsigned *)0x49000054)
769 #define rHcRhPortStatus2 (*(volatile unsigned *)0x49000058)
770
771
772 /* INTERRUPT */
773 #define rSRCPND (*(volatile unsigned *)0x4A000000)
774 #define rINTMOD (*(volatile unsigned *)0x4A000004)
775 #define rINTMSK (*(volatile unsigned *)0x4A000008)
776 #define rPRIORITY (*(volatile unsigned *)0x4A00000C)
777 #define rINTPND (*(volatile unsigned *)0x4A000010)
778 #define rINTOFFSET (*(volatile unsigned *)0x4A000014)
779 #define rSUBSRCPND (*(volatile unsigned *)0x4A000018)
780 #define rINTSUBMSK (*(volatile unsigned *)0x4A00001C)
781
782
783 /* DMA */
784 #define rDISRC0 (*(volatile unsigned *)0x4B000000)
785 #define rDISRCC0 (*(volatile unsigned *)0x4B000004)
786 #define rDIDST0 (*(volatile unsigned *)0x4B000008)
787 #define rDIDSTC0 (*(volatile unsigned *)0x4B00000C)
788 #define rDCON0 (*(volatile unsigned *)0x4B000010)
789 #define rDSTAT0 (*(volatile unsigned *)0x4B000014)
790 #define rDCSRC0 (*(volatile unsigned *)0x4B000018)
791 #define rDCDST0 (*(volatile unsigned *)0x4B00001C)
792 #define rDMASKTRIG0 (*(volatile unsigned *)0x4B000020)
793 #define rDISRC1 (*(volatile unsigned *)0x4B000040)
794 #define rDISRCC1 (*(volatile unsigned *)0x4B000044)
795 #define rDIDST1 (*(volatile unsigned *)0x4B000048)
796 #define rDIDSTC1 (*(volatile unsigned *)0x4B00004C)
797 #define rDCON1 (*(volatile unsigned *)0x4B000050)
798 #define rDSTAT1 (*(volatile unsigned *)0x4B000054)
799 #define rDCSRC1 (*(volatile unsigned *)0x4B000058)
800 #define rDCDST1 (*(volatile unsigned *)0x4B00005C)
801 #define rDMASKTRIG1 (*(volatile unsigned *)0x4B000060)
802 #define rDISRC2 (*(volatile unsigned *)0x4B000080)
803 #define rDISRCC2 (*(volatile unsigned *)0x4B000084)
804 #define rDIDST2 (*(volatile unsigned *)0x4B000088)
805 #define rDIDSTC2 (*(volatile unsigned *)0x4B00008C)
806 #define rDCON2 (*(volatile unsigned *)0x4B000090)
807 #define rDSTAT2 (*(volatile unsigned *)0x4B000094)
808 #define rDCSRC2 (*(volatile unsigned *)0x4B000098)
809 #define rDCDST2 (*(volatile unsigned *)0x4B00009C)
810 #define rDMASKTRIG2 (*(volatile unsigned *)0x4B0000A0)
811 #define rDISRC3 (*(volatile unsigned *)0x4B0000C0)
812 #define rDISRCC3 (*(volatile unsigned *)0x4B0000C4)
813 #define rDIDST3 (*(volatile unsigned *)0x4B0000C8)
814 #define rDIDSTC3 (*(volatile unsigned *)0x4B0000CC)
815 #define rDCON3 (*(volatile unsigned *)0x4B0000D0)
816 #define rDSTAT3 (*(volatile unsigned *)0x4B0000D4)
817 #define rDCSRC3 (*(volatile unsigned *)0x4B0000D8)
818 #define rDCDST3 (*(volatile unsigned *)0x4B0000DC)
819 #define rDMASKTRIG3 (*(volatile unsigned *)0x4B0000E0)
820
821
822 /* CLOCK & POWER MANAGEMENT */
823 #define rLOCKTIME (*(volatile unsigned *)0x4C000000)
824 #define rMPLLCON (*(volatile unsigned *)0x4C000004)
825 #define rUPLLCON (*(volatile unsigned *)0x4C000008)
826 #define rCLKCON (*(volatile unsigned *)0x4C00000C)
827 #define rCLKSLOW (*(volatile unsigned *)0x4C000010)
828 #define rCLKDIVN (*(volatile unsigned *)0x4C000014)
829
830
831 /* LCD CONTROLLER */
832 #define rLCDCON1 (*(volatile unsigned *)0x4D000000)
833 #define rLCDCON2 (*(volatile unsigned *)0x4D000004)
834 #define rLCDCON3 (*(volatile unsigned *)0x4D000008)
835 #define rLCDCON4 (*(volatile unsigned *)0x4D00000C)
836 #define rLCDCON5 (*(volatile unsigned *)0x4D000010)
837 #define rLCDSADDR1 (*(volatile unsigned *)0x4D000014)
838 #define rLCDSADDR2 (*(volatile unsigned *)0x4D000018)
839 #define rLCDSADDR3 (*(volatile unsigned *)0x4D00001C)
840 #define rREDLUT (*(volatile unsigned *)0x4D000020)
841 #define rGREENLUT (*(volatile unsigned *)0x4D000024)
842 #define rBLUELUT (*(volatile unsigned *)0x4D000028)
843 #define rDITHMODE (*(volatile unsigned *)0x4D00004C)
844 #define rTPAL (*(volatile unsigned *)0x4D000050)
845 #define rLCDINTPND (*(volatile unsigned *)0x4D000054)
846 #define rLCDSRCPND (*(volatile unsigned *)0x4D000058)
847 #define rLCDINTMSK (*(volatile unsigned *)0x4D00005C)
848
849
850 /* NAND FLASH */
851 #define rNFCONF (*(volatile unsigned *)0x4E000000)
852 #define rNFCMD (*(volatile unsigned *)0x4E000004)
853 #define rNFADDR (*(volatile unsigned *)0x4E000008)
854 #define rNFDATA (*(volatile unsigned *)0x4E00000C)
855 #define rNFSTAT (*(volatile unsigned *)0x4E000010)
856 #define rNFECC (*(volatile unsigned *)0x4E000014)
857
858
859 /* UART */
860 #define rULCON0 (*(volatile unsigned *)0x50000000)
861 #define rUCON0 (*(volatile unsigned *)0x50000004)
862 #define rUFCON0 (*(volatile unsigned *)0x50000008)
863 #define rUMCON0 (*(volatile unsigned *)0x5000000C)
864 #define rUTRSTAT0 (*(volatile unsigned *)0x50000010)
865 #define rUERSTAT0 (*(volatile unsigned *)0x50000014)
866 #define rUFSTAT0 (*(volatile unsigned *)0x50000018)
867 #define rUMSTAT0 (*(volatile unsigned *)0x5000001C)
868 #define rUBRDIV0 (*(volatile unsigned *)0x50000028)
869
870 #define rULCON1 (*(volatile unsigned *)0x50004000)
871 #define rUCON1 (*(volatile unsigned *)0x50004004)
872 #define rUFCON1 (*(volatile unsigned *)0x50004008)
873 #define rUMCON1 (*(volatile unsigned *)0x5000400C)
874 #define rUTRSTAT1 (*(volatile unsigned *)0x50004010)
875 #define rUERSTAT1 (*(volatile unsigned *)0x50004014)
876 #define rUFSTAT1 (*(volatile unsigned *)0x50004018)
877 #define rUMSTAT1 (*(volatile unsigned *)0x5000401C)
878 #define rUBRDIV1 (*(volatile unsigned *)0x50004028)
879
880 #define rULCON2 (*(volatile unsigned *)0x50008000)
881 #define rUCON2 (*(volatile unsigned *)0x50008004)
882 #define rUFCON2 (*(volatile unsigned *)0x50008008)
883 #define rUTRSTAT2 (*(volatile unsigned *)0x50008010)
884 #define rUERSTAT2 (*(volatile unsigned *)0x50008014)
885 #define rUFSTAT2 (*(volatile unsigned *)0x50008018)
886 #define rUBRDIV2 (*(volatile unsigned *)0x50008028)
887
888 #ifdef __BIG_ENDIAN
889 #define rUTXH0 (*(volatile unsigned char *)0x50000023)
890 #define rURXH0 (*(volatile unsigned char *)0x50000027)
891 #define rUTXH1 (*(volatile unsigned char *)0x50004023)
892 #define rURXH1 (*(volatile unsigned char *)0x50004027)
893 #define rUTXH2 (*(volatile unsigned char *)0x50008023)
894 #define rURXH2 (*(volatile unsigned char *)0x50008027)
895
896 #define WrUTXH0(ch) (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch)
897 #define RdURXH0() (*(volatile unsigned char *)0x50000027)
898 #define WrUTXH1(ch) (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch)
899 #define RdURXH1() (*(volatile unsigned char *)0x50004027)
900 #define WrUTXH2(ch) (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch)
901 #define RdURXH2() (*(volatile unsigned char *)0x50008027)
902
903 #define UTXH0 (0x50000020+3) /* byte_access address by DMA */
904 #define URXH0 (0x50000024+3)
905 #define UTXH1 (0x50004020+3)
906 #define URXH1 (0x50004024+3)
907 #define UTXH2 (0x50008020+3)
908 #define URXH2 (0x50008024+3)
909
910 #else /* Little Endian */
911 #define rUTXH0 (*(volatile unsigned char *)0x50000020)
912 #define rURXH0 (*(volatile unsigned char *)0x50000024)
913 #define rUTXH1 (*(volatile unsigned char *)0x50004020)
914 #define rURXH1 (*(volatile unsigned char *)0x50004024)
915 #define rUTXH2 (*(volatile unsigned char *)0x50008020)
916 #define rURXH2 (*(volatile unsigned char *)0x50008024)
917
918 #define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch)
919 #define RdURXH0() (*(volatile unsigned char *)0x50000024)
920 #define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch)
921 #define RdURXH1() (*(volatile unsigned char *)0x50004024)
922 #define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch)
923 #define RdURXH2() (*(volatile unsigned char *)0x50008024)
924
925 #define UTXH0 (0x50000020) /* byte_access address by DMA */
926 #define URXH0 (0x50000024)
927 #define UTXH1 (0x50004020)
928 #define URXH1 (0x50004024)
929 #define UTXH2 (0x50008020)
930 #define URXH2 (0x50008024)
931 #endif
932
933
934 /* PWM TIMER */
935 #define rTCFG0 (*(volatile unsigned *)0x51000000)
936 #define rTCFG1 (*(volatile unsigned *)0x51000004)
937 #define rTCON (*(volatile unsigned *)0x51000008)
938 #define rTCNTB0 (*(volatile unsigned *)0x5100000C)
939 #define rTCMPB0 (*(volatile unsigned *)0x51000010)
940 #define rTCNTO0 (*(volatile unsigned *)0x51000014)
941 #define rTCNTB1 (*(volatile unsigned *)0x51000018)
942 #define rTCMPB1 (*(volatile unsigned *)0x5100001C)
943 #define rTCNTO1 (*(volatile unsigned *)0x51000020)
944 #define rTCNTB2 (*(volatile unsigned *)0x51000024)
945 #define rTCMPB2 (*(volatile unsigned *)0x51000028)
946 #define rTCNTO2 (*(volatile unsigned *)0x5100002C)
947 #define rTCNTB3 (*(volatile unsigned *)0x51000030)
948 #define rTCMPB3 (*(volatile unsigned *)0x51000034)
949 #define rTCNTO3 (*(volatile unsigned *)0x51000038)
950 #define rTCNTB4 (*(volatile unsigned *)0x5100003C)
951 #define rTCNTO4 (*(volatile unsigned *)0x51000040)
952
953
954 /* USB DEVICE */
955 #ifdef __BIG_ENDIAN
956 #define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000143)
957 #define rPWR_REG (*(volatile unsigned char *)0x52000147)
958 #define rEP_INT_REG (*(volatile unsigned char *)0x5200014B)
959 #define rUSB_INT_REG (*(volatile unsigned char *)0x5200015B)
960 #define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015F)
961 #define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016F)
962 #define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000173)
963 #define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000177)
964 #define rINDEX_REG (*(volatile unsigned char *)0x5200017B)
965 #define rMAXP_REG (*(volatile unsigned char *)0x52000183)
966 #define rEP0_CSR (*(volatile unsigned char *)0x52000187)
967 #define rIN_CSR1_REG (*(volatile unsigned char *)0x52000187)
968 #define rIN_CSR2_REG (*(volatile unsigned char *)0x5200018B)
969 #define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000193)
970 #define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000197)
971 #define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x5200019B)
972 #define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019F)
973 #define rEP0_FIFO (*(volatile unsigned char *)0x520001C3)
974 #define rEP1_FIFO (*(volatile unsigned char *)0x520001C7)
975 #define rEP2_FIFO (*(volatile unsigned char *)0x520001CB)
976 #define rEP3_FIFO (*(volatile unsigned char *)0x520001CF)
977 #define rEP4_FIFO (*(volatile unsigned char *)0x520001D3)
978 #define rEP1_DMA_CON (*(volatile unsigned char *)0x52000203)
979 #define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000207)
980 #define rEP1_DMA_FIFO (*(volatile unsigned char *)0x5200020B)
981 #define rEP1_DMA_TX_LO (*(volatile unsigned char *)0x5200020F)
982 #define rEP1_DMA_TX_MD (*(volatile unsigned char *)0x52000213)
983 #define rEP1_DMA_TX_HI (*(volatile unsigned char *)0x52000217)
984 #define rEP2_DMA_CON (*(volatile unsigned char *)0x5200021B)
985 #define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021F)
986 #define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000223)
987 #define rEP2_DMA_TX_LO (*(volatile unsigned char *)0x52000227)
988 #define rEP2_DMA_TX_MD (*(volatile unsigned char *)0x5200022B)
989 #define rEP2_DMA_TX_HI (*(volatile unsigned char *)0x5200022F)
990 #define rEP3_DMA_CON (*(volatile unsigned char *)0x52000243)
991 #define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000247)
992 #define rEP3_DMA_FIFO (*(volatile unsigned char *)0x5200024B)
993 #define rEP3_DMA_TX_LO (*(volatile unsigned char *)0x5200024F)
994 #define rEP3_DMA_TX_MD (*(volatile unsigned char *)0x52000253)
995 #define rEP3_DMA_TX_HI (*(volatile unsigned char *)0x52000257)
996 #define rEP4_DMA_CON (*(volatile unsigned char *)0x5200025B)
997 #define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025F)
998 #define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000263)
999 #define rEP4_DMA_TX_LO (*(volatile unsigned char *)0x52000267)
1000 #define rEP4_DMA_TX_MD (*(volatile unsigned char *)0x5200026B)
1001 #define rEP4_DMA_TX_HI (*(volatile unsigned char *)0x5200026F)
1002 #else /* little endian */
1003 #define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000140)
1004 #define rPWR_REG (*(volatile unsigned char *)0x52000144)
1005 #define rEP_INT_REG (*(volatile unsigned char *)0x52000148)
1006 #define rUSB_INT_REG (*(volatile unsigned char *)0x52000158)
1007 #define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015C)
1008 #define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016C)
1009 #define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000170)
1010 #define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000174)
1011 #define rINDEX_REG (*(volatile unsigned char *)0x52000178)
1012 #define rMAXP_REG (*(volatile unsigned char *)0x52000180)
1013 #define rEP0_CSR (*(volatile unsigned char *)0x52000184)
1014 #define rIN_CSR1_REG (*(volatile unsigned char *)0x52000184)
1015 #define rIN_CSR2_REG (*(volatile unsigned char *)0x52000188)
1016 #define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000190)
1017 #define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000194)
1018 #define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x52000198)
1019 #define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019C)
1020 #define rEP0_FIFO (*(volatile unsigned char *)0x520001C0)
1021 #define rEP1_FIFO (*(volatile unsigned char *)0x520001C4)
1022 #define rEP2_FIFO (*(volatile unsigned char *)0x520001C8)
1023 #define rEP3_FIFO (*(volatile unsigned char *)0x520001CC)
1024 #define rEP4_FIFO (*(volatile unsigned char *)0x520001D0)
1025 #define rEP1_DMA_CON (*(volatile unsigned char *)0x52000200)
1026 #define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000204)
1027 #define rEP1_DMA_FIFO (*(volatile unsigned char *)0x52000208)
1028 #define rEP1_DMA_TX_LO (*(volatile unsigned char *)0x5200020C)
1029 #define rEP1_DMA_TX_MD (*(volatile unsigned char *)0x52000210)
1030 #define rEP1_DMA_TX_HI (*(volatile unsigned char *)0x52000214)
1031 #define rEP2_DMA_CON (*(volatile unsigned char *)0x52000218)
1032 #define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021C)
1033 #define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000220)
1034 #define rEP2_DMA_TX_LO (*(volatile unsigned char *)0x52000224)
1035 #define rEP2_DMA_TX_MD (*(volatile unsigned char *)0x52000228)
1036 #define rEP2_DMA_TX_HI (*(volatile unsigned char *)0x5200022C)
1037 #define rEP3_DMA_CON (*(volatile unsigned char *)0x52000240)
1038 #define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000244)
1039 #define rEP3_DMA_FIFO (*(volatile unsigned char *)0x52000248)
1040 #define rEP3_DMA_TX_LO (*(volatile unsigned char *)0x5200024C)
1041 #define rEP3_DMA_TX_MD (*(volatile unsigned char *)0x52000250)
1042 #define rEP3_DMA_TX_HI (*(volatile unsigned char *)0x52000254)
1043 #define rEP4_DMA_CON (*(volatile unsigned char *)0x52000258)
1044 #define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025C)
1045 #define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000260)
1046 #define rEP4_DMA_TX_LO (*(volatile unsigned char *)0x52000264)
1047 #define rEP4_DMA_TX_MD (*(volatile unsigned char *)0x52000268)
1048 #define rEP4_DMA_TX_HI (*(volatile unsigned char *)0x5200026C)
1049 #endif /* __BIG_ENDIAN */
1050
1051
1052 /* WATCH DOG TIMER */
1053 #define rWTCON (*(volatile unsigned *)0x53000000)
1054 #define rWTDAT (*(volatile unsigned *)0x53000004)
1055 #define rWTCNT (*(volatile unsigned *)0x53000008)
1056
1057
1058 /* IIC */
1059 #define rIICCON (*(volatile unsigned *)0x54000000)
1060 #define rIICSTAT (*(volatile unsigned *)0x54000004)
1061 #define rIICADD (*(volatile unsigned *)0x54000008)
1062 #define rIICDS (*(volatile unsigned *)0x5400000C)
1063
1064
1065 /* IIS */
1066 #define rIISCON (*(volatile unsigned *)0x55000000)
1067 #define rIISMOD (*(volatile unsigned *)0x55000004)
1068 #define rIISPSR (*(volatile unsigned *)0x55000008)
1069 #define rIISFCON (*(volatile unsigned *)0x5500000C)
1070
1071 #ifdef __BIG_ENDIAN
1072 #define IISFIF ((volatile unsigned short *)0x55000012)
1073 #else /* little endian */
1074 #define IISFIF ((volatile unsigned short *)0x55000010)
1075 #endif
1076
1077
1078 /* I/O PORT */
1079 #define rGPACON (*(volatile unsigned *)0x56000000)
1080 #define rGPADAT (*(volatile unsigned *)0x56000004)
1081
1082 #define rGPBCON (*(volatile unsigned *)0x56000010)
1083 #define rGPBDAT (*(volatile unsigned *)0x56000014)
1084 #define rGPBUP (*(volatile unsigned *)0x56000018)
1085
1086 #define rGPCCON (*(volatile unsigned *)0x56000020)
1087 #define rGPCDAT (*(volatile unsigned *)0x56000024)
1088 #define rGPCUP (*(volatile unsigned *)0x56000028)
1089
1090 #define rGPDCON (*(volatile unsigned *)0x56000030)
1091 #define rGPDDAT (*(volatile unsigned *)0x56000034)
1092 #define rGPDUP (*(volatile unsigned *)0x56000038)
1093
1094 #define rGPECON (*(volatile unsigned *)0x56000040)
1095 #define rGPEDAT (*(volatile unsigned *)0x56000044)
1096 #define rGPEUP (*(volatile unsigned *)0x56000048)
1097
1098 #define rGPFCON (*(volatile unsigned *)0x56000050)
1099 #define rGPFDAT (*(volatile unsigned *)0x56000054)
1100 #define rGPFUP (*(volatile unsigned *)0x56000058)
1101
1102 #define rGPGCON (*(volatile unsigned *)0x56000060)
1103 #define rGPGDAT (*(volatile unsigned *)0x56000064)
1104 #define rGPGUP (*(volatile unsigned *)0x56000068)
1105
1106 #define rGPHCON (*(volatile unsigned *)0x56000070)
1107 #define rGPHDAT (*(volatile unsigned *)0x56000074)
1108 #define rGPHUP (*(volatile unsigned *)0x56000078)
1109
1110 #define rMISCCR (*(volatile unsigned *)0x56000080)
1111 #define rDCLKCON (*(volatile unsigned *)0x56000084)
1112 #define rEXTINT0 (*(volatile unsigned *)0x56000088)
1113 #define rEXTINT1 (*(volatile unsigned *)0x5600008C)
1114 #define rEXTINT2 (*(volatile unsigned *)0x56000090)
1115 #define rEINTFLT0 (*(volatile unsigned *)0x56000094)
1116 #define rEINTFLT1 (*(volatile unsigned *)0x56000098)
1117 #define rEINTFLT2 (*(volatile unsigned *)0x5600009C)
1118 #define rEINTFLT3 (*(volatile unsigned *)0x560000A0)
1119 #define rEINTMASK (*(volatile unsigned *)0x560000A4)
1120 #define rEINTPEND (*(volatile unsigned *)0x560000A8)
1121 #define rGSTATUS0 (*(volatile unsigned *)0x560000AC)
1122 #define rGSTATUS1 (*(volatile unsigned *)0x560000B0)
1123
1124
1125 /* RTC */
1126 #ifdef __BIG_ENDIAN
1127 #define rRTCCON (*(volatile unsigned char *)0x57000043)
1128 #define rTICNT (*(volatile unsigned char *)0x57000047)
1129 #define rRTCALM (*(volatile unsigned char *)0x57000053)
1130 #define rALMSEC (*(volatile unsigned char *)0x57000057)
1131 #define rALMMIN (*(volatile unsigned char *)0x5700005B)
1132 #define rALMHOUR (*(volatile unsigned char *)0x5700005F)
1133 #define rALMDATE (*(volatile unsigned char *)0x57000063)
1134 #define rALMMON (*(volatile unsigned char *)0x57000067)
1135 #define rALMYEAR (*(volatile unsigned char *)0x5700006B)
1136 #define rRTCRST (*(volatile unsigned char *)0x5700006F)
1137 #define rBCDSEC (*(volatile unsigned char *)0x57000073)
1138 #define rBCDMIN (*(volatile unsigned char *)0x57000077)
1139 #define rBCDHOUR (*(volatile unsigned char *)0x5700007B)
1140 #define rBCDDATE (*(volatile unsigned char *)0x5700007F)
1141 #define rBCDDAY (*(volatile unsigned char *)0x57000083)
1142 #define rBCDMON (*(volatile unsigned char *)0x57000087)
1143 #define rBCDYEAR (*(volatile unsigned char *)0x5700008B)
1144 #else /* little endian */
1145 #define rRTCCON (*(volatile unsigned char *)0x57000040)
1146 #define rTICNT (*(volatile unsigned char *)0x57000044)
1147 #define rRTCALM (*(volatile unsigned char *)0x57000050)
1148 #define rALMSEC (*(volatile unsigned char *)0x57000054)
1149 #define rALMMIN (*(volatile unsigned char *)0x57000058)
1150 #define rALMHOUR (*(volatile unsigned char *)0x5700005C)
1151 #define rALMDATE (*(volatile unsigned char *)0x57000060)
1152 #define rALMMON (*(volatile unsigned char *)0x57000064)
1153 #define rALMYEAR (*(volatile unsigned char *)0x57000068)
1154 #define rRTCRST (*(volatile unsigned char *)0x5700006C)
1155 #define rBCDSEC (*(volatile unsigned char *)0x57000070)
1156 #define rBCDMIN (*(volatile unsigned char *)0x57000074)
1157 #define rBCDHOUR (*(volatile unsigned char *)0x57000078)
1158 #define rBCDDATE (*(volatile unsigned char *)0x5700007C)
1159 #define rBCDDAY (*(volatile unsigned char *)0x57000080)
1160 #define rBCDMON (*(volatile unsigned char *)0x57000084)
1161 #define rBCDYEAR (*(volatile unsigned char *)0x57000088)
1162 #endif
1163
1164
1165 /* ADC */
1166 #define rADCCON (*(volatile unsigned *)0x58000000)
1167 #define rADCTSC (*(volatile unsigned *)0x58000004)
1168 #define rADCDLY (*(volatile unsigned *)0x58000008)
1169 #define rADCDAT0 (*(volatile unsigned *)0x5800000C)
1170 #define rADCDAT1 (*(volatile unsigned *)0x58000010)
1171
1172
1173 /* SPI */
1174 #define rSPCON0 (*(volatile unsigned *)0x59000000)
1175 #define rSPSTA0 (*(volatile unsigned *)0x59000004)
1176 #define rSPPIN0 (*(volatile unsigned *)0x59000008)
1177 #define rSPPRE0 (*(volatile unsigned *)0x5900000C)
1178 #define rSPTDAT0 (*(volatile unsigned *)0x59000010)
1179 #define rSPRDAT0 (*(volatile unsigned *)0x59000014)
1180 #define rSPCON1 (*(volatile unsigned *)0x59000020)
1181 #define rSPSTA1 (*(volatile unsigned *)0x59000024)
1182 #define rSPPIN1 (*(volatile unsigned *)0x59000028)
1183 #define rSPPRE1 (*(volatile unsigned *)0x5900002C)
1184 #define rSPTDAT1 (*(volatile unsigned *)0x59000030)
1185 #define rSPRDAT1 (*(volatile unsigned *)0x59000034)
1186
1187
1188 /* SD INTERFACE */
1189 #define rSDICON (*(volatile unsigned *)0x5A000000)
1190 #define rSDIPRE (*(volatile unsigned *)0x5A000004)
1191 #define rSDICmdArg (*(volatile unsigned *)0x5A000008)
1192 #define rSDICmdCon (*(volatile unsigned *)0x5A00000C)
1193 #define rSDICmdSta (*(volatile unsigned *)0x5A000010)
1194 #define rSDIRSP0 (*(volatile unsigned *)0x5A000014)
1195 #define rSDIRSP1 (*(volatile unsigned *)0x5A000018)
1196 #define rSDIRSP2 (*(volatile unsigned *)0x5A00001C)
1197 #define rSDIRSP3 (*(volatile unsigned *)0x5A000020)
1198 #define rSDIDTimer (*(volatile unsigned *)0x5A000024)
1199 #define rSDIBSize (*(volatile unsigned *)0x5A000028)
1200 #define rSDIDatCon (*(volatile unsigned *)0x5A00002C)
1201 #define rSDIDatCnt (*(volatile unsigned *)0x5A000030)
1202 #define rSDIDatSta (*(volatile unsigned *)0x5A000034)
1203 #define rSDIFSTA (*(volatile unsigned *)0x5A000038)
1204 #define rSDIDAT (*(volatile unsigned *)0x5A00003C)
1205 #define rSDIIntMsk (*(volatile unsigned *)0x5A000040)
1206
1207 #endif
1208
1209 int __board_nand_init(struct nand_chip *nand);
1210
1211 #endif /*__S3C24X0_H__*/
Fork of the u-boot for for Samsung based MINI2440 board