2 * Memory Setup stuff - taken from blob memsetup.S
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
7 * Modified for the Samsung SMDK2410 by
9 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 /* some parameters for the board */
39 * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
41 * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
45 #define BWSCON 0x48000000
46 # define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
47 # define INTSUBMSK 0x4A00001C
56 #define B1_BWSCON (DW32)
57 #define B2_BWSCON (DW16)
58 #define B3_BWSCON (DW16 + WAIT + UBLB)
59 #define B4_BWSCON (DW16 + WAIT + UBLB)
60 #define B5_BWSCON (DW16)
61 #define B6_BWSCON (DW32)
62 #define B7_BWSCON (DW32)
65 #define B0_Tacs 0x0 /* 0clk */
66 #define B0_Tcos 0x0 /* 0clk */
67 #define B0_Tacc 0x7 /* 14clk */
68 #define B0_Tcoh 0x0 /* 0clk */
69 #define B0_Tah 0x0 /* 0clk */
71 #define B0_PMC 0x0 /* normal */
74 #define B1_Tacs 0x0 /* 0clk */
75 #define B1_Tcos 0x0 /* 0clk */
76 #define B1_Tacc 0x7 /* 14clk */
77 #define B1_Tcoh 0x0 /* 0clk */
78 #define B1_Tah 0x0 /* 0clk */
90 #define B3_Tacs 0x0 /* 0clk */
91 #define B3_Tcos 0x3 /* 4clk */
92 #define B3_Tacc 0x7 /* 14clk */
93 #define B3_Tcoh 0x1 /* 1clk */
94 #define B3_Tah 0x3 /* 4clk */
95 #define B3_Tacp 0x0 /* 2clk */
96 #define B3_PMC 0x0 /* normal */
106 #define B5_Tacs 0x0 /* 0clk */
107 #define B5_Tcos 0x0 /* 0clk */
108 #define B5_Tacc 0x7 /* 14clk */
109 #define B5_Tcoh 0x0 /* 0clk */
110 #define B5_Tah 0x0 /* 0clk */
112 #define B5_PMC 0x0 /* normal */
114 #define SDRAM_MT 0x3 /* SDRAM */
115 #define SDRAM_Trcd 0x0 /* 2clk */
116 #define SDRAM_SCAN_9 0x1 /* 9bit */
117 #define SDRAM_SCAN_10 0x2 /* 10bit */
119 #define SDRAM_128MB ((SDRAM_MT<<15)+(SDRAM_Trcd<<2)+(SDRAM_SCAN_10))
120 #define SDRAM_64MB ((SDRAM_MT<<15)+(SDRAM_Trcd<<2)+(SDRAM_SCAN_9))
122 /* REFRESH parameter */
123 #define REFEN 0x1 /* Refresh enable */
124 #define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
125 #define Trp 0x1 /* 3clk */
126 #define Trc 0x3 /* 7clk */
127 #define Tchr 0x0 /* unused */
129 #define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048+1-10.37*100) */
131 /**************************************/
138 // disable all interupts
147 /* memory control configuration */
148 /* make r0 relative the current location so that it */
149 /* reads SMRDATA out of FLASH rather than memory ! */
153 ldr r1, =BWSCON /* Bus Width Status Controller */
162 SDRAM comfigured for 128MB, lets try if it works, otherwise,
163 restart it with the smaller scan lines for 64MB
165 ldr r1, =0x34000000 /* just outside 64MB RAM space */
172 ldr r1, =BWSCON+(7*4)
177 /* everything is fine now */
181 /* the literal pools origin */
184 .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
185 .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
186 .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
187 .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
188 .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
189 .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
190 .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
193 .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
194 .word 0xb2 /* enable burst */