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glamo-mmc: Enable reading from cards above 4 GiB
[u-boot-openmoko/mini2440.git] / board / neo1973 / gta02 / glamo-mmc.c
blobd27b1e1c7541669e6339c9307fef92492e45cbd2
1 /*
2 * linux/drivers/mmc/host/glamo-mmc.c - Glamo MMC driver
3 *
4 * Copyright (C) 2007 OpenMoko, Inc, Andy Green <andy@openmoko.com>
5 * Based on the Glamo MCI driver that was -->
6 *
7 * Copyright (C) 2007 OpenMoko, Inc, Andy Green <andy@openmoko.com>
8 * Based on S3C MMC driver that was:
9 * Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
10 *
11 * and
12 *
13 * Based on S3C MMC driver that was (original copyright notice ---->)
14 *
15 * (C) Copyright 2006 by OpenMoko, Inc.
16 * Author: Harald Welte <laforge@openmoko.org>
17 *
18 * based on u-boot pxa MMC driver and linux/drivers/mmc/s3c2410mci.c
19 * (C) 2005-2005 Thomas Kleffel
20 *
21 * Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
22 *
23 * This program is free software; you can redistribute it and/or modify
24 * it under the terms of the GNU General Public License version 2 as
25 * published by the Free Software Foundation.
26 */
27
28 #include <config.h>
29 #include <common.h>
30 #include <mmc.h>
31 #include <asm/errno.h>
32 #include <asm/io.h>
33 #include <part.h>
34 #include <fat.h>
35 #include <pcf50633.h>
36
37 #include "glamo-regs.h"
38 #include "glamo-mmc.h"
39
40 #if defined(CONFIG_MMC) && defined(CONFIG_MMC_GLAMO)
41
42 #define MMC_BLOCK_SIZE_BITS 9
43 #define MMC_BLOCK_SIZE (1 << MMC_BLOCK_SIZE_BITS)
44
45 #define GLAMO_REG(x) (*(volatile u16 *)(CONFIG_GLAMO_BASE + x))
46 #define GLAMO_INTRAM_OFFSET (8 * 1024 * 1024)
47 #define GLAMO_FB_SIZE ((8 * 1024 * 1024) - 0x10000)
48 #define GLAMO_START_OF_MMC_INTMEM ((volatile u16 *)(CONFIG_GLAMO_BASE + \
49 GLAMO_INTRAM_OFFSET + GLAMO_FB_SIZE))
50
51 static int ccnt;
52 static block_dev_desc_t mmc_dev;
53 static mmc_csd_t mmc_csd;
54 static int mmc_ready = 0;
55 static int wide = 0;
56 static enum card_type card_type = CARDTYPE_NONE;
57
58 block_dev_desc_t * mmc_get_dev(int dev)
59 {
60 return (block_dev_desc_t *)&mmc_dev;
61 }
62
63 static void
64 glamo_reg_write(u_int16_t val, u_int16_t reg)
65 {
66 GLAMO_REG(reg) = val;
67 }
68
69 static u_int16_t
70 glamo_reg_read(u_int16_t reg)
71 {
72 return GLAMO_REG(reg);
73 }
74
75 unsigned char CRC7(u8 * pu8, int cnt)
76 {
77 u8 crc = 0;
78
79 while (cnt--) {
80 int n;
81 u8 d = *pu8++;
82 for (n = 0; n < 8; n++) {
83 crc <<= 1;
84 if ((d & 0x80) ^ (crc & 0x80))
85 crc ^= 0x09;
86 d <<= 1;
87 }
88 }
89 return (crc << 1) | 1;
90 }
91
92 /* MMC_DEFAULT_RCA should probably be just 1, but this may break other code
93 that expects it to be shifted. */
94 static u_int16_t rca = MMC_DEFAULT_RCA >> 16;
95
96 static void do_pio_read(u16 *buf, int count_words)
97 {
98 volatile u16 *from_ptr = GLAMO_START_OF_MMC_INTMEM;
99
100 while (count_words--)
101 *buf++ = *from_ptr++;
102 }
103
104 static void do_pio_write(u16 *buf, int count_words)
105 {
106 volatile u16 *to_ptr = GLAMO_START_OF_MMC_INTMEM;
107
108 while (count_words--)
109 *to_ptr++ = *buf++;
110 }
111
112
113 static int mmc_cmd(int opcode, int arg, int flags,
114 int data_size, int data_blocks,
115 int will_stop, u16 *resp)
116 {
117 u16 * pu16 = (u16 *)&resp[0];
118 u16 * reg_resp = (u16 *)(CONFIG_GLAMO_BASE + GLAMO_REGOFS_MMC +
119 GLAMO_REG_MMC_CMD_RSP1);
120 u16 status;
121 int n;
122 u8 u8a[6];
123 u16 fire = 0;
124 int cmd_is_stop = 0;
125 int error = 0;
126
127 #if 0
128 printf("mmc_cmd(opcode=%d, arg=0x%08X, flags=0x%x, "
129 "data_size=%d, data_blocks=%d, will_stop=%d, resp=%p)\n",
130 opcode, arg, flags, data_size, data_blocks, will_stop, resp);
131 #endif
132 switch (opcode) {
133 case MMC_STOP_TRANSMISSION:
134 cmd_is_stop = 1;
135 break;
136 default:
137 break;
138 }
139
140 ccnt++;
141
142 /* this guy has data to read/write? */
143 if ((!cmd_is_stop) && (flags & (MMC_DATA_WRITE | MMC_DATA_READ))) {
144 /*
145 * the S-Media-internal RAM offset for our MMC buffer
146 */
147 glamo_reg_write((u16)GLAMO_FB_SIZE,
148 GLAMO_REGOFS_MMC + GLAMO_REG_MMC_WDATADS1);
149 glamo_reg_write((u16)(GLAMO_FB_SIZE >> 16),
150 GLAMO_REGOFS_MMC + GLAMO_REG_MMC_WDATADS2);
151 glamo_reg_write((u16)GLAMO_FB_SIZE,
152 GLAMO_REGOFS_MMC + GLAMO_REG_MMC_RDATADS1);
153 glamo_reg_write((u16)(GLAMO_FB_SIZE >> 16),
154 GLAMO_REGOFS_MMC + GLAMO_REG_MMC_RDATADS2);
155
156 /* set up the block info */
157 glamo_reg_write(data_size, GLAMO_REGOFS_MMC +
158 GLAMO_REG_MMC_DATBLKLEN);
159 glamo_reg_write(data_blocks, GLAMO_REGOFS_MMC +
160 GLAMO_REG_MMC_DATBLKCNT);
161 }
162
163 /* if we can't do it, reject as busy */
164 if (!glamo_reg_read(GLAMO_REGOFS_MMC + GLAMO_REG_MMC_RB_STAT1) &
165 GLAMO_STAT1_MMC_IDLE)
166 return -1;
167
168 /* create an array in wire order for CRC computation */
169 u8a[0] = 0x40 | (opcode & 0x3f);
170 u8a[1] = (arg >> 24);
171 u8a[2] = (arg >> 16);
172 u8a[3] = (arg >> 8);
173 u8a[4] = arg;
174 u8a[5] = CRC7(&u8a[0], 5); /* CRC7 on first 5 bytes of packet */
175
176 /* issue the wire-order array including CRC in register order */
177 glamo_reg_write((u8a[4] << 8) | u8a[5],
178 GLAMO_REGOFS_MMC + GLAMO_REG_MMC_CMD_REG1);
179 glamo_reg_write((u8a[2] << 8) | u8a[3],
180 GLAMO_REGOFS_MMC + GLAMO_REG_MMC_CMD_REG2);
181 glamo_reg_write((u8a[0] << 8) | u8a[1],
182 GLAMO_REGOFS_MMC + GLAMO_REG_MMC_CMD_REG3);
183
184 /* command index toggle */
185 fire |= (ccnt & 1) << 12;
186
187 /* set type of command */
188 switch (mmc_cmd_type(flags)) {
189 case MMC_CMD_BC:
190 fire |= GLAMO_FIRE_MMC_CMDT_BNR;
191 break;
192 case MMC_CMD_BCR:
193 fire |= GLAMO_FIRE_MMC_CMDT_BR;
194 break;
195 case MMC_CMD_AC:
196 fire |= GLAMO_FIRE_MMC_CMDT_AND;
197 break;
198 case MMC_CMD_ADTC:
199 fire |= GLAMO_FIRE_MMC_CMDT_AD;
200 break;
201 }
202 /*
203 * if it expects a response, set the type expected
204 *
205 * R1, Length : 48bit, Normal response
206 * R1b, Length : 48bit, same R1, but added card busy status
207 * R2, Length : 136bit (really 128 bits with CRC snipped)
208 * R3, Length : 48bit (OCR register value)
209 * R4, Length : 48bit, SDIO_OP_CONDITION, Reverse SDIO Card
210 * R5, Length : 48bit, IO_RW_DIRECTION, Reverse SDIO Card
211 * R6, Length : 48bit (RCA register)
212 * R7, Length : 48bit (interface condition, VHS(voltage supplied),
213 * check pattern, CRC7)
214 */
215 switch (mmc_resp_type(flags)) {
216 case MMC_RSP_R6: /* same index as R7 and R1 */
217 fire |= GLAMO_FIRE_MMC_RSPT_R1;
218 break;
219 case MMC_RSP_R1B:
220 fire |= GLAMO_FIRE_MMC_RSPT_R1b;
221 break;
222 case MMC_RSP_R2:
223 fire |= GLAMO_FIRE_MMC_RSPT_R2;
224 break;
225 case MMC_RSP_R3:
226 fire |= GLAMO_FIRE_MMC_RSPT_R3;
227 break;
228 /* R4 and R5 supported by chip not defined in linux/mmc/core.h (sdio) */
229 }
230 /*
231 * From the command index, set up the command class in the host ctrllr
232 *
233 * missing guys present on chip but couldn't figure out how to use yet:
234 * 0x0 "stream read"
235 * 0x9 "cancel running command"
236 */
237 switch (opcode) {
238 case MMC_READ_SINGLE_BLOCK:
239 fire |= GLAMO_FIRE_MMC_CC_SBR; /* single block read */
240 break;
241 case MMC_SWITCH: /* 64 byte payload */
242 case 0x33: /* observed issued by MCI */
243 case MMC_READ_MULTIPLE_BLOCK:
244 /* we will get an interrupt off this */
245 if (!will_stop)
246 /* multiblock no stop */
247 fire |= GLAMO_FIRE_MMC_CC_MBRNS;
248 else
249 /* multiblock with stop */
250 fire |= GLAMO_FIRE_MMC_CC_MBRS;
251 break;
252 case MMC_WRITE_BLOCK:
253 fire |= GLAMO_FIRE_MMC_CC_SBW; /* single block write */
254 break;
255 case MMC_WRITE_MULTIPLE_BLOCK:
256 if (will_stop)
257 /* multiblock with stop */
258 fire |= GLAMO_FIRE_MMC_CC_MBWS;
259 else
260 /* multiblock NO stop-- 'RESERVED'? */
261 fire |= GLAMO_FIRE_MMC_CC_MBWNS;
262 break;
263 case MMC_STOP_TRANSMISSION:
264 fire |= GLAMO_FIRE_MMC_CC_STOP; /* STOP */
265 break;
266 default:
267 fire |= GLAMO_FIRE_MMC_CC_BASIC; /* "basic command" */
268 break;
269 }
270 /* enforce timeout */
271 glamo_reg_write(0xfff, GLAMO_REGOFS_MMC + GLAMO_REG_MMC_TIMEOUT);
272
273 /* Generate interrupt on txfer; drive strength max */
274 glamo_reg_write((glamo_reg_read(GLAMO_REGOFS_MMC +
275 GLAMO_REG_MMC_BASIC) & 0xfe) |
276 0x0800 | GLAMO_BASIC_MMC_NO_CLK_RD_WAIT |
277 GLAMO_BASIC_MMC_EN_COMPL_INT |
278 GLAMO_BASIC_MMC_EN_DR_STR0 |
279 GLAMO_BASIC_MMC_EN_DR_STR1,
280 GLAMO_REGOFS_MMC + GLAMO_REG_MMC_BASIC);
281
282 /* send the command out on the wire */
283 /* dev_info(&host->pdev->dev, "Using FIRE %04X\n", fire); */
284 glamo_reg_write(fire, GLAMO_REGOFS_MMC + GLAMO_REG_MMC_CMD_FIRE);
285
286 /*
287 * we must spin until response is ready or timed out
288 * -- we don't get interrupts unless there is a bulk rx
289 */
290 do
291 status = glamo_reg_read(GLAMO_REGOFS_MMC +
292 GLAMO_REG_MMC_RB_STAT1);
293 while ((((status >> 15) & 1) != (ccnt & 1)) ||
294 (!(status & (GLAMO_STAT1_MMC_RB_RRDY |
295 GLAMO_STAT1_MMC_RTOUT |
296 GLAMO_STAT1_MMC_DTOUT |
297 GLAMO_STAT1_MMC_BWERR |
298 GLAMO_STAT1_MMC_BRERR))));
299
300 if (status & (GLAMO_STAT1_MMC_RTOUT | GLAMO_STAT1_MMC_DTOUT))
301 error = -4;
302 if (status & (GLAMO_STAT1_MMC_BWERR | GLAMO_STAT1_MMC_BRERR))
303 error = -5;
304
305 if (cmd_is_stop)
306 return 0;
307
308 if (error) {
309 printf("cmd 0x%x, arg 0x%x flags 0x%x\n", opcode, arg, flags);
310 printf("Error after cmd: 0x%x\n", error);
311 goto done;
312 }
313 /*
314 * mangle the response registers in two different exciting
315 * undocumented ways discovered by trial and error
316 */
317 if (mmc_resp_type(flags) == MMC_RSP_R2)
318 /* grab the response */
319 for (n = 0; n < 8; n++) /* super mangle power 1 */
320 pu16[n ^ 6] = reg_resp[n];
321 else
322 for (n = 0; n < 3; n++) /* super mangle power 2 */
323 pu16[n] = (reg_resp[n] >> 8) |
324 (reg_resp[n + 1] << 8);
325 /*
326 * if we don't have bulk data to take care of, we're done
327 */
328 if (!(flags & (MMC_DATA_READ | MMC_DATA_WRITE)))
329 goto done;
330
331 /* enforce timeout */
332 glamo_reg_write(0xfff, GLAMO_REGOFS_MMC + GLAMO_REG_MMC_TIMEOUT);
333 /*
334 * spin
335 */
336 while (!(glamo_reg_read(GLAMO_REG_IRQ_STATUS) & GLAMO_IRQ_MMC))
337 ;
338 /* ack this interrupt source */
339 glamo_reg_write(GLAMO_IRQ_MMC, GLAMO_REG_IRQ_CLEAR);
340
341 if (status & GLAMO_STAT1_MMC_DTOUT)
342 error = -1;
343 if (status & (GLAMO_STAT1_MMC_BWERR | GLAMO_STAT1_MMC_BRERR))
344 error = -2;
345 if (status & GLAMO_STAT1_MMC_RTOUT)
346 error = -5;
347 if (error) {
348 printf("cmd 0x%x, arg 0x%x flags 0x%x\n", opcode, arg, flags);
349 printf("Error after resp: 0x%x\n", status);
350 goto done;
351 }
352 #if 0
353 if (flags & MMC_DATA_READ) {
354 volatile u8 * pu8 = (volatile u8 *)GLAMO_START_OF_MMC_INTMEM;
355 for (n = 0; n < 512; n += 16) {
356 int n1;
357 for (n1 = 0; n1 < 16; n1++) {
358 printf("%02X ", pu8[n + n1]);
359 }
360 printf("\n");
361 }
362 }
363 #endif
364 return 0;
365
366 done:
367 return error;
368 }
369
370 static void glamo_mci_reset(void)
371 {
372 /* reset MMC controller */
373 glamo_reg_write(GLAMO_CLOCK_MMC_RESET | GLAMO_CLOCK_MMC_DG_TCLK |
374 GLAMO_CLOCK_MMC_EN_TCLK | GLAMO_CLOCK_MMC_DG_M9CLK |
375 GLAMO_CLOCK_MMC_EN_M9CLK,
376 GLAMO_REG_CLOCK_MMC);
377 udelay(100000);
378 /* and disable reset */
379 glamo_reg_write(GLAMO_CLOCK_MMC_DG_TCLK |
380 GLAMO_CLOCK_MMC_EN_TCLK | GLAMO_CLOCK_MMC_DG_M9CLK |
381 GLAMO_CLOCK_MMC_EN_M9CLK,
382 GLAMO_REG_CLOCK_MMC);
383 }
384
385
386 static u_int8_t ldo_voltage(unsigned int millivolts)
387 {
388 if (millivolts < 900)
389 return 0;
390 else if (millivolts > 3600)
391 return 0x1f;
392
393 millivolts -= 900;
394 return millivolts / 100;
395 }
396
397 static
398 int glamo_mmc_read(ulong src, uint blksize, uchar *dst, int size)
399 {
400 int resp;
401 u8 response[16];
402 int size_original = size;
403
404 if ((!size) || (size & (MMC_BLOCK_SIZE - 1))) {
405 printf("Bad size %d\n", size);
406 return 0;
407 }
408
409 if (((int)dst) & 1) {
410 printf("Bad align on dst\n");
411 return 0;
412 }
413
414 resp = mmc_cmd(MMC_SET_BLOCKLEN, MMC_BLOCK_SIZE,
415 MMC_CMD_AC | MMC_RSP_R1, 0, 0, 0,
416 (u16 *)&response[0]);
417
418 while (size) {
419 switch (card_type) {
420 case CARDTYPE_SDHC: /* block addressing */
421 if (blksize != MMC_BLOCK_SIZE) {
422 printf("Bad align on src\n");
423 return 0;
424 }
425 resp = mmc_cmd(MMC_READ_SINGLE_BLOCK,
426 src,
427 MMC_CMD_ADTC | MMC_RSP_R1 |
428 MMC_DATA_READ, MMC_BLOCK_SIZE, 1, 0,
429 (u16 *)&response[0]);
430 src += 1;
431 break;
432 default: /* byte addressing */
433 resp = mmc_cmd(MMC_READ_SINGLE_BLOCK, src * blksize,
434 MMC_CMD_ADTC | MMC_RSP_R1 | MMC_DATA_READ,
435 MMC_BLOCK_SIZE, 1, 0,
436 (u16 *)&response[0]);
437 src += MMC_BLOCK_SIZE / blksize;
438 break;
439 }
440 do_pio_read((u16 *)dst, MMC_BLOCK_SIZE >> 1);
441
442 if (size >= MMC_BLOCK_SIZE)
443 size -= MMC_BLOCK_SIZE;
444 else
445 size = 0;
446 dst += MMC_BLOCK_SIZE;
447 }
448 return size_original;
449 }
450
451 ulong mmc_bread(int dev_num, ulong blknr, ulong blkcnt, void *dst)
452 {
453 ulong size = blkcnt * MMC_BLOCK_SIZE;
454
455 if (!blkcnt)
456 return 0;
457
458 /* printf("mmc_bread(%d, %ld, %ld, %p)\n", dev_num, blknr, blkcnt, dst); */
459 glamo_mmc_read(blknr, MMC_BLOCK_SIZE, dst, size);
460 return blkcnt;
461 }
462
463 int mmc_read(ulong src, uchar *dst, int size)
464 {
465 if (src & (MMC_BLOCK_SIZE - 1))
466 return (glamo_mmc_read (src, 1, dst, size));
467 else
468 return (glamo_mmc_read (src >> MMC_BLOCK_SIZE_BITS,
469 MMC_BLOCK_SIZE, dst, size));
470 }
471
472 int mmc_write(uchar *src, ulong dst, int size)
473 {
474 int resp;
475 u8 response[16];
476 int size_original = size;
477
478 if ((!size) || (size & (MMC_BLOCK_SIZE - 1))) {
479 printf("Bad size %d\n", size);
480 return 0;
481 }
482
483 if (((int)dst) & 1) {
484 printf("Bad align on dst\n");
485 return 0;
486 }
487
488 resp = mmc_cmd(MMC_SET_BLOCKLEN, MMC_BLOCK_SIZE,
489 MMC_CMD_AC | MMC_RSP_R1, 0, 0, 0,
490 (u16 *)&response[0]);
491
492 while (size) {
493 do_pio_write((u16 *)src, MMC_BLOCK_SIZE >> 1);
494 switch (card_type) {
495 case CARDTYPE_SDHC: /* block addressing */
496 resp = mmc_cmd(MMC_WRITE_BLOCK,
497 dst >> MMC_BLOCK_SIZE_BITS,
498 MMC_CMD_ADTC | MMC_RSP_R1 |
499 MMC_DATA_WRITE,
500 MMC_BLOCK_SIZE, 1, 0,
501 (u16 *)&response[0]);
502 break;
503 default: /* byte addressing */
504 resp = mmc_cmd(MMC_WRITE_BLOCK, dst,
505 MMC_CMD_ADTC | MMC_RSP_R1 |
506 MMC_DATA_WRITE,
507 MMC_BLOCK_SIZE, 1, 0,
508 (u16 *)&response[0]);
509 break;
510 }
511 if (size >= MMC_BLOCK_SIZE)
512 size -= MMC_BLOCK_SIZE;
513 else
514 size = 0;
515 dst += MMC_BLOCK_SIZE;
516 src += MMC_BLOCK_SIZE;
517 }
518 return size_original;
519 }
520
521 static void print_mmc_cid(mmc_cid_t *cid)
522 {
523 printf("MMC found. Card desciption is:\n");
524 printf("Manufacturer ID = %02x%02x%02x\n",
525 cid->id[0], cid->id[1], cid->id[2]);
526 printf("HW/FW Revision = %x %x\n",cid->hwrev, cid->fwrev);
527 cid->hwrev = cid->fwrev = 0; /* null terminate string */
528 printf("Product Name = %s\n",cid->name);
529 printf("Serial Number = %02x%02x%02x\n",
530 cid->sn[0], cid->sn[1], cid->sn[2]);
531 printf("Month = %d\n",cid->month);
532 printf("Year = %d\n",1997 + cid->year);
533 }
534
535 static void print_sd_cid(const struct sd_cid *cid)
536 {
537 printf("Card Type: ");
538 switch (card_type) {
539 case CARDTYPE_NONE:
540 printf("(None)\n");
541 break;
542 case CARDTYPE_MMC:
543 printf("MMC\n");
544 break;
545 case CARDTYPE_SD:
546 printf("SD\n");
547 break;
548 case CARDTYPE_SD20:
549 printf("SD 2.0\n");
550 break;
551 case CARDTYPE_SDHC:
552 printf("SD 2.0 SDHC\n");
553 break;
554 }
555 printf("Manufacturer: 0x%02x, OEM \"%c%c\"\n",
556 cid->mid, cid->oid_0, cid->oid_1);
557 printf("Product name: \"%c%c%c%c%c\", revision %d.%d\n",
558 cid->pnm_0, cid->pnm_1, cid->pnm_2, cid->pnm_3, cid->pnm_4,
559 cid->prv >> 4, cid->prv & 15);
560 printf("Serial number: %u\n",
561 cid->psn_0 << 24 | cid->psn_1 << 16 | cid->psn_2 << 8 |
562 cid->psn_3);
563 printf("Manufacturing date: %d/%d\n",
564 cid->mdt_1 & 15,
565 2000+((cid->mdt_0 & 15) << 4)+((cid->mdt_1 & 0xf0) >> 4));
566 /* printf("CRC: 0x%02x, b0 = %d\n",
567 cid->crc >> 1, cid->crc & 1); */
568 }
569
570
571 int mmc_init(int verbose)
572 {
573 int retries = 14, rc = -ENODEV;
574 int resp;
575 u8 response[16];
576 mmc_cid_t *mmc_cid = (mmc_cid_t *)response;
577 struct sd_cid *sd_cid = (struct sd_cid *)response;
578 u32 hcs = 0;
579
580 card_type = CARDTYPE_NONE;
581
582 /* enable engine */
583
584 glamo_reg_write(GLAMO_CLOCK_MMC_EN_M9CLK |
585 GLAMO_CLOCK_MMC_EN_TCLK |
586 GLAMO_CLOCK_MMC_DG_M9CLK |
587 GLAMO_CLOCK_MMC_DG_TCLK, GLAMO_REG_CLOCK_MMC);
588 glamo_reg_write(glamo_reg_read(GLAMO_REG_HOSTBUS(2)) |
589 GLAMO_HOSTBUS2_MMIO_EN_MMC, GLAMO_REG_HOSTBUS(2));
590
591 /* controller reset */
592
593 glamo_mci_reset();
594
595 /* power the sdcard slot */
596
597 pcf50633_reg_write(PCF50633_REG_HCLDOOUT, ldo_voltage(3300));
598 udelay(10000);
599 pcf50633_reg_write(PCF50633_REG_HCLDOOUT + 1,
600 pcf50633_reg_read(PCF50633_REG_HCLDOOUT + 1) | 1); /* on */
601 udelay(10000);
602
603 /* start the clock -- slowly (50MHz / 250 == 195kHz */
604
605 glamo_reg_write((glamo_reg_read(GLAMO_REG_CLOCK_GEN8) & 0xff00) | 250,
606 GLAMO_REG_CLOCK_GEN8);
607
608 /* enable clock to divider input */
609
610 glamo_reg_write(glamo_reg_read(
611 GLAMO_REG_CLOCK_GEN5_1) | GLAMO_CLOCK_GEN51_EN_DIV_TCLK,
612 GLAMO_REG_CLOCK_GEN5_1);
613
614 udelay(100000);
615
616 /* set bus width to 1 */
617
618 glamo_reg_write((glamo_reg_read(GLAMO_REGOFS_MMC +
619 GLAMO_REG_MMC_BASIC) &
620 (~GLAMO_BASIC_MMC_EN_4BIT_DATA)),
621 GLAMO_REGOFS_MMC + GLAMO_REG_MMC_BASIC);
622
623 /* reset */
624
625 resp = mmc_cmd(MMC_GO_IDLE_STATE, 0, MMC_CMD_BCR, 0, 0, 0,
626 (u16 *)&response[0]);
627
628 udelay(100000);
629 udelay(100000);
630 udelay(100000);
631
632 /* SDHC card? */
633
634 resp = mmc_cmd(SD_SEND_IF_COND, 0x000001aa,
635 MMC_CMD_BCR | MMC_RSP_R7, 0, 0, 0,
636 (u16 *)&response[0]);
637 if (!resp && (response[0] == 0xaa)) {
638 card_type = CARDTYPE_SD20; /* 2.0 SD, may not be SDHC */
639 hcs = 0x40000000;
640 }
641
642 /* Well, either way let's say hello in SD card protocol */
643
644 while (retries--) {
645
646 udelay(100000);
647
648 resp = mmc_cmd(MMC_APP_CMD, 0x00000000,
649 MMC_CMD_AC | MMC_RSP_R1, 0, 0, 0,
650 (u16 *)&response[0]);
651 if (resp)
652 continue;
653 resp = mmc_cmd(SD_APP_OP_COND, hcs | 0x00300000,
654 MMC_CMD_BCR | MMC_RSP_R3, 0, 0, 0,
655 (u16 *)&response[0]);
656 if (resp)
657 continue;
658
659 if (response[3] & (1 << 6)) /* asserts block addressing */
660 card_type = CARDTYPE_SDHC;
661
662 if (response[3] & (1 << 7)) { /* not busy */
663 if (card_type == CARDTYPE_NONE)
664 card_type = CARDTYPE_SD;
665 break;
666 }
667 }
668 if (retries < 0)
669 return 1;
670
671 if (card_type == CARDTYPE_NONE) {
672 retries = 10;
673 printf("failed to detect SD Card, trying MMC\n");
674 do {
675 resp = mmc_cmd(MMC_SEND_OP_COND, 0x00ffc000,
676 MMC_CMD_BCR | MMC_RSP_R3, 0, 0, 0,
677 (u16 *)&response[0]);
678 debug("resp %x %x\n", response[0], response[1]);
679 udelay(50);
680 } while (retries-- && !(response[3] & 0x80));
681 if (retries >= 0)
682 card_type = CARDTYPE_MMC;
683 else
684 return 1;
685 }
686
687 /* fill in device description */
688 mmc_dev.if_type = IF_TYPE_MMC;
689 mmc_dev.part_type = PART_TYPE_DOS;
690 mmc_dev.dev = 0;
691 mmc_dev.lun = 0;
692 mmc_dev.type = 0;
693 mmc_dev.removable = 0;
694 mmc_dev.block_read = mmc_bread;
695 mmc_dev.blksz = 512;
696 mmc_dev.lba = 1 << 16; /* 64K x 512 blocks = 32MB default */
697
698 /* try to get card id */
699 resp = mmc_cmd(MMC_ALL_SEND_CID, hcs,
700 MMC_CMD_BCR | MMC_RSP_R2, 0, 0, 0,
701 (u16 *)&response[0]);
702 if (resp)
703 return 1;
704
705 switch (card_type) {
706 case CARDTYPE_MMC:
707 /* TODO configure mmc driver depending on card
708 attributes */
709
710 if (verbose)
711 print_mmc_cid(mmc_cid);
712 sprintf((char *) mmc_dev.vendor,
713 "Man %02x%02x%02x Snr %02x%02x%02x",
714 mmc_cid->id[0], mmc_cid->id[1], mmc_cid->id[2],
715 mmc_cid->sn[0], mmc_cid->sn[1], mmc_cid->sn[2]);
716 sprintf((char *) mmc_dev.product, "%s", mmc_cid->name);
717 sprintf((char *) mmc_dev.revision, "%x %x",
718 mmc_cid->hwrev, mmc_cid->fwrev);
719
720 /* MMC exists, get CSD too */
721 resp = mmc_cmd(MMC_SET_RELATIVE_ADDR, MMC_DEFAULT_RCA,
722 MMC_CMD_AC | MMC_RSP_R1, 0, 0, 0,
723 (u16 *)&response[0]);
724 break;
725
726 case CARDTYPE_SD:
727 case CARDTYPE_SD20:
728 case CARDTYPE_SDHC:
729 if (verbose)
730 print_sd_cid(sd_cid);
731 sprintf((char *) mmc_dev.vendor,
732 "Man %02 OEM %c%c \"%c%c%c%c%c\"",
733 sd_cid->mid, sd_cid->oid_0, sd_cid->oid_1,
734 sd_cid->pnm_0, sd_cid->pnm_1, sd_cid->pnm_2,
735 sd_cid->pnm_3, sd_cid->pnm_4);
736 sprintf((char *) mmc_dev.product, "%d",
737 sd_cid->psn_0 << 24 | sd_cid->psn_1 << 16 |
738 sd_cid->psn_2 << 8 | sd_cid->psn_3);
739 sprintf((char *) mmc_dev.revision, "%d.%d",
740 sd_cid->prv >> 4, sd_cid->prv & 15);
741
742 resp = mmc_cmd(SD_SEND_RELATIVE_ADDR, MMC_DEFAULT_RCA,
743 MMC_CMD_BCR | MMC_RSP_R6, 0, 0, 0,
744 (u16 *)&response[0]);
745 rca = response[2] | (response[3] << 8);
746 break;
747
748 default:
749 return 1;
750 }
751
752 /* grab the CSD */
753
754 resp = mmc_cmd(MMC_SEND_CSD, rca << 16,
755 MMC_CMD_AC | MMC_RSP_R2, 0, 0, 0,
756 (u16 *)&response[0]);
757 if (!resp) {
758 mmc_csd_t *csd = (mmc_csd_t *)response;
759
760 memcpy(&mmc_csd, csd, sizeof(csd));
761 rc = 0;
762 mmc_ready = 1;
763 /* FIXME add verbose printout for csd */
764 /* printf("READ_BL_LEN=%u, C_SIZE_MULT=%u, C_SIZE=%u\n",
765 csd->read_bl_len, csd->c_size_mult1,
766 csd->c_size); */
767 mmc_dev.blksz = 512;
768 mmc_dev.lba = (((unsigned long)1 << csd->c_size_mult1) *
769 (unsigned long)csd->c_size) >> 9;
770 printf("MMC/SD size: %dMiB\n", mmc_dev.lba >> 1);
771 }
772
773 resp = mmc_cmd(MMC_SELECT_CARD, rca<<16, MMC_CMD_AC | MMC_RSP_R1,
774 0, 0, 0, (u16 *)&response[0]);
775 if (resp)
776 return 1;
777
778 #ifdef CONFIG_MMC_WIDE
779 /* yay 4-bit! */
780 if (card_type == CARDTYPE_SD || card_type == CARDTYPE_SDHC) {
781 resp = mmc_cmd(MMC_APP_CMD, rca<<16, MMC_CMD_AC | MMC_RSP_R1,
782 0, 0, 0, (u16 *)&response[0]);
783 resp = mmc_cmd(MMC_SWITCH, 0x02, MMC_CMD_AC | MMC_RSP_R1B,
784 0, 0, 0, (u16 *)&response[0]);
785 wide = 1;
786 glamo_reg_write(glamo_reg_read(GLAMO_REGOFS_MMC +
787 GLAMO_REG_MMC_BASIC) | GLAMO_BASIC_MMC_EN_4BIT_DATA,
788 GLAMO_REGOFS_MMC + GLAMO_REG_MMC_BASIC);
789 }
790 #endif
791
792 /* crank the clock to the final speed, 16MHz */
793
794 glamo_reg_write((glamo_reg_read(GLAMO_REG_CLOCK_GEN8) & 0xff00) | 2,
795 GLAMO_REG_CLOCK_GEN8);
796
797 fat_register_device(&mmc_dev, 1); /* partitions start counting with 1 */
798
799 return rc;
800 }
801
802 void mmc_depower(void)
803 {
804 u8 response[16];
805
806 /* reset */
807 mmc_cmd(MMC_GO_IDLE_STATE, 0, MMC_CMD_BCR, 0, 0, 0,
808 (u16 *)&response[0]);
809
810 /* hold engine reset, remove clocks */
811
812 glamo_reg_write(GLAMO_CLOCK_MMC_RESET, GLAMO_REG_CLOCK_MMC);
813
814 /* disable engine */
815
816 glamo_reg_write(0, GLAMO_REG_CLOCK_MMC);
817 glamo_reg_write(glamo_reg_read(GLAMO_REG_HOSTBUS(2)) &
818 (~GLAMO_HOSTBUS2_MMIO_EN_MMC), GLAMO_REG_HOSTBUS(2));
819
820 /* remove power */
821
822 pcf50633_reg_write(PCF50633_REG_HCLDOOUT + 1,
823 pcf50633_reg_read(PCF50633_REG_HCLDOOUT + 1) & ~1); /* off */
824 }
825
826 int
827 mmc_ident(block_dev_desc_t *dev)
828 {
829 return 0;
830 }
831
832 int
833 mmc2info(ulong addr)
834 {
835 /* FIXME hard codes to 32 MB device */
836 if (addr >= CFG_MMC_BASE && addr < CFG_MMC_BASE + 0x02000000)
837 return 1;
838
839 return 0;
840 }
841
842
843 #endif /* defined(CONFIG_MMC) && defined(CONFIG_MMC_GLAMO) */
Fork of the u-boot for for Samsung based MINI2440 board