Added support for the Hynix HY27US08121A 64MB Flash chip.
[u-boot-openmoko/mini2440.git] / drivers / rtc / ds1374.c
blobf6bb2965a4b1b5ffaaffbfb6fdcae5d5a4410acd
1 /*
2 * (C) Copyright 2001, 2002, 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Keith Outwater, keith_outwater@mvis.com`
5 * Steven Scholz, steven.scholz@imc-berlin.de
7 * See file CREDITS for list of people who contributed to this
8 * project.
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
27 * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
28 * DS1374 Real Time Clock (RTC).
30 * based on ds1337.c
33 #include <common.h>
34 #include <command.h>
35 #include <rtc.h>
36 #include <i2c.h>
38 #if (defined(CONFIG_RTC_DS1374)) && defined(CONFIG_CMD_DATE)
40 /*---------------------------------------------------------------------*/
41 #undef DEBUG_RTC
42 #define DEBUG_RTC
44 #ifdef DEBUG_RTC
45 #define DEBUGR(fmt,args...) printf(fmt ,##args)
46 #else
47 #define DEBUGR(fmt,args...)
48 #endif
49 /*---------------------------------------------------------------------*/
51 #ifndef CFG_I2C_RTC_ADDR
52 # define CFG_I2C_RTC_ADDR 0x68
53 #endif
55 #if defined(CONFIG_RTC_DS1374) && (CFG_I2C_SPEED > 400000)
56 # error The DS1374 is specified up to 400kHz in fast mode!
57 #endif
60 * RTC register addresses
62 #define RTC_TOD_CNT_BYTE0_ADDR 0x00 /* TimeOfDay */
63 #define RTC_TOD_CNT_BYTE1_ADDR 0x01
64 #define RTC_TOD_CNT_BYTE2_ADDR 0x02
65 #define RTC_TOD_CNT_BYTE3_ADDR 0x03
67 #define RTC_WD_ALM_CNT_BYTE0_ADDR 0x04
68 #define RTC_WD_ALM_CNT_BYTE1_ADDR 0x05
69 #define RTC_WD_ALM_CNT_BYTE2_ADDR 0x06
71 #define RTC_CTL_ADDR 0x07 /* RTC-CoNTrol-register */
72 #define RTC_SR_ADDR 0x08 /* RTC-StatusRegister */
73 #define RTC_TCS_DS_ADDR 0x09 /* RTC-TrickleChargeSelect DiodeSelect-register */
75 #define RTC_CTL_BIT_AIE (1<<0) /* Bit 0 - Alarm Interrupt enable */
76 #define RTC_CTL_BIT_RS1 (1<<1) /* Bit 1/2 - Rate Select square wave output */
77 #define RTC_CTL_BIT_RS2 (1<<2) /* Bit 2/2 - Rate Select square wave output */
78 #define RTC_CTL_BIT_WDSTR (1<<3) /* Bit 3 - Watchdog Reset Steering */
79 #define RTC_CTL_BIT_BBSQW (1<<4) /* Bit 4 - Battery-Backed Square-Wave */
80 #define RTC_CTL_BIT_WD_ALM (1<<5) /* Bit 5 - Watchdoc/Alarm Counter Select */
81 #define RTC_CTL_BIT_WACE (1<<6) /* Bit 6 - Watchdog/Alarm Counter Enable WACE*/
82 #define RTC_CTL_BIT_EN_OSC (1<<7) /* Bit 7 - Enable Oscilator */
84 #define RTC_SR_BIT_AF 0x01 /* Bit 0 = Alarm Flag */
85 #define RTC_SR_BIT_OSF 0x80 /* Bit 7 - Osc Stop Flag */
87 typedef unsigned char boolean_t;
89 #ifndef TRUE
90 #define TRUE ((boolean_t)(0==0))
91 #endif
92 #ifndef FALSE
93 #define FALSE (!TRUE)
94 #endif
96 const char RtcTodAddr[] = {
97 RTC_TOD_CNT_BYTE0_ADDR,
98 RTC_TOD_CNT_BYTE1_ADDR,
99 RTC_TOD_CNT_BYTE2_ADDR,
100 RTC_TOD_CNT_BYTE3_ADDR
103 static uchar rtc_read (uchar reg);
104 static void rtc_write (uchar reg, uchar val, boolean_t set);
105 static void rtc_write_raw (uchar reg, uchar val);
108 * Get the current time from the RTC
110 int rtc_get (struct rtc_time *tm){
111 int rel = 0;
112 unsigned long time1, time2;
113 unsigned int limit;
114 unsigned char tmp;
115 unsigned int i;
118 * Since the reads are being performed one byte at a time,
119 * there is a chance that a carry will occur during the read.
120 * To detect this, 2 reads are performed and compared.
122 limit = 10;
123 do {
124 i = 4;
125 time1 = 0;
126 while (i--) {
127 tmp = rtc_read(RtcTodAddr[i]);
128 time1 = (time1 << 8) | (tmp & 0xff);
131 i = 4;
132 time2 = 0;
133 while (i--) {
134 tmp = rtc_read(RtcTodAddr[i]);
135 time2 = (time2 << 8) | (tmp & 0xff);
137 } while ((time1 != time2) && limit--);
139 if (time1 != time2) {
140 printf("can't get consistent time from rtc chip\n");
141 rel = -1;
144 DEBUGR ("Get RTC s since 1.1.1970: %d\n", time1);
146 to_tm(time1, tm); /* To Gregorian Date */
148 if (rtc_read(RTC_SR_ADDR) & RTC_SR_BIT_OSF) {
149 printf ("### Warning: RTC oscillator has stopped\n");
150 rel = -1;
153 DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
154 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
155 tm->tm_hour, tm->tm_min, tm->tm_sec);
157 return rel;
161 * Set the RTC
163 void rtc_set (struct rtc_time *tmp){
165 unsigned long time;
166 unsigned i;
168 DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
169 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
170 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
172 if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
173 printf("WARNING: year should be between 1970 and 2069!\n");
175 time = mktime(tmp->tm_year, tmp->tm_mon,
176 tmp->tm_mday, tmp->tm_hour,
177 tmp->tm_min, tmp->tm_sec);
179 DEBUGR ("Set RTC s since 1.1.1970: %d (0x%02x)\n", time, time);
181 /* write to RTC_TOD_CNT_BYTEn_ADDR */
182 for (i = 0; i <= 3; i++) {
183 rtc_write_raw(RtcTodAddr[i], (unsigned char)(time & 0xff));
184 time = time >> 8;
187 /* Start clock */
188 rtc_write(RTC_CTL_ADDR, RTC_CTL_BIT_EN_OSC, FALSE);
192 * Reset the RTC. We setting the date back to 1970-01-01.
193 * We also enable the oscillator output on the SQW/OUT pin and program
194 * it for 32,768 Hz output. Note that according to the datasheet, turning
195 * on the square wave output increases the current drain on the backup
196 * battery to something between 480nA and 800nA.
198 void rtc_reset (void){
200 struct rtc_time tmp;
202 /* clear status flags */
203 rtc_write (RTC_SR_ADDR, (RTC_SR_BIT_AF|RTC_SR_BIT_OSF), FALSE); /* clearing OSF and AF */
205 /* Initialise DS1374 oriented to MPC8349E-ADS */
206 rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_EN_OSC
207 |RTC_CTL_BIT_WACE
208 |RTC_CTL_BIT_AIE), FALSE);/* start osc, disable WACE, clear AIE
209 - set to 0 */
210 rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_WD_ALM
211 |RTC_CTL_BIT_WDSTR
212 |RTC_CTL_BIT_RS1
213 |RTC_CTL_BIT_RS2
214 |RTC_CTL_BIT_BBSQW), TRUE);/* disable WD/ALM, WDSTR set to INT-pin,
215 set BBSQW and SQW to 32k
216 - set to 1 */
217 tmp.tm_year = 1970;
218 tmp.tm_mon = 1;
219 tmp.tm_mday= 1;
220 tmp.tm_hour = 0;
221 tmp.tm_min = 0;
222 tmp.tm_sec = 0;
224 rtc_set(&tmp);
226 printf("RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n",
227 tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
228 tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
230 rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR,0xAC, TRUE);
231 rtc_write(RTC_WD_ALM_CNT_BYTE1_ADDR,0xDE, TRUE);
232 rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR,0xAD, TRUE);
236 * Helper functions
238 static uchar rtc_read (uchar reg)
240 return (i2c_reg_read (CFG_I2C_RTC_ADDR, reg));
243 static void rtc_write (uchar reg, uchar val, boolean_t set)
245 if (set == TRUE) {
246 val |= i2c_reg_read (CFG_I2C_RTC_ADDR, reg);
247 i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val);
248 } else {
249 val = i2c_reg_read (CFG_I2C_RTC_ADDR, reg) & ~val;
250 i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val);
254 static void rtc_write_raw (uchar reg, uchar val)
256 i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val);
258 #endif