drivers/net/pcnet.c

   1 /*
   2  * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
   3  *
   4  * This driver for AMD PCnet network controllers is derived from the
   5  * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <malloc.h>
  28 #include <net.h>
  29 #include <asm/io.h>
  30 #include <pci.h>
  31
  32 #if 0
  33 #define PCNET_DEBUG_LEVEL       0 /* 0=off, 1=init, 2=rx/tx */
  34 #endif
  35
  36 #if PCNET_DEBUG_LEVEL > 0
  37 #define PCNET_DEBUG1(fmt,args...)       printf (fmt ,##args)
  38 #if PCNET_DEBUG_LEVEL > 1
  39 #define PCNET_DEBUG2(fmt,args...)       printf (fmt ,##args)
  40 #else
  41 #define PCNET_DEBUG2(fmt,args...)
  42 #endif
  43 #else
  44 #define PCNET_DEBUG1(fmt,args...)
  45 #define PCNET_DEBUG2(fmt,args...)
  46 #endif
  47
  48 #if defined(CONFIG_CMD_NET) \
  49         && defined(CONFIG_NET_MULTI) && defined(CONFIG_PCNET)
  50
  51 #if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975)
  52 #error "Macro for PCnet chip version is not defined!"
  53 #endif
  54
  55 /*
  56  * Set the number of Tx and Rx buffers, using Log_2(# buffers).
  57  * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
  58  * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
  59  */
  60 #define PCNET_LOG_TX_BUFFERS    0
  61 #define PCNET_LOG_RX_BUFFERS    2
  62
  63 #define TX_RING_SIZE            (1 << (PCNET_LOG_TX_BUFFERS))
  64 #define TX_RING_LEN_BITS        ((PCNET_LOG_TX_BUFFERS) << 12)
  65
  66 #define RX_RING_SIZE            (1 << (PCNET_LOG_RX_BUFFERS))
  67 #define RX_RING_LEN_BITS        ((PCNET_LOG_RX_BUFFERS) << 4)
  68
  69 #define PKT_BUF_SZ              1544
  70
  71 /* The PCNET Rx and Tx ring descriptors. */
  72 struct pcnet_rx_head {
  73     u32 base;
  74     s16 buf_length;
  75     s16 status;
  76     u32 msg_length;
  77     u32 reserved;
  78 };
  79
  80 struct pcnet_tx_head {
  81     u32 base;
  82     s16 length;
  83     s16 status;
  84     u32 misc;
  85     u32 reserved;
  86 };
  87
  88 /* The PCNET 32-Bit initialization block, described in databook. */
  89 struct pcnet_init_block {
  90     u16 mode;
  91     u16 tlen_rlen;
  92     u8  phys_addr[6];
  93     u16 reserved;
  94     u32 filter[2];
  95     /* Receive and transmit ring base, along with extra bits. */
  96     u32 rx_ring;
  97     u32 tx_ring;
  98     u32 reserved2;
  99 };
 100
 101 typedef struct pcnet_priv {
 102     struct pcnet_rx_head    rx_ring[RX_RING_SIZE];
 103     struct pcnet_tx_head    tx_ring[TX_RING_SIZE];
 104     struct pcnet_init_block init_block;
 105     /* Receive Buffer space */
 106     unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
 107     int cur_rx;
 108     int cur_tx;
 109 } pcnet_priv_t;
 110
 111 static pcnet_priv_t *lp;
 112
 113 /* Offsets from base I/O address for WIO mode */
 114 #define PCNET_RDP               0x10
 115 #define PCNET_RAP               0x12
 116 #define PCNET_RESET             0x14
 117 #define PCNET_BDP               0x16
 118
 119 static u16 pcnet_read_csr (struct eth_device *dev, int index)
 120 {
 121     outw (index, dev->iobase+PCNET_RAP);
 122     return inw (dev->iobase+PCNET_RDP);
 123 }
 124
 125 static void pcnet_write_csr (struct eth_device *dev, int index, u16 val)
 126 {
 127     outw (index, dev->iobase+PCNET_RAP);
 128     outw (val, dev->iobase+PCNET_RDP);
 129 }
 130
 131 static u16 pcnet_read_bcr (struct eth_device *dev, int index)
 132 {
 133     outw (index, dev->iobase+PCNET_RAP);
 134     return inw (dev->iobase+PCNET_BDP);
 135 }
 136
 137 static void pcnet_write_bcr (struct eth_device *dev, int index, u16 val)
 138 {
 139     outw (index, dev->iobase+PCNET_RAP);
 140     outw (val, dev->iobase+PCNET_BDP);
 141 }
 142
 143 static void pcnet_reset (struct eth_device *dev)
 144 {
 145     inw (dev->iobase+PCNET_RESET);
 146 }
 147
 148 static int pcnet_check (struct eth_device *dev)
 149 {
 150     outw (88, dev->iobase+PCNET_RAP);
 151     return (inw (dev->iobase+PCNET_RAP) == 88);
 152 }
 153
 154 static int  pcnet_init( struct eth_device* dev, bd_t *bis);
 155 static int  pcnet_send (struct eth_device* dev, volatile void *packet,
 156                         int length);
 157 static int  pcnet_recv (struct eth_device* dev);
 158 static void pcnet_halt (struct eth_device* dev);
 159 static int  pcnet_probe(struct eth_device* dev, bd_t *bis, int dev_num);
 160
 161 #define PCI_TO_MEM(d,a) pci_phys_to_mem((pci_dev_t)d->priv, (u_long)(a))
 162 #define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a)))
 163
 164 static struct pci_device_id supported[] = {
 165         { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE },
 166         { }
 167 };
 168
 169
 170 int pcnet_initialize(bd_t *bis)
 171 {
 172     pci_dev_t devbusfn;
 173     struct eth_device* dev;
 174     u16 command, status;
 175     int dev_nr = 0;
 176
 177     PCNET_DEBUG1("\npcnet_initialize...\n");
 178
 179     for (dev_nr = 0; ; dev_nr++) {
 180
 181         /*
 182          * Find the PCnet PCI device(s).
 183          */
 184         if ((devbusfn = pci_find_devices(supported, dev_nr)) < 0) {
 185             break;
 186         }
 187
 188         /*
 189          * Allocate and pre-fill the device structure.
 190          */
 191         dev = (struct eth_device*) malloc(sizeof *dev);
 192         dev->priv = (void *)devbusfn;
 193         sprintf(dev->name, "pcnet#%d", dev_nr);
 194
 195         /*
 196          * Setup the PCI device.
 197          */
 198         pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (unsigned int *)&dev->iobase);
 199         dev->iobase &= ~0xf;
 200
 201         PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ",
 202                dev->name, devbusfn, dev->iobase);
 203
 204         command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
 205         pci_write_config_word(devbusfn, PCI_COMMAND, command);
 206         pci_read_config_word(devbusfn, PCI_COMMAND, &status);
 207         if ((status & command) != command) {
 208             printf("%s: Couldn't enable IO access or Bus Mastering\n",
 209                    dev->name);
 210             free(dev);
 211             continue;
 212         }
 213
 214         pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
 215
 216         /*
 217          * Probe the PCnet chip.
 218          */
 219         if (pcnet_probe(dev, bis, dev_nr) < 0) {
 220             free(dev);
 221             continue;
 222         }
 223
 224         /*
 225          * Setup device structure and register the driver.
 226          */
 227         dev->init   = pcnet_init;
 228         dev->halt   = pcnet_halt;
 229         dev->send   = pcnet_send;
 230         dev->recv   = pcnet_recv;
 231
 232         eth_register(dev);
 233     }
 234
 235     udelay(10 * 1000);
 236
 237     return dev_nr;
 238 }
 239
 240 static int pcnet_probe(struct eth_device* dev, bd_t *bis, int dev_nr)
 241 {
 242     int chip_version;
 243     char *chipname;
 244 #ifdef PCNET_HAS_PROM
 245     int i;
 246 #endif
 247
 248     /* Reset the PCnet controller */
 249     pcnet_reset(dev);
 250
 251     /* Check if register access is working */
 252     if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) {
 253         printf("%s: CSR register access check failed\n", dev->name);
 254         return -1;
 255     }
 256
 257     /* Identify the chip */
 258     chip_version = pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev,89) << 16);
 259     if ((chip_version & 0xfff) != 0x003)
 260        return -1;
 261     chip_version = (chip_version >> 12) & 0xffff;
 262     switch (chip_version) {
 263 #ifdef CONFIG_PCNET_79C973
 264     case 0x2625:
 265         chipname = "PCnet/FAST III 79C973"; /* PCI */
 266         break;
 267 #endif
 268 #ifdef CONFIG_PCNET_79C975
 269     case 0x2627:
 270         chipname = "PCnet/FAST III 79C975"; /* PCI */
 271         break;
 272 #endif
 273     default:
 274         printf("%s: PCnet version %#x not supported\n",
 275                dev->name, chip_version);
 276         return -1;
 277     }
 278
 279     PCNET_DEBUG1("AMD %s\n", chipname);
 280
 281 #ifdef PCNET_HAS_PROM
 282     /*
 283      * In most chips, after a chip reset, the ethernet address is read from
 284      * the station address PROM at the base address and programmed into the
 285      * "Physical Address Registers" CSR12-14.
 286      */
 287     for (i = 0; i < 3; i++) {
 288         unsigned int val;
 289         val = pcnet_read_csr(dev, i+12) & 0x0ffff;
 290         /* There may be endianness issues here. */
 291         dev->enetaddr[2*i  ] =  val       & 0x0ff;
 292         dev->enetaddr[2*i+1] = (val >> 8) & 0x0ff;
 293     }
 294 #endif /* PCNET_HAS_PROM */
 295
 296     return 0;
 297 }
 298
 299 static int pcnet_init(struct eth_device* dev, bd_t *bis)
 300 {
 301     int i, val;
 302     u32 addr;
 303
 304     PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
 305
 306     /* Switch pcnet to 32bit mode */
 307     pcnet_write_bcr (dev, 20, 2);
 308
 309 #ifdef CONFIG_PN62
 310     /* Setup LED registers */
 311     val = pcnet_read_bcr (dev, 2) | 0x1000;
 312     pcnet_write_bcr (dev, 2, val);    /* enable LEDPE */
 313     pcnet_write_bcr (dev, 4, 0x5080); /* 100MBit */
 314     pcnet_write_bcr (dev, 5, 0x40c0); /* LNKSE */
 315     pcnet_write_bcr (dev, 6, 0x4090); /* TX Activity */
 316     pcnet_write_bcr (dev, 7, 0x4084); /* RX Activity */
 317 #endif
 318
 319     /* Set/reset autoselect bit */
 320     val = pcnet_read_bcr (dev, 2) & ~2;
 321     val |= 2;
 322     pcnet_write_bcr (dev, 2, val);
 323
 324     /* Enable auto negotiate, setup, disable fd */
 325     val = pcnet_read_bcr(dev, 32) & ~0x98;
 326     val |= 0x20;
 327     pcnet_write_bcr(dev, 32, val);
 328
 329     /*
 330      * We only maintain one structure because the drivers will never
 331      * be used concurrently. In 32bit mode the RX and TX ring entries
 332      * must be aligned on 16-byte boundaries.
 333      */
 334     if (lp == NULL) {
 335         addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10);
 336         addr = (addr + 0xf) & ~0xf;
 337         lp = (pcnet_priv_t *)addr;
 338     }
 339
 340     lp->init_block.mode = cpu_to_le16(0x0000);
 341     lp->init_block.filter[0] = 0x00000000;
 342     lp->init_block.filter[1] = 0x00000000;
 343
 344     /*
 345      * Initialize the Rx ring.
 346      */
 347     lp->cur_rx = 0;
 348     for (i = 0; i < RX_RING_SIZE; i++) {
 349         lp->rx_ring[i].base = PCI_TO_MEM_LE(dev, lp->rx_buf[i]);
 350         lp->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
 351         lp->rx_ring[i].status = cpu_to_le16(0x8000);
 352         PCNET_DEBUG1("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n",
 353                i, lp->rx_ring[i].base, lp->rx_ring[i].buf_length,
 354                lp->rx_ring[i].status);
 355     }
 356
 357     /*
 358      * Initialize the Tx ring. The Tx buffer address is filled in as
 359      * needed, but we do need to clear the upper ownership bit.
 360      */
 361     lp->cur_tx = 0;
 362     for (i = 0; i < TX_RING_SIZE; i++) {
 363         lp->tx_ring[i].base = 0;
 364         lp->tx_ring[i].status = 0;
 365     }
 366
 367     /*
 368      * Setup Init Block.
 369      */
 370     PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->init_block);
 371
 372     for (i = 0; i < 6; i++) {
 373         lp->init_block.phys_addr[i] = dev->enetaddr[i];
 374         PCNET_DEBUG1(" %02x", lp->init_block.phys_addr[i]);
 375     }
 376
 377     lp->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
 378                                            RX_RING_LEN_BITS);
 379     lp->init_block.rx_ring = PCI_TO_MEM_LE(dev, lp->rx_ring);
 380     lp->init_block.tx_ring = PCI_TO_MEM_LE(dev, lp->tx_ring);
 381
 382     PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
 383            lp->init_block.tlen_rlen,
 384            lp->init_block.rx_ring, lp->init_block.tx_ring);
 385
 386     /*
 387      * Tell the controller where the Init Block is located.
 388      */
 389     addr = PCI_TO_MEM(dev, &lp->init_block);
 390     pcnet_write_csr(dev, 1, addr & 0xffff);
 391     pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
 392
 393     pcnet_write_csr (dev, 4, 0x0915);
 394     pcnet_write_csr (dev, 0, 0x0001); /* start */
 395
 396     /* Wait for Init Done bit */
 397     for (i = 10000; i > 0; i--) {
 398         if (pcnet_read_csr (dev, 0) & 0x0100)
 399             break;
 400         udelay(10);
 401     }
 402     if (i <= 0) {
 403         printf("%s: TIMEOUT: controller init failed\n", dev->name);
 404         pcnet_reset (dev);
 405         return -1;
 406     }
 407
 408     /*
 409      * Finally start network controller operation.
 410      */
 411     pcnet_write_csr (dev, 0, 0x0002);
 412
 413     return 0;
 414 }
 415
 416 static int pcnet_send(struct eth_device* dev, volatile void *packet, int pkt_len)
 417 {
 418     int i, status;
 419     struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx];
 420
 421     PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, packet);
 422
 423     /* Wait for completion by testing the OWN bit */
 424     for (i = 1000; i > 0; i--) {
 425         status = le16_to_cpu(entry->status);
 426         if ((status & 0x8000) == 0)
 427             break;
 428         udelay(100);
 429         PCNET_DEBUG2(".");
 430     }
 431     if (i <= 0) {
 432         printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
 433                dev->name, lp->cur_tx, status);
 434         pkt_len = 0;
 435         goto failure;
 436     }
 437
 438     /*
 439      * Setup Tx ring. Caution: the write order is important here,
 440      * set the status with the "ownership" bits last.
 441      */
 442     status = 0x8300;
 443     entry->length = le16_to_cpu(-pkt_len);
 444     entry->misc   = 0x00000000;
 445     entry->base   = PCI_TO_MEM_LE(dev, packet);
 446     entry->status = le16_to_cpu(status);
 447
 448     /* Trigger an immediate send poll. */
 449     pcnet_write_csr (dev, 0, 0x0008);
 450
 451  failure:
 452     if (++lp->cur_tx >= TX_RING_SIZE)
 453         lp->cur_tx = 0;
 454
 455     PCNET_DEBUG2("done\n");
 456     return pkt_len;
 457 }
 458
 459 static int pcnet_recv(struct eth_device* dev)
 460 {
 461     struct pcnet_rx_head *entry;
 462     int pkt_len = 0;
 463     u16 status;
 464
 465     while (1) {
 466         entry = &lp->rx_ring[lp->cur_rx];
 467         /*
 468          * If we own the next entry, it's a new packet. Send it up.
 469          */
 470         if (((status = le16_to_cpu(entry->status)) & 0x8000) != 0) {
 471             break;
 472         }
 473         status >>= 8;
 474
 475         if (status != 0x03) {   /* There was an error. */
 476
 477             printf("%s: Rx%d", dev->name, lp->cur_rx);
 478             PCNET_DEBUG1(" (status=0x%x)", status);
 479             if (status & 0x20) printf(" Frame");
 480             if (status & 0x10) printf(" Overflow");
 481             if (status & 0x08) printf(" CRC");
 482             if (status & 0x04) printf(" Fifo");
 483             printf(" Error\n");
 484             entry->status &= le16_to_cpu(0x03ff);
 485
 486         } else {
 487
 488             pkt_len = (le32_to_cpu(entry->msg_length) & 0xfff) - 4;
 489             if (pkt_len < 60) {
 490                 printf("%s: Rx%d: invalid packet length %d\n",
 491                        dev->name, lp->cur_rx, pkt_len);
 492             } else {
 493                 NetReceive(lp->rx_buf[lp->cur_rx], pkt_len);
 494                 PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
 495                        lp->cur_rx, pkt_len, lp->rx_buf[lp->cur_rx]);
 496             }
 497         }
 498         entry->status |= cpu_to_le16(0x8000);
 499
 500         if (++lp->cur_rx >= RX_RING_SIZE)
 501             lp->cur_rx = 0;
 502     }
 503     return pkt_len;
 504 }
 505
 506 static void pcnet_halt(struct eth_device* dev)
 507 {
 508     int i;
 509
 510     PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name);
 511
 512     /* Reset the PCnet controller */
 513     pcnet_reset (dev);
 514
 515     /* Wait for Stop bit */
 516     for (i = 1000; i > 0; i--) {
 517         if (pcnet_read_csr (dev, 0) & 0x4)
 518             break;
 519         udelay(10);
 520     }
 521     if (i <= 0) {
 522         printf("%s: TIMEOUT: controller reset failed\n", dev->name);
 523     }
 524 }
 525
 526 #endif