drivers/net/lan91c96.h

   1 /*------------------------------------------------------------------------
   2  * lan91c96.h
   3  *
   4  * (C) Copyright 2002
   5  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   6  * Rolf Offermanns <rof@sysgo.de>
   7  * Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
   8  *       Developed by Simple Network Magic Corporation (SNMC)
   9  * Copyright (C) 1996 by Erik Stahlman (ES)
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  24  *
  25  * This file contains register information and access macros for
  26  * the LAN91C96 single chip ethernet controller.  It is a modified
  27  * version of the smc9111.h file.
  28  *
  29  * Information contained in this file was obtained from the LAN91C96
  30  * manual from SMC. To get a copy, if you really want one, you can find
  31  * information under www.smsc.com.
  32  *
  33  * Authors
  34  *      Erik Stahlman                           ( erik@vt.edu )
  35  *      Daris A Nevil                           ( dnevil@snmc.com )
  36  *
  37  * History
  38  * 04/30/03     Mathijs Haarman         Modified smc91111.h (u-boot version)
  39  *                                      for lan91c96
  40  *-------------------------------------------------------------------------
  41  */
  42 #ifndef _LAN91C96_H_
  43 #define _LAN91C96_H_
  44
  45 #include <asm/types.h>
  46 #include <asm/io.h>
  47 #include <config.h>
  48
  49 /*
  50  * This function may be called by the board specific initialisation code
  51  * in order to override the default mac address.
  52  */
  53
  54 void smc_set_mac_addr(const unsigned char *addr);
  55
  56
  57 /* I want some simple types */
  58
  59 typedef unsigned char                   byte;
  60 typedef unsigned short                  word;
  61 typedef unsigned long int               dword;
  62
  63 /*
  64  * DEBUGGING LEVELS
  65  *
  66  * 0 for normal operation
  67  * 1 for slightly more details
  68  * >2 for various levels of increasingly useless information
  69  *    2 for interrupt tracking, status flags
  70  *    3 for packet info
  71  *    4 for complete packet dumps
  72  */
  73 /*#define SMC_DEBUG 0 */
  74
  75 /* Because of bank switching, the LAN91xxx uses only 16 I/O ports */
  76
  77 #define SMC_IO_EXTENT   16
  78
  79 #ifdef CONFIG_PXA250
  80
  81 #ifdef  CONFIG_LUBBOCK
  82 #define SMC_IO_SHIFT    2
  83 #undef  USE_32_BIT
  84
  85 #else
  86 #define SMC_IO_SHIFT    0
  87 #endif
  88
  89 #define SMCREG(r)       (SMC_BASE_ADDRESS+((r)<<SMC_IO_SHIFT))
  90
  91 #define SMC_inl(r)      (*((volatile dword *)SMCREG(r)))
  92 #define SMC_inw(r)      (*((volatile word *)SMCREG(r)))
  93 #define SMC_inb(p) ({ \
  94         unsigned int __p = p; \
  95         unsigned int __v = SMC_inw(__p & ~1); \
  96         if (__p & 1) __v >>= 8; \
  97         else __v &= 0xff; \
  98         __v; })
  99
 100 #define SMC_outl(d,r)   (*((volatile dword *)SMCREG(r)) = d)
 101 #define SMC_outw(d,r)   (*((volatile word *)SMCREG(r)) = d)
 102 #define SMC_outb(d,r)   ({      word __d = (byte)(d);  \
 103                                 word __w = SMC_inw((r)&~1);  \
 104                                 __w &= ((r)&1) ? 0x00FF : 0xFF00;  \
 105                                 __w |= ((r)&1) ? __d<<8 : __d;  \
 106                                 SMC_outw(__w,(r)&~1);  \
 107                         })
 108
 109 #define SMC_outsl(r,b,l)        ({      int __i; \
 110                                         dword *__b2; \
 111                                         __b2 = (dword *) b; \
 112                                         for (__i = 0; __i < l; __i++) { \
 113                                             SMC_outl( *(__b2 + __i), r ); \
 114                                         } \
 115                                 })
 116
 117 #define SMC_outsw(r,b,l)        ({      int __i; \
 118                                         word *__b2; \
 119                                         __b2 = (word *) b; \
 120                                         for (__i = 0; __i < l; __i++) { \
 121                                             SMC_outw( *(__b2 + __i), r ); \
 122                                         } \
 123                                 })
 124
 125 #define SMC_insl(r,b,l)         ({      int __i ;  \
 126                                         dword *__b2;  \
 127                                         __b2 = (dword *) b;  \
 128                                         for (__i = 0; __i < l; __i++) {  \
 129                                           *(__b2 + __i) = SMC_inl(r);  \
 130                                           SMC_inl(0);  \
 131                                         };  \
 132                                 })
 133
 134 #define SMC_insw(r,b,l)         ({      int __i ;  \
 135                                         word *__b2;  \
 136                                         __b2 = (word *) b;  \
 137                                         for (__i = 0; __i < l; __i++) {  \
 138                                           *(__b2 + __i) = SMC_inw(r);  \
 139                                           SMC_inw(0);  \
 140                                         };  \
 141                                 })
 142
 143 #define SMC_insb(r,b,l)         ({      int __i ;  \
 144                                         byte *__b2;  \
 145                                         __b2 = (byte *) b;  \
 146                                         for (__i = 0; __i < l; __i++) {  \
 147                                           *(__b2 + __i) = SMC_inb(r);  \
 148                                           SMC_inb(0);  \
 149                                         };  \
 150                                 })
 151
 152 #else /* if not CONFIG_PXA250 */
 153
 154 /*
 155  * We have only 16 Bit PCMCIA access on Socket 0
 156  */
 157
 158 #define SMC_inw(r)      (*((volatile word *)(SMC_BASE_ADDRESS+(r))))
 159 #define  SMC_inb(r)     (((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF)
 160
 161 #define SMC_outw(d,r)   (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
 162 #define SMC_outb(d,r)   ({      word __d = (byte)(d);  \
 163                                 word __w = SMC_inw((r)&~1);  \
 164                                 __w &= ((r)&1) ? 0x00FF : 0xFF00;  \
 165                                 __w |= ((r)&1) ? __d<<8 : __d;  \
 166                                 SMC_outw(__w,(r)&~1);  \
 167                         })
 168 #if 0
 169 #define SMC_outsw(r,b,l)        outsw(SMC_BASE_ADDRESS+(r), (b), (l))
 170 #else
 171 #define SMC_outsw(r,b,l)        ({      int __i; \
 172                                         word *__b2; \
 173                                         __b2 = (word *) b; \
 174                                         for (__i = 0; __i < l; __i++) { \
 175                                             SMC_outw( *(__b2 + __i), r); \
 176                                         } \
 177                                 })
 178 #endif
 179
 180 #if 0
 181 #define SMC_insw(r,b,l)         insw(SMC_BASE_ADDRESS+(r), (b), (l))
 182 #else
 183 #define SMC_insw(r,b,l)         ({      int __i ;  \
 184                                         word *__b2;  \
 185                                         __b2 = (word *) b;  \
 186                                         for (__i = 0; __i < l; __i++) {  \
 187                                           *(__b2 + __i) = SMC_inw(r);  \
 188                                           SMC_inw(0);  \
 189                                         };  \
 190                                 })
 191 #endif
 192
 193 #endif
 194
 195 /*
 196  ****************************************************************************
 197  *      Bank Select Field
 198  ****************************************************************************
 199  */
 200 #define LAN91C96_BANK_SELECT  14       /* Bank Select Register */
 201 #define LAN91C96_BANKSELECT (0x3UC << 0)
 202 #define BANK0               0x00
 203 #define BANK1               0x01
 204 #define BANK2               0x02
 205 #define BANK3               0x03
 206 #define BANK4               0x04
 207
 208 /*
 209  ****************************************************************************
 210  *      EEPROM Addresses.
 211  ****************************************************************************
 212  */
 213 #define EEPROM_MAC_OFFSET_1    0x6020
 214 #define EEPROM_MAC_OFFSET_2    0x6021
 215 #define EEPROM_MAC_OFFSET_3    0x6022
 216
 217 /*
 218  ****************************************************************************
 219  *      Bank 0 Register Map in I/O Space
 220  ****************************************************************************
 221  */
 222 #define LAN91C96_TCR          0        /* Transmit Control Register */
 223 #define LAN91C96_EPH_STATUS   2        /* EPH Status Register */
 224 #define LAN91C96_RCR          4        /* Receive Control Register */
 225 #define LAN91C96_COUNTER      6        /* Counter Register */
 226 #define LAN91C96_MIR          8        /* Memory Information Register */
 227 #define LAN91C96_MCR          10       /* Memory Configuration Register */
 228
 229 /*
 230  ****************************************************************************
 231  *      Transmit Control Register - Bank 0 - Offset 0
 232  ****************************************************************************
 233  */
 234 #define LAN91C96_TCR_TXENA        (0x1U << 0)
 235 #define LAN91C96_TCR_LOOP         (0x1U << 1)
 236 #define LAN91C96_TCR_FORCOL       (0x1U << 2)
 237 #define LAN91C96_TCR_TXP_EN       (0x1U << 3)
 238 #define LAN91C96_TCR_PAD_EN       (0x1U << 7)
 239 #define LAN91C96_TCR_NOCRC        (0x1U << 8)
 240 #define LAN91C96_TCR_MON_CSN      (0x1U << 10)
 241 #define LAN91C96_TCR_FDUPLX       (0x1U << 11)
 242 #define LAN91C96_TCR_STP_SQET     (0x1U << 12)
 243 #define LAN91C96_TCR_EPH_LOOP     (0x1U << 13)
 244 #define LAN91C96_TCR_ETEN_TYPE    (0x1U << 14)
 245 #define LAN91C96_TCR_FDSE         (0x1U << 15)
 246
 247 /*
 248  ****************************************************************************
 249  *      EPH Status Register - Bank 0 - Offset 2
 250  ****************************************************************************
 251  */
 252 #define LAN91C96_EPHSR_TX_SUC     (0x1U << 0)
 253 #define LAN91C96_EPHSR_SNGL_COL   (0x1U << 1)
 254 #define LAN91C96_EPHSR_MUL_COL    (0x1U << 2)
 255 #define LAN91C96_EPHSR_LTX_MULT   (0x1U << 3)
 256 #define LAN91C96_EPHSR_16COL      (0x1U << 4)
 257 #define LAN91C96_EPHSR_SQET       (0x1U << 5)
 258 #define LAN91C96_EPHSR_LTX_BRD    (0x1U << 6)
 259 #define LAN91C96_EPHSR_TX_DEFR    (0x1U << 7)
 260 #define LAN91C96_EPHSR_WAKEUP     (0x1U << 8)
 261 #define LAN91C96_EPHSR_LATCOL     (0x1U << 9)
 262 #define LAN91C96_EPHSR_LOST_CARR  (0x1U << 10)
 263 #define LAN91C96_EPHSR_EXC_DEF    (0x1U << 11)
 264 #define LAN91C96_EPHSR_CTR_ROL    (0x1U << 12)
 265
 266 #define LAN91C96_EPHSR_LINK_OK    (0x1U << 14)
 267 #define LAN91C96_EPHSR_TX_UNRN    (0x1U << 15)
 268
 269 #define LAN91C96_EPHSR_ERRORS     (LAN91C96_EPHSR_SNGL_COL  |    \
 270                                    LAN91C96_EPHSR_MUL_COL   |    \
 271                                    LAN91C96_EPHSR_16COL     |    \
 272                                    LAN91C96_EPHSR_SQET      |    \
 273                                    LAN91C96_EPHSR_TX_DEFR   |    \
 274                                    LAN91C96_EPHSR_LATCOL    |    \
 275                                    LAN91C96_EPHSR_LOST_CARR |    \
 276                                    LAN91C96_EPHSR_EXC_DEF   |    \
 277                                    LAN91C96_EPHSR_LINK_OK   |    \
 278                                    LAN91C96_EPHSR_TX_UNRN)
 279
 280 /*
 281  ****************************************************************************
 282  *      Receive Control Register - Bank 0 - Offset 4
 283  ****************************************************************************
 284  */
 285 #define LAN91C96_RCR_RX_ABORT     (0x1U << 0)
 286 #define LAN91C96_RCR_PRMS         (0x1U << 1)
 287 #define LAN91C96_RCR_ALMUL        (0x1U << 2)
 288 #define LAN91C96_RCR_RXEN         (0x1U << 8)
 289 #define LAN91C96_RCR_STRIP_CRC    (0x1U << 9)
 290 #define LAN91C96_RCR_FILT_CAR     (0x1U << 14)
 291 #define LAN91C96_RCR_SOFT_RST     (0x1U << 15)
 292
 293 /*
 294  ****************************************************************************
 295  *      Counter Register - Bank 0 - Offset 6
 296  ****************************************************************************
 297  */
 298 #define LAN91C96_ECR_SNGL_COL     (0xFU << 0)
 299 #define LAN91C96_ECR_MULT_COL     (0xFU << 5)
 300 #define LAN91C96_ECR_DEF_TX       (0xFU << 8)
 301 #define LAN91C96_ECR_EXC_DEF_TX   (0xFU << 12)
 302
 303 /*
 304  ****************************************************************************
 305  *      Memory Information Register - Bank 0 - OFfset 8
 306  ****************************************************************************
 307  */
 308 #define LAN91C96_MIR_SIZE        (0x18 << 0)    /* 6144 bytes */
 309
 310 /*
 311  ****************************************************************************
 312  *      Memory Configuration Register - Bank 0 - Offset 10
 313  ****************************************************************************
 314  */
 315 #define LAN91C96_MCR_MEM_RES      (0xFFU << 0)
 316 #define LAN91C96_MCR_MEM_MULT     (0x3U << 9)
 317 #define LAN91C96_MCR_HIGH_ID      (0x3U << 12)
 318
 319 #define LAN91C96_MCR_TRANSMIT_PAGES 0x6
 320
 321 /*
 322  ****************************************************************************
 323  *      Bank 1 Register Map in I/O Space
 324  ****************************************************************************
 325  */
 326 #define LAN91C96_CONFIG       0        /* Configuration Register */
 327 #define LAN91C96_BASE         2        /* Base Address Register */
 328 #define LAN91C96_IA0          4        /* Individual Address Register - 0 */
 329 #define LAN91C96_IA1          5        /* Individual Address Register - 1 */
 330 #define LAN91C96_IA2          6        /* Individual Address Register - 2 */
 331 #define LAN91C96_IA3          7        /* Individual Address Register - 3 */
 332 #define LAN91C96_IA4          8        /* Individual Address Register - 4 */
 333 #define LAN91C96_IA5          9        /* Individual Address Register - 5 */
 334 #define LAN91C96_GEN_PURPOSE  10       /* General Address Registers */
 335 #define LAN91C96_CONTROL      12       /* Control Register */
 336
 337 /*
 338  ****************************************************************************
 339  *      Configuration Register - Bank 1 - Offset 0
 340  ****************************************************************************
 341  */
 342 #define LAN91C96_CR_INT_SEL0      (0x1U << 1)
 343 #define LAN91C96_CR_INT_SEL1      (0x1U << 2)
 344 #define LAN91C96_CR_RES           (0x3U << 3)
 345 #define LAN91C96_CR_DIS_LINK      (0x1U << 6)
 346 #define LAN91C96_CR_16BIT         (0x1U << 7)
 347 #define LAN91C96_CR_AUI_SELECT    (0x1U << 8)
 348 #define LAN91C96_CR_SET_SQLCH     (0x1U << 9)
 349 #define LAN91C96_CR_FULL_STEP     (0x1U << 10)
 350 #define LAN91C96_CR_NO_WAIT       (0x1U << 12)
 351
 352 /*
 353  ****************************************************************************
 354  *      Base Address Register - Bank 1 - Offset 2
 355  ****************************************************************************
 356  */
 357 #define LAN91C96_BAR_RA_BITS      (0x27U << 0)
 358 #define LAN91C96_BAR_ROM_SIZE     (0x1U << 6)
 359 #define LAN91C96_BAR_A_BITS       (0xFFU << 8)
 360
 361 /*
 362  ****************************************************************************
 363  *      Control Register - Bank 1 - Offset 12
 364  ****************************************************************************
 365  */
 366 #define LAN91C96_CTR_STORE        (0x1U << 0)
 367 #define LAN91C96_CTR_RELOAD       (0x1U << 1)
 368 #define LAN91C96_CTR_EEPROM       (0x1U << 2)
 369 #define LAN91C96_CTR_TE_ENABLE    (0x1U << 5)
 370 #define LAN91C96_CTR_CR_ENABLE    (0x1U << 6)
 371 #define LAN91C96_CTR_LE_ENABLE    (0x1U << 7)
 372 #define LAN91C96_CTR_BIT_8        (0x1U << 8)
 373 #define LAN91C96_CTR_AUTO_RELEASE (0x1U << 11)
 374 #define LAN91C96_CTR_WAKEUP_EN    (0x1U << 12)
 375 #define LAN91C96_CTR_PWRDN        (0x1U << 13)
 376 #define LAN91C96_CTR_RCV_BAD      (0x1U << 14)
 377
 378 /*
 379  ****************************************************************************
 380  *      Bank 2 Register Map in I/O Space
 381  ****************************************************************************
 382  */
 383 #define LAN91C96_MMU            0      /* MMU Command Register */
 384 #define LAN91C96_AUTO_TX_START  1      /* Auto Tx Start Register */
 385 #define LAN91C96_PNR            2      /* Packet Number Register */
 386 #define LAN91C96_ARR            3      /* Allocation Result Register */
 387 #define LAN91C96_FIFO           4      /* FIFO Ports Register */
 388 #define LAN91C96_POINTER        6      /* Pointer Register */
 389 #define LAN91C96_DATA_HIGH      8      /* Data High Register */
 390 #define LAN91C96_DATA_LOW       10     /* Data Low Register */
 391 #define LAN91C96_INT_STATS      12     /* Interrupt Status Register - RO */
 392 #define LAN91C96_INT_ACK        12     /* Interrupt Acknowledge Register -WO */
 393 #define LAN91C96_INT_MASK       13     /* Interrupt Mask Register */
 394
 395 /*
 396  ****************************************************************************
 397  *      MMU Command Register - Bank 2 - Offset 0
 398  ****************************************************************************
 399  */
 400 #define LAN91C96_MMUCR_NO_BUSY    (0x1U << 0)
 401 #define LAN91C96_MMUCR_N1         (0x1U << 1)
 402 #define LAN91C96_MMUCR_N2         (0x1U << 2)
 403 #define LAN91C96_MMUCR_COMMAND    (0xFU << 4)
 404 #define LAN91C96_MMUCR_ALLOC_TX   (0x2U << 4)    /* WXYZ = 0010 */
 405 #define LAN91C96_MMUCR_RESET_MMU  (0x4U << 4)    /* WXYZ = 0100 */
 406 #define LAN91C96_MMUCR_REMOVE_RX  (0x6U << 4)    /* WXYZ = 0110 */
 407 #define LAN91C96_MMUCR_REMOVE_TX  (0x7U << 4)    /* WXYZ = 0111 */
 408 #define LAN91C96_MMUCR_RELEASE_RX (0x8U << 4)    /* WXYZ = 1000 */
 409 #define LAN91C96_MMUCR_RELEASE_TX (0xAU << 4)    /* WXYZ = 1010 */
 410 #define LAN91C96_MMUCR_ENQUEUE    (0xCU << 4)    /* WXYZ = 1100 */
 411 #define LAN91C96_MMUCR_RESET_TX   (0xEU << 4)    /* WXYZ = 1110 */
 412
 413 /*
 414  ****************************************************************************
 415  *      Auto Tx Start Register - Bank 2 - Offset 1
 416  ****************************************************************************
 417  */
 418 #define LAN91C96_AUTOTX           (0xFFU << 0)
 419
 420 /*
 421  ****************************************************************************
 422  *      Packet Number Register - Bank 2 - Offset 2
 423  ****************************************************************************
 424  */
 425 #define LAN91C96_PNR_TX           (0x1FU << 0)
 426
 427 /*
 428  ****************************************************************************
 429  *      Allocation Result Register - Bank 2 - Offset 3
 430  ****************************************************************************
 431  */
 432 #define LAN91C96_ARR_ALLOC_PN     (0x7FU << 0)
 433 #define LAN91C96_ARR_FAILED       (0x1U << 7)
 434
 435 /*
 436  ****************************************************************************
 437  *      FIFO Ports Register - Bank 2 - Offset 4
 438  ****************************************************************************
 439  */
 440 #define LAN91C96_FIFO_TX_DONE_PN  (0x1FU << 0)
 441 #define LAN91C96_FIFO_TEMPTY      (0x1U << 7)
 442 #define LAN91C96_FIFO_RX_DONE_PN  (0x1FU << 8)
 443 #define LAN91C96_FIFO_RXEMPTY     (0x1U << 15)
 444
 445 /*
 446  ****************************************************************************
 447  *      Pointer Register - Bank 2 - Offset 6
 448  ****************************************************************************
 449  */
 450 #define LAN91C96_PTR_LOW          (0xFFU << 0)
 451 #define LAN91C96_PTR_HIGH         (0x7U << 8)
 452 #define LAN91C96_PTR_AUTO_TX      (0x1U << 11)
 453 #define LAN91C96_PTR_ETEN         (0x1U << 12)
 454 #define LAN91C96_PTR_READ         (0x1U << 13)
 455 #define LAN91C96_PTR_AUTO_INCR    (0x1U << 14)
 456 #define LAN91C96_PTR_RCV          (0x1U << 15)
 457
 458 #define LAN91C96_PTR_RX_FRAME     (LAN91C96_PTR_RCV       |    \
 459                                    LAN91C96_PTR_AUTO_INCR |    \
 460                                    LAN91C96_PTR_READ)
 461
 462 /*
 463  ****************************************************************************
 464  *      Data Register - Bank 2 - Offset 8
 465  ****************************************************************************
 466  */
 467 #define LAN91C96_CONTROL_CRC      (0x1U << 4)    /* CRC bit */
 468 #define LAN91C96_CONTROL_ODD      (0x1U << 5)    /* ODD bit */
 469
 470 /*
 471  ****************************************************************************
 472  *      Interrupt Status Register - Bank 2 - Offset 12
 473  ****************************************************************************
 474  */
 475 #define LAN91C96_IST_RCV_INT      (0x1U << 0)
 476 #define LAN91C96_IST_TX_INT       (0x1U << 1)
 477 #define LAN91C96_IST_TX_EMPTY_INT (0x1U << 2)
 478 #define LAN91C96_IST_ALLOC_INT    (0x1U << 3)
 479 #define LAN91C96_IST_RX_OVRN_INT  (0x1U << 4)
 480 #define LAN91C96_IST_EPH_INT      (0x1U << 5)
 481 #define LAN91C96_IST_ERCV_INT     (0x1U << 6)
 482 #define LAN91C96_IST_RX_IDLE_INT  (0x1U << 7)
 483
 484 /*
 485  ****************************************************************************
 486  *      Interrupt Acknowledge Register - Bank 2 - Offset 12
 487  ****************************************************************************
 488  */
 489 #define LAN91C96_ACK_TX_INT       (0x1U << 1)
 490 #define LAN91C96_ACK_TX_EMPTY_INT (0x1U << 2)
 491 #define LAN91C96_ACK_RX_OVRN_INT  (0x1U << 4)
 492 #define LAN91C96_ACK_ERCV_INT     (0x1U << 6)
 493
 494 /*
 495  ****************************************************************************
 496  *      Interrupt Mask Register - Bank 2 - Offset 13
 497  ****************************************************************************
 498  */
 499 #define LAN91C96_MSK_RCV_INT      (0x1U << 0)
 500 #define LAN91C96_MSK_TX_INT       (0x1U << 1)
 501 #define LAN91C96_MSK_TX_EMPTY_INT (0x1U << 2)
 502 #define LAN91C96_MSK_ALLOC_INT    (0x1U << 3)
 503 #define LAN91C96_MSK_RX_OVRN_INT  (0x1U << 4)
 504 #define LAN91C96_MSK_EPH_INT      (0x1U << 5)
 505 #define LAN91C96_MSK_ERCV_INT     (0x1U << 6)
 506 #define LAN91C96_MSK_TX_IDLE_INT  (0x1U << 7)
 507
 508 /*
 509  ****************************************************************************
 510  *      Bank 3 Register Map in I/O Space
 511  **************************************************************************
 512  */
 513 #define LAN91C96_MGMT_MDO         (0x1U << 0)
 514 #define LAN91C96_MGMT_MDI         (0x1U << 1)
 515 #define LAN91C96_MGMT_MCLK        (0x1U << 2)
 516 #define LAN91C96_MGMT_MDOE        (0x1U << 3)
 517 #define LAN91C96_MGMT_LOW_ID      (0x3U << 4)
 518 #define LAN91C96_MGMT_IOS0        (0x1U << 8)
 519 #define LAN91C96_MGMT_IOS1        (0x1U << 9)
 520 #define LAN91C96_MGMT_IOS2        (0x1U << 10)
 521 #define LAN91C96_MGMT_nXNDEC      (0x1U << 11)
 522 #define LAN91C96_MGMT_HIGH_ID     (0x3U << 12)
 523
 524 /*
 525  ****************************************************************************
 526  *      Revision Register - Bank 3 - Offset 10
 527  ****************************************************************************
 528  */
 529 #define LAN91C96_REV_REVID        (0xFU << 0)
 530 #define LAN91C96_REV_CHIPID       (0xFU << 4)
 531
 532 /*
 533  ****************************************************************************
 534  *      Early RCV Register - Bank 3 - Offset 12
 535  ****************************************************************************
 536  */
 537 #define LAN91C96_ERCV_THRESHOLD   (0x1FU << 0)
 538 #define LAN91C96_ERCV_RCV_DISCRD  (0x1U << 7)
 539
 540 /*
 541  ****************************************************************************
 542  *      PCMCIA Configuration Registers
 543  ****************************************************************************
 544  */
 545 #define LAN91C96_ECOR    0x8000        /* Ethernet Configuration Register */
 546 #define LAN91C96_ECSR    0x8002        /* Ethernet Configuration and Status */
 547
 548 /*
 549  ****************************************************************************
 550  *      PCMCIA Ethernet Configuration Option Register (ECOR)
 551  ****************************************************************************
 552  */
 553 #define LAN91C96_ECOR_ENABLE       (0x1U << 0)
 554 #define LAN91C96_ECOR_WR_ATTRIB    (0x1U << 2)
 555 #define LAN91C96_ECOR_LEVEL_REQ    (0x1U << 6)
 556 #define LAN91C96_ECOR_SRESET       (0x1U << 7)
 557
 558 /*
 559  ****************************************************************************
 560  *      PCMCIA Ethernet Configuration and Status Register (ECSR)
 561  ****************************************************************************
 562  */
 563 #define LAN91C96_ECSR_INTR        (0x1U << 1)
 564 #define LAN91C96_ECSR_PWRDWN      (0x1U << 2)
 565 #define LAN91C96_ECSR_IOIS8       (0x1U << 5)
 566
 567 /*
 568  ****************************************************************************
 569  *      Receive Frame Status Word - See page 38 of the LAN91C96 specification.
 570  ****************************************************************************
 571  */
 572 #define LAN91C96_TOO_SHORT        (0x1U << 10)
 573 #define LAN91C96_TOO_LONG         (0x1U << 11)
 574 #define LAN91C96_ODD_FRM          (0x1U << 12)
 575 #define LAN91C96_BAD_CRC          (0x1U << 13)
 576 #define LAN91C96_BROD_CAST        (0x1U << 14)
 577 #define LAN91C96_ALGN_ERR         (0x1U << 15)
 578
 579 #define FRAME_FILTER              (LAN91C96_TOO_SHORT | LAN91C96_TOO_LONG  | LAN91C96_BAD_CRC   | LAN91C96_ALGN_ERR)
 580
 581 /*
 582  ****************************************************************************
 583  *      Default MAC Address
 584  ****************************************************************************
 585  */
 586 #define MAC_DEF_HI  0x0800
 587 #define MAC_DEF_MED 0x3333
 588 #define MAC_DEF_LO  0x0100
 589
 590 /*
 591  ****************************************************************************
 592  *      Default I/O Signature - 0x33
 593  ****************************************************************************
 594  */
 595 #define LAN91C96_LOW_SIGNATURE        (0x33U << 0)
 596 #define LAN91C96_HIGH_SIGNATURE       (0x33U << 8)
 597 #define LAN91C96_SIGNATURE (LAN91C96_HIGH_SIGNATURE | LAN91C96_LOW_SIGNATURE)
 598
 599 #define LAN91C96_MAX_PAGES     6        /* Maximum number of 256 pages. */
 600 #define ETHERNET_MAX_LENGTH 1514
 601
 602
 603 /*-------------------------------------------------------------------------
 604  *  I define some macros to make it easier to do somewhat common
 605  * or slightly complicated, repeated tasks.
 606  *-------------------------------------------------------------------------
 607  */
 608
 609 /* select a register bank, 0 to 3  */
 610
 611 #define SMC_SELECT_BANK(x)  { SMC_outw( x, LAN91C96_BANK_SELECT ); }
 612
 613 /* this enables an interrupt in the interrupt mask register */
 614 #define SMC_ENABLE_INT(x) {\
 615                 unsigned char mask;\
 616                 SMC_SELECT_BANK(2);\
 617                 mask = SMC_inb( LAN91C96_INT_MASK );\
 618                 mask |= (x);\
 619                 SMC_outb( mask, LAN91C96_INT_MASK ); \
 620 }
 621
 622 /* this disables an interrupt from the interrupt mask register */
 623
 624 #define SMC_DISABLE_INT(x) {\
 625                 unsigned char mask;\
 626                 SMC_SELECT_BANK(2);\
 627                 mask = SMC_inb( LAN91C96_INT_MASK );\
 628                 mask &= ~(x);\
 629                 SMC_outb( mask, LAN91C96_INT_MASK ); \
 630 }
 631
 632 /*----------------------------------------------------------------------
 633  * Define the interrupts that I want to receive from the card
 634  *
 635  * I want:
 636  *  LAN91C96_IST_EPH_INT, for nasty errors
 637  *  LAN91C96_IST_RCV_INT, for happy received packets
 638  *  LAN91C96_IST_RX_OVRN_INT, because I have to kick the receiver
 639  *-------------------------------------------------------------------------
 640  */
 641 #define SMC_INTERRUPT_MASK   (LAN91C96_IST_EPH_INT | LAN91C96_IST_RX_OVRN_INT | LAN91C96_IST_RCV_INT)
 642
 643 #endif  /* _LAN91C96_H_ */