Added support for the Hynix HY27US08121A 64MB Flash chip.
[u-boot-openmoko/mini2440.git] / drivers / i2c / tsi108_i2c.c
blobd6736b0477e663d8d4eafb6e65007175d3049042
1 /*
2 * (C) Copyright 2004 Tundra Semiconductor Corp.
3 * Author: Alex Bounine
5 * See file CREDITS for list of people who contributed to this
6 * project.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
25 #include <config.h>
26 #include <common.h>
28 #ifdef CONFIG_TSI108_I2C
29 #include <tsi108.h>
31 #if defined(CONFIG_CMD_I2C)
33 #define I2C_DELAY 100000
34 #undef DEBUG_I2C
36 #ifdef DEBUG_I2C
37 #define DPRINT(x) printf (x)
38 #else
39 #define DPRINT(x)
40 #endif
42 /* All functions assume that Tsi108 I2C block is the only master on the bus */
43 /* I2C read helper function */
45 static int i2c_read_byte (
46 uint i2c_chan, /* I2C channel number: 0 - main, 1 - SDC SPD */
47 uchar chip_addr,/* I2C device address on the bus */
48 uint byte_addr, /* Byte address within I2C device */
49 uchar * buffer /* pointer to data buffer */
52 u32 temp;
53 u32 to_count = I2C_DELAY;
54 u32 op_status = TSI108_I2C_TIMEOUT_ERR;
55 u32 chan_offset = TSI108_I2C_OFFSET;
57 DPRINT (("I2C read_byte() %d 0x%02x 0x%02x\n",
58 i2c_chan, chip_addr, byte_addr));
60 if (0 != i2c_chan)
61 chan_offset = TSI108_I2C_SDRAM_OFFSET;
63 /* Check if I2C operation is in progress */
64 temp = *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2);
66 if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS |
67 I2C_CNTRL2_START))) {
68 /* Set device address and operation (read = 0) */
69 temp = (byte_addr << 16) | ((chip_addr & 0x07) << 8) |
70 ((chip_addr >> 3) & 0x0F);
71 *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL1) =
72 temp;
74 /* Issue the read command
75 * (at this moment all other parameters are 0
76 * (size = 1 byte, lane = 0)
79 *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2) =
80 (I2C_CNTRL2_START);
82 /* Wait until operation completed */
83 do {
84 /* Read I2C operation status */
85 temp = *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2);
87 if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_START))) {
88 if (0 == (temp &
89 (I2C_CNTRL2_I2C_CFGERR |
90 I2C_CNTRL2_I2C_TO_ERR))
91 ) {
92 op_status = TSI108_I2C_SUCCESS;
94 temp = *(u32 *) (CFG_TSI108_CSR_BASE +
95 chan_offset +
96 I2C_RD_DATA);
98 *buffer = (u8) (temp & 0xFF);
99 } else {
100 /* report HW error */
101 op_status = TSI108_I2C_IF_ERROR;
103 DPRINT (("I2C HW error reported: 0x%02x\n", temp));
106 break;
108 } while (to_count--);
109 } else {
110 op_status = TSI108_I2C_IF_BUSY;
112 DPRINT (("I2C Transaction start failed: 0x%02x\n", temp));
115 DPRINT (("I2C read_byte() status: 0x%02x\n", op_status));
116 return op_status;
120 * I2C Read interface as defined in "include/i2c.h" :
121 * chip_addr: I2C chip address, range 0..127
122 * (to read from SPD channel EEPROM use (0xD0 ... 0xD7)
123 * NOTE: The bit 7 in the chip_addr serves as a channel select.
124 * This hack is for enabling "isdram" command on Tsi108 boards
125 * without changes to common code. Used for I2C reads only.
126 * byte_addr: Memory or register address within the chip
127 * alen: Number of bytes to use for addr (typically 1, 2 for larger
128 * memories, 0 for register type devices with only one
129 * register)
130 * buffer: Pointer to destination buffer for data to be read
131 * len: How many bytes to read
133 * Returns: 0 on success, not 0 on failure
136 int i2c_read (uchar chip_addr, uint byte_addr, int alen,
137 uchar * buffer, int len)
139 u32 op_status = TSI108_I2C_PARAM_ERR;
140 u32 i2c_if = 0;
142 /* Hack to support second (SPD) I2C controller (SPD EEPROM read only).*/
143 if (0xD0 == (chip_addr & ~0x07)) {
144 i2c_if = 1;
145 chip_addr &= 0x7F;
147 /* Check for valid I2C address */
148 if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) {
149 while (len--) {
150 op_status = i2c_read_byte(i2c_if, chip_addr, byte_addr++, buffer++);
152 if (TSI108_I2C_SUCCESS != op_status) {
153 DPRINT (("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len));
155 break;
160 DPRINT (("I2C read() status: 0x%02x\n", op_status));
161 return op_status;
164 /* I2C write helper function */
166 static int i2c_write_byte (uchar chip_addr,/* I2C device address on the bus */
167 uint byte_addr, /* Byte address within I2C device */
168 uchar * buffer /* pointer to data buffer */
171 u32 temp;
172 u32 to_count = I2C_DELAY;
173 u32 op_status = TSI108_I2C_TIMEOUT_ERR;
175 /* Check if I2C operation is in progress */
176 temp = *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2);
178 if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) {
179 /* Place data into the I2C Tx Register */
180 *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
181 I2C_TX_DATA) = (u32) * buffer;
183 /* Set device address and operation */
184 temp =
185 I2C_CNTRL1_I2CWRITE | (byte_addr << 16) |
186 ((chip_addr & 0x07) << 8) | ((chip_addr >> 3) & 0x0F);
187 *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
188 I2C_CNTRL1) = temp;
190 /* Issue the write command (at this moment all other parameters
191 * are 0 (size = 1 byte, lane = 0)
194 *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
195 I2C_CNTRL2) = (I2C_CNTRL2_START);
197 op_status = TSI108_I2C_TIMEOUT_ERR;
199 /* Wait until operation completed */
200 do {
201 /* Read I2C operation status */
202 temp = *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2);
204 if (0 == (temp & (I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) {
205 if (0 == (temp &
206 (I2C_CNTRL2_I2C_CFGERR |
207 I2C_CNTRL2_I2C_TO_ERR))) {
208 op_status = TSI108_I2C_SUCCESS;
209 } else {
210 /* report detected HW error */
211 op_status = TSI108_I2C_IF_ERROR;
213 DPRINT (("I2C HW error reported: 0x%02x\n", temp));
216 break;
219 } while (to_count--);
220 } else {
221 op_status = TSI108_I2C_IF_BUSY;
223 DPRINT (("I2C Transaction start failed: 0x%02x\n", temp));
226 return op_status;
230 * I2C Write interface as defined in "include/i2c.h" :
231 * chip_addr: I2C chip address, range 0..127
232 * byte_addr: Memory or register address within the chip
233 * alen: Number of bytes to use for addr (typically 1, 2 for larger
234 * memories, 0 for register type devices with only one
235 * register)
236 * buffer: Pointer to data to be written
237 * len: How many bytes to write
239 * Returns: 0 on success, not 0 on failure
242 int i2c_write (uchar chip_addr, uint byte_addr, int alen, uchar * buffer,
243 int len)
245 u32 op_status = TSI108_I2C_PARAM_ERR;
247 /* Check for valid I2C address */
248 if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) {
249 while (len--) {
250 op_status =
251 i2c_write_byte (chip_addr, byte_addr++, buffer++);
253 if (TSI108_I2C_SUCCESS != op_status) {
254 DPRINT (("I2C write_byte() failed: 0x%02x (%d left)\n", op_status, len));
256 break;
261 return op_status;
265 * I2C interface function as defined in "include/i2c.h".
266 * Probe the given I2C chip address by reading single byte from offset 0.
267 * Returns 0 if a chip responded, not 0 on failure.
270 int i2c_probe (uchar chip)
272 u32 tmp;
275 * Try to read the first location of the chip.
276 * The Tsi108 HW doesn't support sending just the chip address
277 * and checkong for an <ACK> back.
279 return i2c_read (chip, 0, 1, (uchar *)&tmp, 1);
282 #endif
283 #endif /* CONFIG_TSI108_I2C */