Fixed tools/env utilities
[u-boot-openmoko/mini2440.git] / include / mpc5xx.h
blob414651fa0f8b81c6b401ecabcf87fb843410c7e4
1 /*
2 * (C) Copyright 2003
3 * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
5 * See file CREDITS for list of people who contributed to this
6 * project.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
25 * File: mpc5xx.h
27 * Discription: mpc5xx specific definitions
31 #ifndef __MPC5XX_H__
32 #define __MPC5XX_H__
35 /*-----------------------------------------------------------------------
36 * Exception offsets (PowerPC standard)
38 #define EXC_OFF_SYS_RESET 0x0100 /* System reset */
39 #define _START_OFFSET EXC_OFF_SYS_RESET
41 /*-----------------------------------------------------------------------
42 * ISB bit in IMMR to set internal memory map
45 #define CFG_ISB ((CFG_IMMR / 0x00400000) << 1)
47 /*-----------------------------------------------------------------------
48 * SYPCR - System Protection Control Register
50 #define SYPCR_SWTC 0xffff0000 /* Software Watchdog Timer Count */
51 #define SYPCR_BMT 0x0000ff00 /* Bus Monitor Timing */
52 #define SYPCR_BME 0x00000080 /* Bus Monitor Enable */
53 #define SYPCR_SWF 0x00000008 /* Software Watchdog Freeze */
54 #define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */
55 #define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select */
56 #define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */
58 /*-----------------------------------------------------------------------
59 * SIUMCR - SIU Module Configuration Register
61 #define SIUMCR_EARB 0x80000000 /* External Arbitration */
62 #define SIUMCR_EARP0 0x00000000 /* External Arbi. Request priority 0 */
63 #define SIUMCR_EARP1 0x10000000 /* External Arbi. Request priority 1 */
64 #define SIUMCR_EARP2 0x20000000 /* External Arbi. Request priority 2 */
65 #define SIUMCR_EARP3 0x30000000 /* External Arbi. Request priority 3 */
66 #define SIUMCR_EARP4 0x40000000 /* External Arbi. Request priority 4 */
67 #define SIUMCR_EARP5 0x50000000 /* External Arbi. Request priority 5 */
68 #define SIUMCR_EARP6 0x60000000 /* External Arbi. Request priority 6 */
69 #define SIUMCR_EARP7 0x70000000 /* External Arbi. Request priority 7 */
70 #define SIUMCR_DSHW 0x00800000 /* Data Showcycles */
71 #define SIUMCR_DBGC00 0x00000000 /* Debug pins configuration */
72 #define SIUMCR_DBGC01 0x00200000 /* - " - */
73 #define SIUMCR_DBGC10 0x00400000 /* - " - */
74 #define SIUMCR_DBGC11 0x00600000 /* - " - */
75 #define SIUMCR_DBPC00 0x00000000 /* Debug Port pins Config. */
76 #define SIUMCR_DBPC01 0x00080000 /* - " - */
77 #define SIUMCR_DBPC10 0x00100000 /* - " - */
78 #define SIUMCR_DBPC11 0x00180000 /* - " - */
79 #define SIUMCR_GPC00 0x00000000 /* General Pins Config */
80 #define SIUMCR_GPC01 0x00020000 /* General Pins Config */
81 #define SIUMCR_GPC10 0x00040000 /* General Pins Config */
82 #define SIUMCR_GPC11 0x00060000 /* General Pins Config */
83 #define SIUMCR_DLK 0x00010000 /* Debug Register Lock */
84 #define SIUMCR_SC00 0x00000000 /* Multi Chip 32 bit */
85 #define SIUMCR_SC01 0x00004000 /* Muilt Chip 16 bit */
86 #define SIUMCR_SC10 0x00004000 /* Single adress show */
87 #define SIUMCR_SC11 0x00006000 /* Single adress */
88 #define SIUMCR_RCTX 0x00001000 /* Data Parity pins Config. */
89 #define SIUMCR_MLRC00 0x00000000 /* Multi Level Reserva. Ctrl */
90 #define SIUMCR_MLRC01 0x00000400 /* - " - */
91 #define SIUMCR_MLRC10 0x00000800 /* - " - */
92 #define SIUMCR_MLRC11 0x00000c00 /* - " - */
93 #define SIUMCR_MTSC 0x00000100 /* Memory transfer */
95 /*-----------------------------------------------------------------------
96 * TBSCR - Time Base Status and Control Register
98 #define TBSCR_REFA ((ushort)0x0080) /* Reference Interrupt Status A */
99 #define TBSCR_REFB ((ushort)0x0040) /* Reference Interrupt Status B */
100 #define TBSCR_TBF ((ushort)0x0002) /* Time Base stops while FREEZE */
102 /*-----------------------------------------------------------------------
103 * PISCR - Periodic Interrupt Status and Control Register
105 #define PISCR_PITF ((ushort)0x0002) /* PIT stops when FREEZE */
106 #define PISCR_PS 0x0080 /* Periodic Interrupt Status */
108 /*-----------------------------------------------------------------------
109 * PLPRCR - PLL, Low-Power, and Reset Control Register
111 #define PLPRCR_MF_MSK 0xfff00000 /* MF mask */
112 #define PLPRCR_DIVF_MSK 0x0000001f /* DIVF mask */
113 #define PLPRCR_CSRC_MSK 0x00000400 /* CSRC mask */
114 #define PLPRCR_MF_SHIFT 0x00000014 /* Multiplication factor shift value */
115 #define PLPRCR_DIVF_0 0x00000000 /* Division factor 0 */
116 #define PLPRCR_MF_9 0x00900000 /* Mulitipliaction factor 9 */
117 #define PLPRCR_TEXPS 0x00004000 /* TEXP Status */
118 #define PLPRCR_TMIST 0x00001000 /* Timers Interrupt Status */
119 #define PLPRCR_CSR 0x00000080 /* CheskStop Reset value */
120 #define PLPRCR_SPLSS 0x00008000 /* SPLL Lock Status Sticky bit */
122 /*-----------------------------------------------------------------------
123 * SCCR - System Clock and reset Control Register
125 #define SCCR_DFNL_MSK 0x00000070 /* DFNL mask */
126 #define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */
127 #define SCCR_DFNL_SHIFT 0x0000004 /* DFNL shift value */
128 #define SCCR_RTSEL 0x00100000 /* RTC circuit input source select */
129 #define SCCR_EBDF00 0x00000000 /* Division factor 1. CLKOUT is GCLK2 */
130 #define SCCR_EBDF11 0x00060000 /* reserved */
131 #define SCCR_TBS 0x02000000 /* Time Base Source */
132 #define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */
133 #define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */
134 #define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */
135 #define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */
136 #define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */
138 /*-----------------------------------------------------------------------
139 * MC - Memory Controller
141 #define BR_V 0x00000001 /* Bank valid */
142 #define BR_BI 0x00000002 /* Burst inhibit */
143 #define BR_PS_8 0x00000400 /* 8 bit port size */
144 #define BR_PS_16 0x00000800 /* 16 bit port size */
145 #define BR_PS_32 0x00000000 /* 32 bit port size */
146 #define BR_LBDIR 0x00000008 /* Late burst data in progess */
147 #define BR_SETA 0x00000004 /* External Data Acknowledge */
148 #define OR_SCY_3 0x00000030 /* 3 clock cycles wait states */
149 #define OR_SCY_1 0x00000000 /* 1 clock cycle wait state */
150 #define OR_SCY_8 0x00000080 /* 8 clock cycles wait states */
151 #define OR_TRLX 0x00000001 /* Timing relaxed */
152 #define OR_BSCY 0x00000060 /* Burst beats length in clocks */
153 #define OR_ACS_10 0x00000600 /* Adress to chip-select setup */
154 #define OR_CSNT 0x00000800 /* Chip-select negotation time */
155 #define OR_ETHR 0x00000100 /* Extended hold time on read */
156 #define OR_ADDR_MK_FF 0xFF000000
157 #define OR_ADDR_MK_FFFF 0xFFFF0000
159 /*-----------------------------------------------------------------------
160 * UMCR - UIMB Module Configuration Register
162 #define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */
163 #define UMCR_HSPEED 0x10000000 /* Half speed */
165 /*-----------------------------------------------------------------------
166 * ICTRL - I-Bus Support Control Register
168 #define ICTRL_ISCT_SER_7 0x00000007 /* All indirect change of flow */
171 #define NR_IRQS 0 /* Place this later in a separate file */
173 /*-----------------------------------------------------------------------
174 * SCI - Serial communication interface
177 #define SCI_TDRE 0x0100 /* Transmit data register empty */
178 #define SCI_TE 0x0008 /* Transmitter enabled */
179 #define SCI_RE 0x0004 /* Receiver enabled */
180 #define SCI_RDRF 0x0040 /* Receive data register full */
181 #define SCI_PE 0x0400 /* Parity enable */
182 #define SCI_SCXBR_MK 0x1fff /* Baudrate mask */
183 #define SCI_SCXDR_MK 0x00ff /* Data register mask */
184 #define SCI_M_11 0x0200 /* Frame size is 11 bit */
185 #define SCI_M_10 0x0000 /* Frame size is 10 bit */
186 #define SCI_PORT_1 ((int)1) /* Place this later somewhere better */
187 #define SCI_PORT_2 ((int)2)
189 #endif /* __MPC5XX_H__ */