include/configs/MPC8548CDS.h

   1 /*
   2  * Copyright 2004, 2007 Freescale Semiconductor.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * mpc8548cds board configuration file
  25  *
  26  * Please refer to doc/README.mpc85xxcds for more info.
  27  *
  28  */
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 /* High Level Configuration Options */
  33 #define CONFIG_BOOKE            1       /* BOOKE */
  34 #define CONFIG_E500             1       /* BOOKE e500 family */
  35 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48 */
  36 #define CONFIG_MPC8548          1       /* MPC8548 specific */
  37 #define CONFIG_MPC8548CDS       1       /* MPC8548CDS board specific */
  38
  39 #define CONFIG_PCI              /* enable any pci type devices */
  40 #define CONFIG_PCI1             /* PCI controller 1 */
  41 #define CONFIG_PCIE1            /* PCIE controler 1 (slot 1) */
  42 #undef CONFIG_RIO
  43 #undef CONFIG_PCI2
  44 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  45 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  46
  47 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  48 #define CONFIG_ENV_OVERWRITE
  49 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  50 #define CONFIG_DDR_DLL                  /* possible DLL fix needed */
  51 #undef CONFIG_DDR_2T_TIMING             /* Sets the 2T timing bit */
  52
  53 #define CONFIG_DDR_ECC                  /* only for ECC DDR module */
  54 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  55 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  56 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  57
  58 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  59
  60 #define CONFIG_FSL_VIA
  61 #define CONFIG_FSL_CDS_EEPROM
  62
  63 /*
  64  * When initializing flash, if we cannot find the manufacturer ID,
  65  * assume this is the AMD flash associated with the CDS board.
  66  * This allows booting from a promjet.
  67  */
  68 #define CONFIG_ASSUME_AMD_FLASH
  69
  70 #define MPC85xx_DDR_SDRAM_CLK_CNTL      /* 85xx has clock control reg */
  71
  72 #ifndef __ASSEMBLY__
  73 extern unsigned long get_clock_freq(void);
  74 #endif
  75 #define CONFIG_SYS_CLK_FREQ     get_clock_freq() /* sysclk for MPC85xx */
  76
  77 /*
  78  * These can be toggled for performance analysis, otherwise use default.
  79  */
  80 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  81 #define CONFIG_BTB                      /* toggle branch predition */
  82 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
  83 #define CONFIG_CLEAR_LAW0               /* Clear LAW0 in cpu_init_r */
  84
  85 /*
  86  * Only possible on E500 Version 2 or newer cores.
  87  */
  88 #define CONFIG_ENABLE_36BIT_PHYS        1
  89
  90 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  91
  92 #undef  CFG_DRAM_TEST                   /* memory test, takes time */
  93 #define CFG_MEMTEST_START       0x00200000      /* memtest works on */
  94 #define CFG_MEMTEST_END         0x00400000
  95
  96 /*
  97  * Base addresses -- Note these are effective addresses where the
  98  * actual resources get mapped (not physical addresses)
  99  */
 100 #define CFG_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default */
 101 #define CFG_CCSRBAR             0xe0000000      /* relocated CCSRBAR */
 102 #define CFG_CCSRBAR_PHYS        CFG_CCSRBAR     /* physical addr of CCSRBAR */
 103 #define CFG_IMMR                CFG_CCSRBAR     /* PQII uses CFG_IMMR */
 104
 105 #define CFG_PCI1_ADDR   (CFG_CCSRBAR+0x8000)
 106 #define CFG_PCI2_ADDR   (CFG_CCSRBAR+0x9000)
 107 #define CFG_PCIE1_ADDR  (CFG_CCSRBAR+0xa000)
 108
 109 /*
 110  * DDR Setup
 111  */
 112 #define CFG_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory*/
 113 #define CFG_SDRAM_BASE          CFG_DDR_SDRAM_BASE
 114
 115 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
 116
 117 /*
 118  * Make sure required options are set
 119  */
 120 #ifndef CONFIG_SPD_EEPROM
 121 #error ("CONFIG_SPD_EEPROM is required")
 122 #endif
 123
 124 #undef CONFIG_CLOCKS_IN_MHZ
 125
 126 /*
 127  * Local Bus Definitions
 128  */
 129
 130 /*
 131  * FLASH on the Local Bus
 132  * Two banks, 8M each, using the CFI driver.
 133  * Boot from BR0/OR0 bank at 0xff00_0000
 134  * Alternate BR1/OR1 bank at 0xff80_0000
 135  *
 136  * BR0, BR1:
 137  *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
 138  *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
 139  *    Port Size = 16 bits = BRx[19:20] = 10
 140  *    Use GPCM = BRx[24:26] = 000
 141  *    Valid = BRx[31] = 1
 142  *
 143  * 0    4    8    12   16   20   24   28
 144  * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
 145  * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
 146  *
 147  * OR0, OR1:
 148  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 149  *    Reserved ORx[17:18] = 11, confusion here?
 150  *    CSNT = ORx[20] = 1
 151  *    ACS = half cycle delay = ORx[21:22] = 11
 152  *    SCY = 6 = ORx[24:27] = 0110
 153  *    TRLX = use relaxed timing = ORx[29] = 1
 154  *    EAD = use external address latch delay = OR[31] = 1
 155  *
 156  * 0    4    8    12   16   20   24   28
 157  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 158  */
 159
 160 #define CFG_BOOT_BLOCK          0xff000000      /* boot TLB block */
 161 #define CFG_FLASH_BASE          CFG_BOOT_BLOCK  /* start of FLASH 16M */
 162
 163 #define CFG_BR0_PRELIM          0xff801001
 164 #define CFG_BR1_PRELIM          0xff001001
 165
 166 #define CFG_OR0_PRELIM          0xff806e65
 167 #define CFG_OR1_PRELIM          0xff806e65
 168
 169 #define CFG_FLASH_BANKS_LIST    {0xff800000, CFG_FLASH_BASE}
 170 #define CFG_MAX_FLASH_BANKS     2               /* number of banks */
 171 #define CFG_MAX_FLASH_SECT      128             /* sectors per device */
 172 #undef  CFG_FLASH_CHECKSUM
 173 #define CFG_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
 174 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
 175
 176 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor */
 177
 178 #define CFG_FLASH_CFI_DRIVER
 179 #define CFG_FLASH_CFI
 180 #define CFG_FLASH_EMPTY_INFO
 181
 182
 183 /*
 184  * SDRAM on the Local Bus
 185  */
 186 #define CFG_LBC_CACHE_BASE      0xf0000000      /* Localbus cacheable */
 187 #define CFG_LBC_CACHE_SIZE      64
 188 #define CFG_LBC_NONCACHE_BASE   0xf8000000      /* Localbus non-cacheable */
 189 #define CFG_LBC_NONCACHE_SIZE   64
 190
 191 #define CFG_LBC_SDRAM_BASE      CFG_LBC_CACHE_BASE      /* Localbus SDRAM */
 192 #define CFG_LBC_SDRAM_SIZE      64              /* LBC SDRAM is 64MB */
 193
 194 /*
 195  * Base Register 2 and Option Register 2 configure SDRAM.
 196  * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
 197  *
 198  * For BR2, need:
 199  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 200  *    port-size = 32-bits = BR2[19:20] = 11
 201  *    no parity checking = BR2[21:22] = 00
 202  *    SDRAM for MSEL = BR2[24:26] = 011
 203  *    Valid = BR[31] = 1
 204  *
 205  * 0    4    8    12   16   20   24   28
 206  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 207  *
 208  * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
 209  * FIXME: the top 17 bits of BR2.
 210  */
 211
 212 #define CFG_BR2_PRELIM          0xf0001861
 213
 214 /*
 215  * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
 216  *
 217  * For OR2, need:
 218  *    64MB mask for AM, OR2[0:7] = 1111 1100
 219  *                 XAM, OR2[17:18] = 11
 220  *    9 columns OR2[19-21] = 010
 221  *    13 rows   OR2[23-25] = 100
 222  *    EAD set for extra time OR[31] = 1
 223  *
 224  * 0    4    8    12   16   20   24   28
 225  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 226  */
 227
 228 #define CFG_OR2_PRELIM          0xfc006901
 229
 230 #define CFG_LBC_LCRR            0x00030004      /* LB clock ratio reg */
 231 #define CFG_LBC_LBCR            0x00000000      /* LB config reg */
 232 #define CFG_LBC_LSRT            0x20000000      /* LB sdram refresh timer */
 233 #define CFG_LBC_MRTPR           0x00000000      /* LB refresh timer prescal*/
 234
 235 /*
 236  * LSDMR masks
 237  */
 238 #define CFG_LBC_LSDMR_RFEN      (1 << (31 -  1))
 239 #define CFG_LBC_LSDMR_BSMA1516  (3 << (31 - 10))
 240 #define CFG_LBC_LSDMR_BSMA1617  (4 << (31 - 10))
 241 #define CFG_LBC_LSDMR_RFCR16    (7 << (31 - 16))
 242 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
 243 #define CFG_LBC_LSDMR_ACTTORW7  (7 << (31 - 22))
 244 #define CFG_LBC_LSDMR_ACTTORW6  (6 << (31 - 22))
 245 #define CFG_LBC_LSDMR_BL8       (1 << (31 - 23))
 246 #define CFG_LBC_LSDMR_WRC4      (0 << (31 - 27))
 247 #define CFG_LBC_LSDMR_CL3       (3 << (31 - 31))
 248
 249 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
 250 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
 251 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
 252 #define CFG_LBC_LSDMR_OP_MRW    (3 << (31 - 4))
 253 #define CFG_LBC_LSDMR_OP_PRECH  (4 << (31 - 4))
 254 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
 255 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
 256 #define CFG_LBC_LSDMR_OP_RWINV  (7 << (31 - 4))
 257
 258 /*
 259  * Common settings for all Local Bus SDRAM commands.
 260  * At run time, either BSMA1516 (for CPU 1.1)
 261  *                  or BSMA1617 (for CPU 1.0) (old)
 262  * is OR'ed in too.
 263  */
 264 #define CFG_LBC_LSDMR_COMMON    ( CFG_LBC_LSDMR_RFCR16          \
 265                                 | CFG_LBC_LSDMR_PRETOACT7       \
 266                                 | CFG_LBC_LSDMR_ACTTORW7        \
 267                                 | CFG_LBC_LSDMR_BL8             \
 268                                 | CFG_LBC_LSDMR_WRC4            \
 269                                 | CFG_LBC_LSDMR_CL3             \
 270                                 | CFG_LBC_LSDMR_RFEN            \
 271                                 )
 272
 273 /*
 274  * The CADMUS registers are connected to CS3 on CDS.
 275  * The new memory map places CADMUS at 0xf8000000.
 276  *
 277  * For BR3, need:
 278  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 279  *    port-size = 8-bits  = BR[19:20] = 01
 280  *    no parity checking  = BR[21:22] = 00
 281  *    GPMC for MSEL       = BR[24:26] = 000
 282  *    Valid               = BR[31]    = 1
 283  *
 284  * 0    4    8    12   16   20   24   28
 285  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 286  *
 287  * For OR3, need:
 288  *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 289  *    disable buffer ctrl OR[19]    = 0
 290  *    CSNT                OR[20]    = 1
 291  *    ACS                 OR[21:22] = 11
 292  *    XACS                OR[23]    = 1
 293  *    SCY 15 wait states  OR[24:27] = 1111      max is suboptimal but safe
 294  *    SETA                OR[28]    = 0
 295  *    TRLX                OR[29]    = 1
 296  *    EHTR                OR[30]    = 1
 297  *    EAD extra time      OR[31]    = 1
 298  *
 299  * 0    4    8    12   16   20   24   28
 300  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 301  */
 302
 303 #define CONFIG_FSL_CADMUS
 304
 305 #define CADMUS_BASE_ADDR 0xf8000000
 306 #define CFG_BR3_PRELIM   0xf8000801
 307 #define CFG_OR3_PRELIM   0xfff00ff7
 308
 309 #define CONFIG_L1_INIT_RAM
 310 #define CFG_INIT_RAM_LOCK       1
 311 #define CFG_INIT_RAM_ADDR       0xe4010000      /* Initial RAM address */
 312 #define CFG_INIT_RAM_END        0x4000          /* End of used area in RAM */
 313
 314 #define CFG_INIT_L2_ADDR        0xf8f80000      /* relocate boot L2SRAM */
 315
 316 #define CFG_GBL_DATA_SIZE       128             /* num bytes initial data */
 317 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 318 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 319
 320 #define CFG_MONITOR_LEN         (256 * 1024) /* Reserve 256 kB for Mon */
 321 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserved for malloc */
 322
 323 /* Serial Port */
 324 #define CONFIG_CONS_INDEX       2
 325 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 326 #define CFG_NS16550
 327 #define CFG_NS16550_SERIAL
 328 #define CFG_NS16550_REG_SIZE    1
 329 #define CFG_NS16550_CLK         get_bus_freq(0)
 330
 331 #define CFG_BAUDRATE_TABLE \
 332         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 333
 334 #define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
 335 #define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
 336
 337 /* Use the HUSH parser */
 338 #define CFG_HUSH_PARSER
 339 #ifdef  CFG_HUSH_PARSER
 340 #define CFG_PROMPT_HUSH_PS2 "> "
 341 #endif
 342
 343 /* pass open firmware flat tree */
 344 #define CONFIG_OF_LIBFDT                1
 345 #define CONFIG_OF_BOARD_SETUP           1
 346 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 347
 348 /*
 349  * I2C
 350  */
 351 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 352 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 353 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 354 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 355 #define CFG_I2C_EEPROM_ADDR     0x57
 356 #define CFG_I2C_SLAVE           0x7F
 357 #define CFG_I2C_NOPROBES        {0x69}  /* Don't probe these addrs */
 358 #define CFG_I2C_OFFSET          0x3000
 359
 360 /*
 361  * General PCI
 362  * Memory space is mapped 1-1, but I/O space must start from 0.
 363  */
 364 #define CFG_PCI_PHYS            0x80000000      /* 1G PCI TLB */
 365
 366 #define CFG_PCI1_MEM_BASE       0x80000000
 367 #define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
 368 #define CFG_PCI1_MEM_SIZE       0x20000000      /* 512M */
 369 #define CFG_PCI1_IO_BASE        0x00000000
 370 #define CFG_PCI1_IO_PHYS        0xe2000000
 371 #define CFG_PCI1_IO_SIZE        0x00100000      /* 1M */
 372
 373 #ifdef CONFIG_PCI2
 374 #define CFG_PCI2_MEM_BASE       0xa0000000
 375 #define CFG_PCI2_MEM_PHYS       CFG_PCI2_MEM_BASE
 376 #define CFG_PCI2_MEM_SIZE       0x20000000      /* 512M */
 377 #define CFG_PCI2_IO_BASE        0x00000000
 378 #define CFG_PCI2_IO_PHYS        0xe2800000
 379 #define CFG_PCI2_IO_SIZE        0x00100000      /* 1M */
 380 #endif
 381
 382 #ifdef CONFIG_PCIE1
 383 #define CFG_PCIE1_MEM_BASE      0xa0000000
 384 #define CFG_PCIE1_MEM_PHYS      CFG_PCIE1_MEM_BASE
 385 #define CFG_PCIE1_MEM_SIZE      0x20000000      /* 512M */
 386 #define CFG_PCIE1_IO_BASE       0x00000000
 387 #define CFG_PCIE1_IO_PHYS       0xe3000000
 388 #define CFG_PCIE1_IO_SIZE       0x00100000      /*   1M */
 389 #endif
 390
 391 #ifdef CONFIG_RIO
 392 /*
 393  * RapidIO MMU
 394  */
 395 #define CFG_RIO_MEM_BASE        0xC0000000
 396 #define CFG_RIO_MEM_SIZE        0x20000000      /* 512M */
 397 #endif
 398
 399 #ifdef CONFIG_LEGACY
 400 #define BRIDGE_ID 17
 401 #define VIA_ID 2
 402 #else
 403 #define BRIDGE_ID 28
 404 #define VIA_ID 4
 405 #endif
 406
 407 #if defined(CONFIG_PCI)
 408
 409 #define CONFIG_NET_MULTI
 410 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 411
 412 #undef CONFIG_EEPRO100
 413 #undef CONFIG_TULIP
 414
 415 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 416
 417 /* PCI view of System Memory */
 418 #define CFG_PCI_MEMORY_BUS      0x00000000
 419 #define CFG_PCI_MEMORY_PHYS     0x00000000
 420 #define CFG_PCI_MEMORY_SIZE     0x80000000
 421
 422 #endif  /* CONFIG_PCI */
 423
 424
 425 #if defined(CONFIG_TSEC_ENET)
 426
 427 #ifndef CONFIG_NET_MULTI
 428 #define CONFIG_NET_MULTI        1
 429 #endif
 430
 431 #define CONFIG_MII              1       /* MII PHY management */
 432 #define CONFIG_TSEC1    1
 433 #define CONFIG_TSEC1_NAME       "eTSEC0"
 434 #define CONFIG_TSEC2    1
 435 #define CONFIG_TSEC2_NAME       "eTSEC1"
 436 #define CONFIG_TSEC3    1
 437 #define CONFIG_TSEC3_NAME       "eTSEC2"
 438 #define CONFIG_TSEC4
 439 #define CONFIG_TSEC4_NAME       "eTSEC3"
 440 #undef CONFIG_MPC85XX_FEC
 441
 442 #define TSEC1_PHY_ADDR          0
 443 #define TSEC2_PHY_ADDR          1
 444 #define TSEC3_PHY_ADDR          2
 445 #define TSEC4_PHY_ADDR          3
 446
 447 #define TSEC1_PHYIDX            0
 448 #define TSEC2_PHYIDX            0
 449 #define TSEC3_PHYIDX            0
 450 #define TSEC4_PHYIDX            0
 451 #define TSEC1_FLAGS             TSEC_GIGABIT
 452 #define TSEC2_FLAGS             TSEC_GIGABIT
 453 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 454 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 455
 456 /* Options are: eTSEC[0-3] */
 457 #define CONFIG_ETHPRIME         "eTSEC0"
 458 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 459 #endif  /* CONFIG_TSEC_ENET */
 460
 461 /*
 462  * Environment
 463  */
 464 #define CFG_ENV_IS_IN_FLASH     1
 465 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + 0x40000)
 466 #define CFG_ENV_SECT_SIZE       0x40000 /* 256K(one sector) for env */
 467 #define CFG_ENV_SIZE            0x2000
 468
 469 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 470 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 471
 472 /*
 473  * BOOTP options
 474  */
 475 #define CONFIG_BOOTP_BOOTFILESIZE
 476 #define CONFIG_BOOTP_BOOTPATH
 477 #define CONFIG_BOOTP_GATEWAY
 478 #define CONFIG_BOOTP_HOSTNAME
 479
 480
 481 /*
 482  * Command line configuration.
 483  */
 484 #include <config_cmd_default.h>
 485
 486 #define CONFIG_CMD_PING
 487 #define CONFIG_CMD_I2C
 488 #define CONFIG_CMD_MII
 489 #define CONFIG_CMD_ELF
 490
 491 #if defined(CONFIG_PCI)
 492     #define CONFIG_CMD_PCI
 493 #endif
 494
 495
 496 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 497
 498 /*
 499  * Miscellaneous configurable options
 500  */
 501 #define CFG_LONGHELP                    /* undef to save memory */
 502 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 503 #define CFG_LOAD_ADDR   0x2000000       /* default load address */
 504 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt */
 505 #if defined(CONFIG_CMD_KGDB)
 506 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size */
 507 #else
 508 #define CFG_CBSIZE      256             /* Console I/O Buffer Size */
 509 #endif
 510 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 511 #define CFG_MAXARGS     16              /* max number of command args */
 512 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 513 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 514
 515 /*
 516  * For booting Linux, the board info and command line data
 517  * have to be in the first 8 MB of memory, since this is
 518  * the maximum mapped by the Linux kernel during initialization.
 519  */
 520 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux*/
 521
 522 /*
 523  * Internal Definitions
 524  *
 525  * Boot Flags
 526  */
 527 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 528 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 529
 530 #if defined(CONFIG_CMD_KGDB)
 531 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 532 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 533 #endif
 534
 535 /*
 536  * Environment Configuration
 537  */
 538
 539 /* The mac addresses for all ethernet interface */
 540 #if defined(CONFIG_TSEC_ENET)
 541 #define CONFIG_HAS_ETH0
 542 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
 543 #define CONFIG_HAS_ETH1
 544 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 545 #define CONFIG_HAS_ETH2
 546 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 547 #define CONFIG_HAS_ETH3
 548 #define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
 549 #endif
 550
 551 #define CONFIG_IPADDR    192.168.1.253
 552
 553 #define CONFIG_HOSTNAME  unknown
 554 #define CONFIG_ROOTPATH  /nfsroot
 555 #define CONFIG_BOOTFILE 8548cds/uImage.uboot
 556 #define CONFIG_UBOOTPATH        8548cds/u-boot.bin      /* TFTP server */
 557
 558 #define CONFIG_SERVERIP  192.168.1.1
 559 #define CONFIG_GATEWAYIP 192.168.1.1
 560 #define CONFIG_NETMASK   255.255.255.0
 561
 562 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
 563
 564 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 565 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs*/
 566
 567 #define CONFIG_BAUDRATE 115200
 568
 569 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 570  "netdev=eth0\0"                                                \
 571  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                         \
 572  "tftpflash=tftpboot $loadaddr $uboot; "                        \
 573         "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 574         "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 575         "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 576         "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 577         "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 578  "consoledev=ttyS1\0"                           \
 579  "ramdiskaddr=2000000\0"                        \
 580  "ramdiskfile=ramdisk.uboot\0"                  \
 581  "fdtaddr=c00000\0"                             \
 582  "fdtfile=mpc8548cds.dtb\0"
 583
 584 #define CONFIG_NFSBOOTCOMMAND                                           \
 585    "setenv bootargs root=/dev/nfs rw "                                  \
 586       "nfsroot=$serverip:$rootpath "                                    \
 587       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 588       "console=$consoledev,$baudrate $othbootargs;"                     \
 589    "tftp $loadaddr $bootfile;"                                          \
 590    "tftp $fdtaddr $fdtfile;"                                            \
 591    "bootm $loadaddr - $fdtaddr"
 592
 593
 594 #define CONFIG_RAMBOOTCOMMAND \
 595    "setenv bootargs root=/dev/ram rw "                                  \
 596       "console=$consoledev,$baudrate $othbootargs;"                     \
 597    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 598    "tftp $loadaddr $bootfile;"                                          \
 599    "tftp $fdtaddr $fdtfile;"                                            \
 600    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 601
 602 #define CONFIG_BOOTCOMMAND      CONFIG_NFSBOOTCOMMAND
 603
 604 #endif  /* __CONFIG_H */