include/configs/CPCI405DT.h

   1 /*
   2  * (C) Copyright 2001-2004
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  37 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  38 #define CONFIG_CPCI405          1       /* ...on a CPCI405 board        */
  39 #define CONFIG_CPCI405_VER2     1       /* ...version 2                 */
  40
  41 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  42
  43 #define CONFIG_SYS_CLK_FREQ     33330000 /* external frequency to pll   */
  44
  45 #define CONFIG_BAUDRATE         9600
  46 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  47
  48 #undef  CONFIG_BOOTARGS
  49 #undef  CONFIG_BOOTCOMMAND
  50
  51 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  52
  53 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  54 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
  55
  56 #define CONFIG_MII              1       /* MII PHY management           */
  57 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  58 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  59 #define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
  60
  61 #define CONFIG_NET_MULTI        1
  62 #undef  CONFIG_HAS_ETH1
  63
  64 #define CONFIG_RTC_M48T35A      1               /* ST Electronics M48 timekeeper */
  65
  66 /*
  67  * BOOTP options
  68  */
  69 #define CONFIG_BOOTP_SUBNETMASK
  70 #define CONFIG_BOOTP_GATEWAY
  71 #define CONFIG_BOOTP_HOSTNAME
  72 #define CONFIG_BOOTP_BOOTPATH
  73 #define CONFIG_BOOTP_DNS
  74 #define CONFIG_BOOTP_DNS2
  75 #define CONFIG_BOOTP_SEND_HOSTNAME
  76
  77
  78 /*
  79  * Command line configuration.
  80  */
  81 #include <config_cmd_default.h>
  82
  83 #define CONFIG_CMD_DHCP
  84 #define CONFIG_CMD_PCI
  85 #define CONFIG_CMD_IRQ
  86 #define CONFIG_CMD_IDE
  87 #define CONFIG_CMD_FAT
  88 #define CONFIG_CMD_ELF
  89 #define CONFIG_CMD_DATE
  90 #define CONFIG_CMD_JFFS2
  91 #define CONFIG_CMD_I2C
  92 #define CONFIG_CMD_MII
  93 #define CONFIG_CMD_PING
  94 #define CONFIG_CMD_BSP
  95 #define CONFIG_CMD_EEPROM
  96
  97
  98 #if 0 /* test-only */
  99 #define CONFIG_NETCONSOLE
 100 #define CONFIG_NET_MULTI
 101
 102 #ifdef CONFIG_NET_MULTI
 103 #define CONFIG_PHY1_ADDR        1       /* PHY address: for NetConsole  */
 104 #endif
 105 #endif
 106
 107 #define CONFIG_MAC_PARTITION
 108 #define CONFIG_DOS_PARTITION
 109
 110 #define CONFIG_SUPPORT_VFAT
 111
 112 #undef  CONFIG_AUTO_UPDATE              /* autoupdate via compactflash  */
 113
 114 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 115
 116 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
 117
 118 /*
 119  * Miscellaneous configurable options
 120  */
 121 #define CFG_LONGHELP                    /* undef to save memory         */
 122 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 123
 124 #undef  CFG_HUSH_PARSER                 /* use "hush" command parser    */
 125 #ifdef  CFG_HUSH_PARSER
 126 #define CFG_PROMPT_HUSH_PS2     "> "
 127 #endif
 128
 129 #if defined(CONFIG_CMD_KGDB)
 130 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 131 #else
 132 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 133 #endif
 134 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 135 #define CFG_MAXARGS     16              /* max number of command args   */
 136 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 137
 138 #define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
 139
 140 #define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
 141
 142 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
 143
 144 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 145 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 146
 147 #undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
 148 #define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
 149 #define CFG_BASE_BAUD       691200
 150
 151 /* The following table includes the supported baudrates */
 152 #define CFG_BAUDRATE_TABLE      \
 153         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 154          57600, 115200, 230400, 460800, 921600 }
 155
 156 #define CFG_LOAD_ADDR   0x100000        /* default load address */
 157 #define CFG_EXTBDINFO   1               /* To use extended board_into (bd_t) */
 158
 159 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 160
 161 #define CONFIG_LOOPW            1       /* enable loopw command         */
 162
 163 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 164
 165 /* Only interrupt boot if special string is typed */
 166 #define CONFIG_AUTOBOOT_KEYED 1
 167 #define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds\n"
 168 #undef  CONFIG_AUTOBOOT_DELAY_STR
 169 #undef  CONFIG_AUTOBOOT_STOP_STR        /* defined via environment var  */
 170 #define CONFIG_AUTOBOOT_STOP_STR2 "esdesd" /* esd special for esd access*/
 171
 172 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 173
 174 #define CFG_RX_ETH_BUFFER       16      /* use 16 rx buffer on 405 emac */
 175
 176 /*-----------------------------------------------------------------------
 177  * PCI stuff
 178  *-----------------------------------------------------------------------
 179  */
 180 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 181 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 182 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 183
 184 #define CONFIG_PCI                      /* include pci support          */
 185 #define CONFIG_PCI_HOST PCI_HOST_AUTO   /* select pci host function     */
 186 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 187                                         /* resource configuration       */
 188
 189 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 190
 191 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 192
 193 #define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 194
 195 #define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 196 #define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 197 #define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
 198 #define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 199 #define CFG_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
 200 #define CFG_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
 201 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 202 #define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
 203 #define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 204 #define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 205
 206 /*-----------------------------------------------------------------------
 207  * IDE/ATA stuff
 208  *-----------------------------------------------------------------------
 209  */
 210 #undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
 211 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 212 #define CONFIG_IDE_RESET        1       /* reset for ide supported      */
 213
 214 #define CFG_IDE_MAXBUS          1               /* max. 1 IDE busses    */
 215 #define CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 216
 217 #define CFG_ATA_BASE_ADDR       0xF0100000
 218 #define CFG_ATA_IDE0_OFFSET     0x0000
 219
 220 #define CFG_ATA_DATA_OFFSET     0x0000  /* Offset for data I/O                  */
 221 #define CFG_ATA_REG_OFFSET      0x0000  /* Offset for normal register accesses  */
 222 #define CFG_ATA_ALT_OFFSET      0x0000  /* Offset for alternate registers       */
 223
 224 /*-----------------------------------------------------------------------
 225  * Start addresses for the final memory configuration
 226  * (Set up by the startup code)
 227  * Please note that CFG_SDRAM_BASE _must_ start at 0
 228  */
 229 #define CFG_SDRAM_BASE          0x00000000
 230 #define CFG_FLASH_BASE          0xFFFC0000
 231 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 232 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Monitor   */
 233 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserve 128 kB for malloc()  */
 234
 235 /*
 236  * For booting Linux, the board info and command line data
 237  * have to be in the first 8 MB of memory, since this is
 238  * the maximum mapped by the Linux kernel during initialization.
 239  */
 240 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 241 /*-----------------------------------------------------------------------
 242  * FLASH organization
 243  */
 244 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 245 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 246
 247 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 248 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 249
 250 #define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
 251 #define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
 252 #define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
 253 /*
 254  * The following defines are added for buggy IOP480 byte interface.
 255  * All other boards should use the standard values (CPCI405 etc.)
 256  */
 257 #define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
 258 #define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
 259 #define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
 260
 261 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 262
 263 /*
 264  * JFFS2 partitions
 265  */
 266 /* No command line, one static partition */
 267 #undef CONFIG_JFFS2_CMDLINE
 268 #define CONFIG_JFFS2_DEV                "nor0"
 269 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 270 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 271
 272 /* mtdparts command line support */
 273
 274 /* Use first bank for JFFS2, second bank contains U-Boot.
 275  *
 276  * Note: fake mtd_id's used, no linux mtd map file.
 277  */
 278 /*
 279 #define CONFIG_JFFS2_CMDLINE
 280 #define MTDIDS_DEFAULT          "nor0=cpci405dt-0"
 281 #define MTDPARTS_DEFAULT        "mtdparts=cpci405dt-0:-(jffs2)"
 282 */
 283
 284 #if 0 /* Use NVRAM for environment variables */
 285 /*-----------------------------------------------------------------------
 286  * NVRAM organization
 287  */
 288 #define CFG_ENV_IS_IN_NVRAM     1       /* use NVRAM for environment vars       */
 289 #define CFG_ENV_SIZE            0x0ff8          /* Size of Environment vars     */
 290 #define CFG_ENV_ADDR            \
 291         (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8))   /* Env  */
 292
 293 #else /* Use EEPROM for environment variables */
 294
 295 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 296 #define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
 297 #define CFG_ENV_SIZE            0x800   /* 2048 bytes may be used for env vars*/
 298                                    /* total size of a CAT24WC16 is 2048 bytes */
 299 #endif
 300
 301 #define CFG_NVRAM_BASE_ADDR     0xf0200000              /* NVRAM base address   */
 302 #define CFG_NVRAM_SIZE          (32*1024)               /* NVRAM size           */
 303 #define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
 304
 305 /*-----------------------------------------------------------------------
 306  * I2C EEPROM (CAT24WC16) for environment
 307  */
 308 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 309 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 310 #define CFG_I2C_SLAVE           0x7F
 311
 312 #define CFG_I2C_EEPROM_ADDR     0x50    /* EEPROM CAT28WC08             */
 313 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address             */
 314 /* mask of address bits that overflow into the "EEPROM chip address"    */
 315 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x07
 316 #define CFG_EEPROM_PAGE_WRITE_BITS 4    /* The Catalyst CAT24WC08 has   */
 317                                         /* 16 byte page write mode using*/
 318                                         /* last 4 bits of the address   */
 319 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10   /* and takes up to 10 msec */
 320 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 321
 322 /*
 323  * Init Memory Controller:
 324  *
 325  * BR0/1 and OR0/1 (FLASH)
 326  */
 327
 328 #define FLASH_BASE0_PRELIM      0xFF800000      /* FLASH bank #0        */
 329 #define FLASH_BASE1_PRELIM      0xFFC00000      /* FLASH bank #1        */
 330
 331 /*-----------------------------------------------------------------------
 332  * External Bus Controller (EBC) Setup
 333  */
 334
 335 /* Memory Bank 0 (Flash Bank 0) initialization                                  */
 336 #define CFG_EBC_PB0AP           0x92015480
 337 #define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 338
 339 /* Memory Bank 1 (Flash Bank 1) initialization                                  */
 340 #define CFG_EBC_PB1AP           0x92015480
 341 #define CFG_EBC_PB1CR           0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 342
 343 /* Memory Bank 2 (CAN0, 1) initialization                                       */
 344 #define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 345 #define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 346 #define CFG_LED_ADDR            0xF0000380
 347
 348 /* Memory Bank 3 (CompactFlash IDE) initialization                              */
 349 #define CFG_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 350 #define CFG_EBC_PB3CR           0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 351
 352 /* Memory Bank 4 (NVRAM/RTC) initialization                                     */
 353 /*#define CFG_EBC_PB4AP           0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1     */
 354 #define CFG_EBC_PB4AP           0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1     */
 355 #define CFG_EBC_PB4CR           0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit  */
 356
 357 /* Memory Bank 5 (optional Quart) initialization                                */
 358 #define CFG_EBC_PB5AP           0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
 359 #define CFG_EBC_PB5CR           0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
 360
 361 /* Memory Bank 6 (FPGA internal) initialization                                 */
 362 #define CFG_EBC_PB6AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 363 #define CFG_EBC_PB6CR           0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 364 #define CFG_FPGA_BASE_ADDR      0xF0400000
 365
 366 /*-----------------------------------------------------------------------
 367  * FPGA stuff
 368  */
 369 /* FPGA internal regs */
 370 #define CFG_FPGA_MODE           0x00
 371 #define CFG_FPGA_STATUS         0x02
 372 #define CFG_FPGA_TS             0x04
 373 #define CFG_FPGA_TS_LOW         0x06
 374 #define CFG_FPGA_TS_CAP0        0x10
 375 #define CFG_FPGA_TS_CAP0_LOW    0x12
 376 #define CFG_FPGA_TS_CAP1        0x14
 377 #define CFG_FPGA_TS_CAP1_LOW    0x16
 378 #define CFG_FPGA_TS_CAP2        0x18
 379 #define CFG_FPGA_TS_CAP2_LOW    0x1a
 380 #define CFG_FPGA_TS_CAP3        0x1c
 381 #define CFG_FPGA_TS_CAP3_LOW    0x1e
 382
 383 /* FPGA Mode Reg */
 384 #define CFG_FPGA_MODE_CF_RESET      0x0001
 385 #define CFG_FPGA_MODE_DUART_RESET   0x0002
 386 #define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
 387 #define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
 388 #define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
 389 #define CFG_FPGA_MODE_TS_CLEAR      0x2000
 390
 391 /* FPGA Status Reg */
 392 #define CFG_FPGA_STATUS_DIP0    0x0001
 393 #define CFG_FPGA_STATUS_DIP1    0x0002
 394 #define CFG_FPGA_STATUS_DIP2    0x0004
 395 #define CFG_FPGA_STATUS_FLASH   0x0008
 396 #define CFG_FPGA_STATUS_TS_IRQ  0x1000
 397
 398 #define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
 399 #define CFG_FPGA_MAX_SIZE       32*1024     /* 32kByte is enough for XC2S15  */
 400
 401 /* FPGA program pin configuration */
 402 #define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
 403 #define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
 404 #define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
 405 #define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
 406 #define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
 407
 408 /*-----------------------------------------------------------------------
 409  * Definitions for initial stack pointer and data area (in data cache)
 410  */
 411 #define CFG_INIT_DCACHE_CS      7       /* use cs # 7 for data cache memory    */
 412
 413 #define CFG_INIT_RAM_ADDR       0x40000000  /* use data cache                  */
 414 #define CFG_INIT_RAM_END        0x2000  /* End of used area in RAM             */
 415 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 416 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 417 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 418
 419
 420 /*
 421  * Internal Definitions
 422  *
 423  * Boot Flags
 424  */
 425 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 426 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 427
 428 #endif  /* __CONFIG_H */