include/configs/BAB7xx.h

   1 /*
   2  * (C) Copyright 2002 ELTEC Elektronik AG
   3  * Frank Gottschling <fgottschling@eltec.de>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 #define GTREGREAD(x) 0xffffffff         /* needed for debug */
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37
  38 /* these hardware addresses are pretty bogus, please change them to
  39    suit your needs */
  40
  41 /* first ethernet */
  42 #define CONFIG_ETHADDR          00:00:5b:ee:de:ad
  43
  44 #define CONFIG_IPADDR           192.168.0.105
  45 #define CONFIG_SERVERIP         192.168.0.100
  46
  47 #define CONFIG_BAB7xx           1       /* this is an BAB740/BAB750 board */
  48
  49 #define CONFIG_BAUDRATE         9600    /* console baudrate */
  50
  51 #undef  CONFIG_WATCHDOG
  52
  53 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
  54
  55 #define CONFIG_ZERO_BOOTDELAY_CHECK
  56
  57 #undef  CONFIG_BOOTARGS
  58 #define CONFIG_BOOTCOMMAND                                  \
  59     "bootp 1000000; "                                       \
  60     "setenv bootargs root=ramfs console=ttyS00,9600 "       \
  61     "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:"    \
  62     "${netmask}:${hostname}:eth0:none; "                    \
  63     "bootm"
  64
  65 #define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
  66 #define CFG_LOADS_BAUD_CHANGE           /* allow baudrate changes */
  67
  68 /*
  69  * BOOTP options
  70  */
  71 #define CONFIG_BOOTP_SUBNETMASK
  72 #define CONFIG_BOOTP_GATEWAY
  73 #define CONFIG_BOOTP_HOSTNAME
  74 #define CONFIG_BOOTP_BOOTPATH
  75
  76 #define CONFIG_BOOTP_BOOTFILESIZE
  77
  78
  79 /*
  80  * Command line configuration.
  81  */
  82 #include <config_cmd_default.h>
  83
  84 #define CONFIG_CMD_PCI
  85 #define CONFIG_CMD_JFFS2
  86 #define CONFIG_CMD_SCSI
  87 #define CONFIG_CMD_IDE
  88 #define CONFIG_CMD_DATE
  89 #define CONFIG_CMD_FDC
  90 #define CONFIG_CMD_ELF
  91
  92
  93 /*
  94  * Miscellaneous configurable options
  95  */
  96 #define CFG_LONGHELP                    /* undef to save memory */
  97 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt */
  98
  99 /*
 100  * choose between COM1 and COM2 as serial console
 101  */
 102 #define CONFIG_CONS_INDEX       1
 103
 104 #if defined(CONFIG_CMD_KGDB)
 105 #define CFG_CBSIZE              1024        /* Console I/O Buffer Size */
 106 #else
 107 #define CFG_CBSIZE              256         /* Console I/O Buffer Size */
 108 #endif
 109 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 110 #define CFG_MAXARGS             16          /* max number of command args    */
 111 #define CFG_BARGSIZE            CFG_CBSIZE  /* Boot Argument Buffer Size    */
 112
 113 #define CFG_MEMTEST_START       0x00000000  /* memtest works on    */
 114 #define CFG_MEMTEST_END         0x04000000  /* 0 ... 64 MB in DRAM    */
 115
 116 #define CFG_LOAD_ADDR           0x1000000   /* default load address    */
 117
 118 #define CFG_HZ                  1000        /* dec. freq: 1 ms ticks */
 119
 120 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
 121
 122 /*
 123  * Low Level Configuration Settings
 124  * (address mappings, register initial values, etc.)
 125  * You should know what you are doing if you make changes here.
 126  */
 127 #define CFG_BOARD_ASM_INIT
 128 #define CONFIG_MISC_INIT_R
 129
 130 /*
 131  * Choose the address mapping scheme for the MPC106 mem controller.
 132  * Default is mapping B (CHRP), set this define to choose mapping A (PReP).
 133  */
 134 #define CFG_ADDRESS_MAP_A
 135 #ifdef  CFG_ADDRESS_MAP_A
 136
 137 #define CFG_PCI_MEMORY_BUS      0x80000000
 138 #define CFG_PCI_MEMORY_PHYS     0x00000000
 139 #define CFG_PCI_MEMORY_SIZE     0x80000000
 140
 141 #define CFG_PCI_MEM_BUS         0x00000000
 142 #define CFG_PCI_MEM_PHYS        0xc0000000
 143 #define CFG_PCI_MEM_SIZE        0x3f000000
 144
 145 #define CFG_ISA_MEM_BUS         0
 146 #define CFG_ISA_MEM_PHYS        0
 147 #define CFG_ISA_MEM_SIZE        0
 148
 149 #define CFG_PCI_IO_BUS          0x1000
 150 #define CFG_PCI_IO_PHYS         0x81000000
 151 #define CFG_PCI_IO_SIZE         0x01000000-CFG_PCI_IO_BUS
 152
 153 #define CFG_ISA_IO_BUS          0x00000000
 154 #define CFG_ISA_IO_PHYS         0x80000000
 155 #define CFG_ISA_IO_SIZE         0x00800000
 156
 157 #else
 158
 159 #define CFG_PCI_MEMORY_BUS      0x00000000
 160 #define CFG_PCI_MEMORY_PHYS     0x00000000
 161 #define CFG_PCI_MEMORY_SIZE     0x40000000
 162
 163 #define CFG_PCI_MEM_BUS         0x80000000
 164 #define CFG_PCI_MEM_PHYS        0x80000000
 165 #define CFG_PCI_MEM_SIZE        0x7d000000
 166
 167 #define CFG_ISA_MEM_BUS         0x00000000
 168 #define CFG_ISA_MEM_PHYS        0xfd000000
 169 #define CFG_ISA_MEM_SIZE        0x01000000
 170
 171 #define CFG_PCI_IO_BUS          0x00800000
 172 #define CFG_PCI_IO_PHYS         0xfe800000
 173 #define CFG_PCI_IO_SIZE         0x00400000
 174
 175 #define CFG_ISA_IO_BUS          0x00000000
 176 #define CFG_ISA_IO_PHYS         0xfe000000
 177 #define CFG_ISA_IO_SIZE         0x00800000
 178
 179 #endif /*CFG_ADDRESS_MAP_A */
 180
 181 #define CFG_60X_PCI_MEM_OFFSET  0x00000000
 182
 183 /* driver defines FDC,IDE,... */
 184 #define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
 185 #define CFG_ISA_IO              CFG_ISA_IO_PHYS
 186 #define CFG_60X_PCI_IO_OFFSET   CFG_ISA_IO_PHYS
 187
 188 /*
 189  * Start addresses for the final memory configuration
 190  * (Set up by the startup code)
 191  * Please note that CFG_SDRAM_BASE _must_ start at 0
 192  */
 193 #define CFG_SDRAM_BASE          0x00000000
 194 #define CFG_FLASH_BASE          0xfff00000
 195
 196 /*
 197  * Definitions for initial stack pointer and data area
 198  */
 199 #define CFG_INIT_RAM_ADDR       0x00fd0000  /* above the memtest region */
 200 #define CFG_INIT_RAM_END        0x4000
 201 #define CFG_GBL_DATA_SIZE       64          /* size in bytes reserved for init data */
 202 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 203 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 204
 205 /*
 206  * Flash mapping/organization on the MPC10x.
 207  */
 208 #define FLASH_BASE0_PRELIM      0xff800000
 209 #define FLASH_BASE1_PRELIM      0xffc00000
 210
 211 #define CFG_MAX_FLASH_BANKS     2           /* max number of memory banks    */
 212 #define CFG_MAX_FLASH_SECT      67          /* max number of sectors on one chip */
 213
 214 #define CFG_FLASH_ERASE_TOUT    120000      /* Timeout for Flash Erase (in ms) */
 215 #define CFG_FLASH_WRITE_TOUT    500         /* Timeout for Flash Write (in ms) */
 216
 217 /*
 218  * JFFS2 partitions
 219  *
 220  */
 221 /* No command line, one static partition */
 222 #undef CONFIG_JFFS2_CMDLINE
 223 #define CONFIG_JFFS2_DEV                "nor"
 224 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 225 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 226
 227 /* mtdparts command line support
 228  *
 229  * Note: fake mtd_id used, no linux mtd map file
 230  */
 231 /*
 232 #define CONFIG_JFFS2_CMDLINE
 233 #define MTDIDS_DEFAULT          "nor0=bab7xx-0"
 234 #define MTDPARTS_DEFAULT        "mtdparts=bab7xx-0:-(jffs2)"
 235 */
 236
 237 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 238 #define CFG_MONITOR_LEN         0x40000     /* Reserve 256 kB for Monitor */
 239 #define CFG_MALLOC_LEN          0x20000     /* Reserve 128 kB for malloc() */
 240 #undef  CFG_MEMTEST
 241
 242 /*
 243  * Environment settings
 244  */
 245 #define CONFIG_ENV_OVERWRITE
 246 #define CFG_ENV_IS_IN_NVRAM     1           /* use NVRAM for environment vars */
 247 #define CFG_NVRAM_SIZE          0x1ff0      /* NVRAM size (8kB), we must protect the clock data (16 bytes) */
 248 #define CFG_ENV_SIZE            0x400       /* Size of Environment vars (1kB) */
 249 /*
 250  * We store the environment and an image of revision eeprom in the upper part of the NVRAM. Thus,
 251  * user applications can use the remaining space for other purposes.
 252  */
 253 #define CFG_ENV_ADDR            (CFG_NVRAM_SIZE +0x10 -0x800)
 254 #define CFG_NV_SROM_COPY_ADDR   (CFG_NVRAM_SIZE +0x10 -0x400)
 255 #define CFG_NVRAM_ACCESS_ROUTINE            /* This board needs a special routine to access the NVRAM */
 256 #define CFG_SROM_SIZE           0x100       /* shadow of revision info is in nvram */
 257
 258 /*
 259  * Serial devices
 260  */
 261 #define CFG_NS16550
 262 #define CFG_NS16550_SERIAL
 263 #define CFG_NS16550_REG_SIZE    1
 264 #define CFG_NS16550_CLK         1843200
 265 #define CFG_NS16550_COM1        (CFG_ISA_IO + CFG_NS87308_UART1_BASE)
 266 #define CFG_NS16550_COM2        (CFG_ISA_IO + CFG_NS87308_UART2_BASE)
 267
 268 /*
 269  * PCI stuff
 270  */
 271 #define CONFIG_PCI                                /* include pci support */
 272 #define CONFIG_PCI_PNP                            /* pci plug-and-play */
 273 #define CONFIG_PCI_HOST         PCI_HOST_AUTO
 274 #undef  CONFIG_PCI_SCAN_SHOW
 275
 276 /*
 277  * Video console (graphic: SMI LynxEM, keyboard: i8042)
 278  */
 279 #define CONFIG_VIDEO
 280 #define CONFIG_CFB_CONSOLE
 281 #define CONFIG_VIDEO_SMI_LYNXEM
 282 #define CONFIG_I8042_KBD
 283 #define CONFIG_VIDEO_LOGO
 284 #define CONFIG_CONSOLE_TIME
 285 #define CONFIG_CONSOLE_EXTRA_INFO
 286 #define CONFIG_CONSOLE_CURSOR
 287 #define CFG_CONSOLE_BLINK_COUNT         30000    /* approx. 2 HZ */
 288
 289 /*
 290  * IDE/SCSI globals
 291  */
 292 #ifndef __ASSEMBLY__
 293 extern unsigned int    eltec_board;
 294 extern unsigned int    ata_reset_time;
 295 extern unsigned int    scsi_reset_time;
 296 extern unsigned short  scsi_dev_id;
 297 extern unsigned int    scsi_max_scsi_id;
 298 extern unsigned char   scsi_sym53c8xx_ccf;
 299 #endif
 300
 301 /*
 302  * ATAPI Support (experimental)
 303  */
 304 #define CONFIG_ATAPI
 305 #define CFG_IDE_MAXBUS          1                       /* max. 2 IDE busses    */
 306 #define CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS*2)      /* max. 2 drives per IDE bus */
 307
 308 #define CFG_ATA_BASE_ADDR       CFG_60X_PCI_IO_OFFSET   /* base address */
 309 #define CFG_ATA_IDE0_OFFSET     0x1F0                   /* default ide0 offste */
 310 #define CFG_ATA_IDE1_OFFSET     0x170                   /* default ide1 offset */
 311 #define CFG_ATA_DATA_OFFSET     0                       /* data reg offset    */
 312 #define CFG_ATA_REG_OFFSET      0                       /* reg offset */
 313 #define CFG_ATA_ALT_OFFSET      0x200                   /* alternate register offset */
 314
 315 #define ATA_RESET_TIME          (ata_reset_time)
 316
 317 #undef  CONFIG_IDE_PCMCIA                               /* no pcmcia interface required */
 318 #undef  CONFIG_IDE_LED                                  /* no led for ide supported */
 319
 320 /*
 321  * SCSI support (experimental) only SYM53C8xx supported
 322  */
 323 #define CONFIG_SCSI_SYM53C8XX
 324 #define CONFIG_SCSI_DEV_ID      (scsi_dev_id)           /* 875 or 860 */
 325 #define CFG_SCSI_SYM53C8XX_CCF  (scsi_sym53c8xx_ccf)    /* value for none 40 mhz clocks */
 326 #define CFG_SCSI_MAX_LUN        8                       /* number of supported LUNs */
 327 #define CFG_SCSI_MAX_SCSI_ID    (scsi_max_scsi_id)      /* max SCSI ID (0-6) */
 328 #define CFG_SCSI_MAX_DEVICE     (15 * CFG_SCSI_MAX_LUN) /* max. Target devices */
 329 #define CFG_SCSI_SPIN_UP_TIME   (scsi_reset_time)
 330
 331 /*
 332  * Partion suppport
 333  */
 334 #define CONFIG_DOS_PARTITION
 335 #define CONFIG_MAC_PARTITION
 336 #define CONFIG_ISO_PARTITION
 337
 338 /*
 339  * Winbond Configuration
 340  */
 341 #define CFG_WINBOND_83C553      1                       /* has a winbond bridge */
 342 #define CFG_USE_WINBOND_IDE     0                       /* use winbond 83c553 internal ide */
 343 #define CFG_WINBOND_ISA_CFG_ADDR    0x80005800          /* pci-isa bridge config addr */
 344 #define CFG_WINBOND_IDE_CFG_ADDR    0x80005900          /* ide config addr */
 345
 346 /*
 347  * NS87308 Configuration
 348  */
 349 #define CFG_NS87308                    /* Nat Semi super-io cntr on ISA bus */
 350 #define CFG_NS87308_BADDR_10    1
 351 #define CFG_NS87308_DEVS        (CFG_NS87308_UART1   | \
 352                                  CFG_NS87308_UART2   | \
 353                                  CFG_NS87308_KBC1    | \
 354                                  CFG_NS87308_MOUSE   | \
 355                                  CFG_NS87308_FDC     | \
 356                                  CFG_NS87308_RARP    | \
 357                                  CFG_NS87308_GPIO    | \
 358                                  CFG_NS87308_POWRMAN | \
 359                                  CFG_NS87308_RTC_APC )
 360
 361 #define CFG_NS87308_PS2MOD
 362 #define CFG_NS87308_GPIO_BASE   0x0220
 363 #define CFG_NS87308_PWMAN_BASE  0x0460
 364 #define CFG_NS87308_PMC2        0x00        /* SuperI/O clock source is 24MHz via X1 */
 365
 366 /*
 367  * set up the NVRAM access registers
 368  * NVRAM's controlled by the configurable CS line from the 87308
 369  */
 370 #define CFG_NS87308_CS0_BASE    0x0076
 371 #define CFG_NS87308_CS0_CONF    0x40
 372 #define CFG_NS87308_CS1_BASE    0x0070
 373 #define CFG_NS87308_CS1_CONF    0x1C
 374 #define CFG_NS87308_CS2_BASE    0x0071
 375 #define CFG_NS87308_CS2_CONF    0x1C
 376
 377 #define CONFIG_RTC_MK48T59
 378
 379 /*
 380  * Initial BATs
 381  */
 382 #if 1
 383
 384 #define CFG_IBAT0L 0
 385 #define CFG_IBAT0U 0
 386 #define CFG_DBAT0L CFG_IBAT1L
 387 #define CFG_DBAT0U CFG_IBAT1U
 388
 389 #define CFG_IBAT1L 0
 390 #define CFG_IBAT1U 0
 391 #define CFG_DBAT1L CFG_IBAT1L
 392 #define CFG_DBAT1U CFG_IBAT1U
 393
 394 #define CFG_IBAT2L 0
 395 #define CFG_IBAT2U 0
 396 #define CFG_DBAT2L CFG_IBAT2L
 397 #define CFG_DBAT2U CFG_IBAT2U
 398
 399 #define CFG_IBAT3L 0
 400 #define CFG_IBAT3U 0
 401 #define CFG_DBAT3L CFG_IBAT3L
 402 #define CFG_DBAT3U CFG_IBAT3U
 403
 404 #else
 405
 406 /* SDRAM */
 407 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_RW)
 408 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 409 #define CFG_DBAT0L CFG_IBAT1L
 410 #define CFG_DBAT0U CFG_IBAT1U
 411
 412 /* address range for flashes */
 413 #define CFG_IBAT1L (CFG_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
 414 #define CFG_IBAT1U (CFG_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
 415 #define CFG_DBAT1L CFG_IBAT1L
 416 #define CFG_DBAT1U CFG_IBAT1U
 417
 418 /* ISA IO space */
 419 #define CFG_IBAT2L (CFG_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
 420 #define CFG_IBAT2U (CFG_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
 421 #define CFG_DBAT2L CFG_IBAT2L
 422 #define CFG_DBAT2U CFG_IBAT2U
 423
 424 /* ISA memory space */
 425 #define CFG_IBAT3L (CFG_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
 426 #define CFG_IBAT3U (CFG_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
 427 #define CFG_DBAT3L CFG_IBAT3L
 428 #define CFG_DBAT3U CFG_IBAT3U
 429
 430 #endif
 431
 432 /*
 433  * Speed settings are board specific
 434  */
 435 #ifndef __ASSEMBLY__
 436 extern  unsigned long           bab7xx_get_bus_freq (void);
 437 extern  unsigned long           bab7xx_get_gclk_freq (void);
 438 #endif
 439 #define CFG_BUS_HZ              bab7xx_get_bus_freq()
 440 #define CFG_BUS_CLK             CFG_BUS_HZ
 441 #define CFG_CPU_CLK             bab7xx_get_gclk_freq()
 442
 443 /*
 444  * For booting Linux, the board info and command line data
 445  * have to be in the first 8 MB of memory, since this is
 446  * the maximum mapped by the Linux kernel during initialization.
 447  */
 448 #define CFG_BOOTMAPSZ           (8 << 20)           /* Initial Memory map for Linux */
 449
 450 /*
 451  * Cache Configuration
 452  */
 453 #define CFG_CACHELINE_SIZE        32    /* For all MPC74xx CPUs */
 454 #if defined(CONFIG_CMD_KGDB)
 455 #define CFG_CACHELINE_SHIFT        5    /* log base 2 of the above value */
 456 #endif
 457
 458 /*
 459  * L2 Cache Configuration is board specific for BAB740/BAB750
 460  * Init values read from revision srom.
 461  */
 462 #undef  CFG_L2
 463 #define L2_INIT     (L2CR_L2SIZ_HM | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
 464                      L2CR_L2OH_5   | L2CR_L2CTL   | L2CR_L2WT)
 465 #define L2_ENABLE   (L2_INIT | L2CR_L2E)
 466
 467 #define CFG_L2_BAB7xx
 468
 469 /*
 470  * Internal Definitions
 471  *
 472  * Boot Flags
 473  */
 474 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
 475 #define BOOTFLAG_WARM           0x02    /* Software reboot */
 476
 477
 478 #define CONFIG_NET_MULTI                /* Multi ethernet cards support */
 479 #define CONFIG_TULIP
 480 #define CONFIG_TULIP_SELECT_MEDIA
 481
 482 #endif    /* __CONFIG_H */