include/configs/AMX860.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC860           1
  37 #define CONFIG_AMX860           1
  38
  39 #undef  CONFIG_8xx_CONS_SMC1            /* Console is on SCC2           */
  40 #undef  CONFIG_8xx_CONS_SMC2
  41 #define CONFIG_8xx_CONS_SCC2    1
  42 #undef  CONFIG_8xx_CONS_NONE
  43 #define CONFIG_BAUDRATE         9600
  44 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  45
  46 #define MPC8XX_FACT             10              /* Multiply by 10       */
  47 #define MPC8XX_XIN              5000000                 /* 5 MHz in     */
  48 #define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
  49
  50 #if 0
  51 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  52 #else
  53 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  54 #endif
  55
  56 #define CONFIG_BOOTCOMMAND                                                      \
  57         "bootp;"                                                                \
  58         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  59         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"    \
  60         "bootm"                         /* autoboot command */
  61
  62 #undef CONFIG_BOOTARGS
  63
  64 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  65
  66 #define CONFIG_SCC1_ENET        1       /* use SCC1 ethernet */
  67
  68 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  69
  70
  71 /*
  72  * Command line configuration.
  73  */
  74 #include <config_cmd_default.h>
  75
  76 #define CONFIG_CMD_DHCP
  77 #define CONFIG_CMD_DATE
  78 #define CONFIG_CMD_NFS
  79 #define CONFIG_CMD_SNTP
  80
  81
  82 #if defined(CONFIG_CMD_KGDB)
  83 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
  84 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
  85 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
  86 #define CONFIG_KGDB_INDEX       1       /* which serial channel for kgdb */
  87 #define CONFIG_KGDB_BAUDRATE    9600    /* speed to run kgdb serial port at */
  88 #endif
  89
  90
  91 /*
  92  * BOOTP options
  93  */
  94 #define CONFIG_BOOTP_BOOTFILESIZE
  95 #define CONFIG_BOOTP_BOOTPATH
  96 #define CONFIG_BOOTP_GATEWAY
  97 #define CONFIG_BOOTP_HOSTNAME
  98 #define CONFIG_BOOTP_SUBNETMASK
  99
 100
 101 /*
 102  * Miscellaneous configurable options
 103  */
 104 #define CFG_LONGHELP                    /* undef to save memory         */
 105 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 106 #if defined(CONFIG_CMD_KGDB)
 107 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 108 #else
 109 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 110 #endif
 111 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 112 #define CFG_MAXARGS     16              /* max number of command args   */
 113 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 114
 115 #define CFG_MEMTEST_START       0x0100000       /* memtest works on     */
 116 #define CFG_MEMTEST_END         0x0200000       /* 1 ... 4 MB in DRAM   */
 117
 118 #define CFG_LOAD_ADDR           0x00100000
 119
 120 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 121
 122 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 123
 124 /*
 125  * Low Level Configuration Settings
 126  * (address mappings, register initial values, etc.)
 127  * You should know what you are doing if you make changes here.
 128  */
 129
 130 /*-----------------------------------------------------------------------
 131  * Internal Memory Mapped Register
 132  */
 133 #define CFG_IMMR                        0xFF000000
 134
 135 /*-----------------------------------------------------------------------
 136  * Definitions for initial stack pointer and data area (in DPRAM)
 137  */
 138 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 139 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 140 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 141 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 142 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 143
 144 /*-----------------------------------------------------------------------
 145  * Start addresses for the final memory configuration
 146  * (Set up by the startup code)
 147  * Please note that CFG_SDRAM_BASE _must_ start at 0
 148  */
 149 #define CFG_SDRAM_BASE          0x00000000
 150 #define CFG_FLASH_BASE          0x40000000
 151 #if defined(DEBUG)
 152 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 153 #else
 154 #define CFG_MONITOR_LEN         (192 << 10)     /* Reserve 192 kB for Monitor   */
 155 #endif
 156 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 157 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 158
 159 /*
 160  * U-Boot for AMX board supports two types of memory extension
 161  * modules: one that provides 4 MB flash memory, and another one with
 162  * 16 MB EDO DRAM.
 163  *
 164  * The flash module swaps the CS0 and CS1 signals: if the module is
 165  * installed, CS0 is connected to Flash on the module and CS1 is
 166  * connected to the on-board Flash. This means that you must intall
 167  * U-Boot when the Flash module is plugged in, if you plan to use
 168  * it.
 169  *
 170  * To enable support for the DRAM extension card, CONFIG_AMX_RAM_EXT
 171  * must be defined. The DRAM module uses CS1.
 172  *
 173  * Only one of these modules may be installed at a time. If U-Boot
 174  * is compiled with the CONFIG_AMX_RAM_EXT option set, it will not
 175  * work if the Flash extension module is installed instead of the
 176  * DRAM module.
 177  */
 178 #define CONFIG_AMX_RAM_EXT      /* 16Mb Ext. DRAM module support */
 179
 180 /*
 181  * For booting Linux, the board info and command line data
 182  * have to be in the first 8 MB of memory, since this is
 183  * the maximum mapped by the Linux kernel during initialization.
 184  *
 185  * Use 4 MB for without and 8 MB with 16 MB DRAM extension module
 186  * (CONFIG_AMX_RAM_EXT)
 187  */
 188 #ifdef CONFIG_AMX_RAM_EXT
 189 # define        CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux */
 190 #else
 191 # define        CFG_BOOTMAPSZ   (4 << 20)       /* Initial Memory map for Linux */
 192 #endif
 193 /*-----------------------------------------------------------------------
 194  * FLASH organization
 195  */
 196 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 197 #define CFG_MAX_FLASH_SECT      35      /* max number of sectors on one chip    */
 198
 199 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 200 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 201
 202 #define CFG_ENV_IS_IN_FLASH     1
 203 #define CFG_ENV_OFFSET          0x8000  /*   Offset   of Environment Sector     */
 204 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 205
 206 /*-----------------------------------------------------------------------
 207  * Cache Configuration
 208  */
 209 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 210 #if defined(CONFIG_CMD_KGDB)
 211 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 212 #endif
 213
 214 /*-----------------------------------------------------------------------
 215  * SYPCR - System Protection Control                                    11-9
 216  * SYPCR can only be written once after reset!
 217  *-----------------------------------------------------------------------
 218  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 219  */
 220 #if defined(CONFIG_WATCHDOG)
 221 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 222                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 223 #else
 224 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 225 #endif
 226
 227 /*-----------------------------------------------------------------------
 228  * SIUMCR - SIU Module Configuration                                    11-6
 229  *-----------------------------------------------------------------------
 230  * PCMCIA config., multi-function pin tri-state
 231  */
 232 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 233
 234 /*-----------------------------------------------------------------------
 235  * TBSCR - Time Base Status and Control                                 11-26
 236  *-----------------------------------------------------------------------
 237  * Clear Reference Interrupt Status, Timebase freezing enabled
 238  */
 239 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 240
 241 /*-----------------------------------------------------------------------
 242  * PISCR - Periodic Interrupt Status and Control                11-31
 243  *-----------------------------------------------------------------------
 244  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 245  */
 246 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 247
 248 /*-----------------------------------------------------------------------
 249  * PLPRCR - PLL, Low-Power, and Reset Control Register  15-30
 250  *-----------------------------------------------------------------------
 251  * set the PLL, the low-power modes and the reset control (15-29)
 252  */
 253 #define CFG_PLPRCR      (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
 254                                 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 255
 256 /*-----------------------------------------------------------------------
 257  * SCCR - System Clock and reset Control Register               15-27
 258  *-----------------------------------------------------------------------
 259  * Set clock output, timebase and RTC source and divider,
 260  * power management and some other internal clocks
 261  */
 262 #define SCCR_MASK       SCCR_EBDF11
 263 #define CFG_SCCR        (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
 264
 265 #define CFG_DER         0
 266
 267 /*
 268  * Init Memory Controller:
 269  *
 270  * BR0/1 and OR0/1 (FLASH)
 271  */
 272
 273 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 274 #ifndef CONFIG_AMX_RAM_EXT
 275 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #1        */
 276 #endif
 277
 278 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 279 #define CFG_PRELIM_OR_AM        0xFFC00000      /* OR addr mask */
 280
 281 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0        */
 282 /*                               0x00000800     0x00000400 0x00000100 0x00000030     0x00000004 */
 283 #define CFG_OR_TIMING_FLASH     (OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_TRLX)
 284
 285 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 286
 287 #define CFG_OR0_PRELIM  0xFFC00954      /* Real values for the board */
 288 #define CFG_BR0_PRELIM  0x40000001      /* Real values for the board */
 289
 290 #ifndef CONFIG_AMX_RAM_EXT
 291 #define CFG_OR1_REMAP   CFG_OR0_REMAP
 292 #define CFG_OR1_PRELIM  0xFFC00954      /* Real values for the board */
 293 #define CFG_BR1_PRELIM  0x60000001      /* Real values for the board */
 294 #endif
 295
 296 /* DSP ("Glue") Xilinx */
 297 #define CFG_OR6_PRELIM  0xFFFF8000      /* 32kB, 15 waits, cs after addr, no bursts */
 298 #define CFG_BR6_PRELIM  0x60000401      /* use GPCM for CS generation, 8 bit port */
 299
 300 /*
 301  * Internal Definitions
 302  *
 303  * Boot Flags
 304  */
 305 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 306 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 307
 308 #endif  /* __CONFIG_H */