cpu/mpc824x/cpu_init.c

   1 /*
   2  * (C) Copyright 2000
   3  * Rob Taylor. Flying Pig Systems. robt@flyingpig.com.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/processor.h>
  26 #include <mpc824x.h>
  27
  28 #ifndef CFG_BANK0_ROW
  29 #define CFG_BANK0_ROW 0
  30 #endif
  31 #ifndef CFG_BANK1_ROW
  32 #define CFG_BANK1_ROW 0
  33 #endif
  34 #ifndef CFG_BANK2_ROW
  35 #define CFG_BANK2_ROW 0
  36 #endif
  37 #ifndef CFG_BANK3_ROW
  38 #define CFG_BANK3_ROW 0
  39 #endif
  40 #ifndef CFG_BANK4_ROW
  41 #define CFG_BANK4_ROW 0
  42 #endif
  43 #ifndef CFG_BANK5_ROW
  44 #define CFG_BANK5_ROW 0
  45 #endif
  46 #ifndef CFG_BANK6_ROW
  47 #define CFG_BANK6_ROW 0
  48 #endif
  49 #ifndef CFG_BANK7_ROW
  50 #define CFG_BANK7_ROW 0
  51 #endif
  52 #ifndef CFG_DBUS_SIZE2
  53 #define CFG_DBUS_SIZE2 0
  54 #endif
  55
  56 /*
  57  * Breath some life into the CPU...
  58  *
  59  * Set up the memory map,
  60  * initialize a bunch of registers,
  61  */
  62 void
  63 cpu_init_f (void)
  64 {
  65 /* MOUSSE board is initialized in asm */
  66 #if !defined(CONFIG_MOUSSE) && !defined(CONFIG_BMW)
  67     register unsigned long val;
  68     CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
  69 /*    CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/
  70
  71 #if defined(CONFIG_MUSENKI) || defined(CONFIG_PN62)
  72 /* Why is this here, you ask?  Try, just try setting 0x8000
  73  * in PCIACR with CONFIG_WRITE_HALFWORD()
  74  * this one was a stumper, and we are annoyed
  75  */
  76
  77 #define M_CONFIG_WRITE_HALFWORD( addr, data ) \
  78         __asm__ __volatile__("          \
  79                 stw  %2,0(%0)\n         \
  80                 sync\n                  \
  81                 sth  %3,2(%1)\n         \
  82                 sync\n                  \
  83                 "                       \
  84                 : /* no output */       \
  85                 : "r" (CONFIG_ADDR), "r" (CONFIG_DATA),                 \
  86                 "r" (PCISWAP(addr & ~3)), "r" (PCISWAP(data << 16))     \
  87         );
  88
  89         M_CONFIG_WRITE_HALFWORD(PCIACR, 0x8000);
  90 #endif
  91
  92         CONFIG_WRITE_BYTE(PCLSR, 0x8);  /* set PCI cache line size */
  93         CONFIG_WRITE_BYTE (PLTR, 0x40); /* set PCI latency timer */
  94         /*
  95         * Note that although this bit is cleared after a hard reset, it
  96         * must be explicitly set and then cleared by software during
  97         * initialization in order to guarantee correct operation of the
  98         * DLL and the SDRAM_CLK[0:3] signals (if they are used).
  99         */
 100         CONFIG_READ_BYTE (AMBOR, val);
 101         CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
 102         CONFIG_WRITE_BYTE(AMBOR, val | 0x20);
 103         CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
 104 #ifdef CONFIG_MPC8245
 105         /* silicon bug 28 MPC8245 */
 106         CONFIG_READ_BYTE(AMBOR,val);
 107         CONFIG_WRITE_BYTE(AMBOR,val|0x1);
 108
 109 #if 0
 110         /*
 111          * The following bug only affects older (XPC8245) processors.
 112          * DMA transfers initiated by external devices get corrupted due
 113          * to a hardware scheduling problem.
 114          *
 115          * The effect is:
 116          * when transferring X words, the first 32 words are transferred
 117          * OK, the next 3 x 32 words are 'old' data (from previous DMA)
 118          * while the rest of the X words is xferred fine.
 119          *
 120          * Disabling 3 of the 4 32 word hardware buffers solves the problem
 121          * with no significant performance loss.
 122          */
 123
 124         CONFIG_READ_BYTE(PCMBCR,val);
 125         /* in order not to corrupt data which is being read over the PCI bus
 126         * with the PPC as slave, we need to reduce the number of PCMRBs to 1,
 127         * 4.11 in the  processor user manual
 128         * */
 129
 130 #if 1
 131         CONFIG_WRITE_BYTE(PCMBCR,(val|0xC0)); /* 1 PCMRB */
 132 #else
 133         CONFIG_WRITE_BYTE(PCMBCR,(val|0x80)); /* 2 PCMRBs */
 134         CONFIG_WRITE_BYTE(PCMBCR,(val|0x40)); /* 3 PCMRBs */
 135         /* default, 4 PCMRBs are used */
 136 #endif
 137 #endif
 138 #endif
 139
 140         CONFIG_READ_WORD(PICR1, val);
 141 #if defined(CONFIG_MPC8240)
 142         CONFIG_WRITE_WORD( PICR1,
 143                 (val & (PICR1_ADDRESS_MAP | PICR1_RCS0)) |
 144                        PIRC1_MSK | PICR1_PROC_TYPE_603E |
 145                        PICR1_FLASH_WR_EN | PICR1_MCP_EN |
 146                        PICR1_CF_DPARK | PICR1_EN_PCS |
 147                        PICR1_CF_APARK );
 148 #elif defined(CONFIG_MPC8245)
 149         CONFIG_WRITE_WORD( PICR1,
 150                 (val & (PICR1_RCS0)) |
 151                        PICR1_PROC_TYPE_603E |
 152                        PICR1_FLASH_WR_EN | PICR1_MCP_EN |
 153                        PICR1_CF_DPARK | PICR1_NO_BUSW_CK |
 154                        PICR1_DEC| PICR1_CF_APARK | 0x10); /* 8245 UM says bit 4 must be set */
 155 #else
 156 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
 157 #endif
 158
 159         CONFIG_READ_WORD(PICR2, val);
 160         val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/
 161 #ifndef CONFIG_PN62
 162         val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/
 163 #endif
 164         CONFIG_WRITE_WORD(PICR2, val);
 165
 166         CONFIG_WRITE_WORD(EUMBBAR, CFG_EUMB_ADDR);
 167 #ifndef CFG_RAMBOOT
 168         CONFIG_WRITE_WORD(MCCR1, (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) |
 169                                  (CFG_BANK0_ROW) |
 170                                  (CFG_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) |
 171                                  (CFG_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) |
 172                                  (CFG_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) |
 173                                  (CFG_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) |
 174                                  (CFG_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) |
 175                                  (CFG_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) |
 176                                  (CFG_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) |
 177                                  (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT));
 178 #endif
 179
 180 #if defined(CFG_ASRISE) && defined(CFG_ASFALL)
 181         CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT |
 182                                  CFG_ASRISE << MCCR2_ASRISE_SHIFT |
 183                                  CFG_ASFALL << MCCR2_ASFALL_SHIFT);
 184 #else
 185         CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT);
 186 #endif
 187
 188 #if defined(CONFIG_MPC8240)
 189         CONFIG_WRITE_WORD(MCCR3,
 190                 (((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
 191                 (CFG_REFREC << MCCR3_REFREC_SHIFT) |
 192                 (CFG_RDLAT  << MCCR3_RDLAT_SHIFT));
 193 #elif defined(CONFIG_MPC8245)
 194         CONFIG_WRITE_WORD(MCCR3,
 195                 (((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
 196                 (CFG_REFREC << MCCR3_REFREC_SHIFT));
 197 #else
 198 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
 199 #endif
 200
 201 /* this is gross.  We think these should all be the same, and various boards
 202  *  should define CFG_ACTORW to 0 if they don't want to set it, or even, if
 203  *  its not set, we define it to zero in this file
 204  */
 205 #if defined(CONFIG_CU824) || defined(CONFIG_PN62)
 206         CONFIG_WRITE_WORD(MCCR4,
 207         (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) |
 208         (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
 209         MCCR4_BIT21 |
 210         (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
 211         ((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
 212         (((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) |
 213                   CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) |
 214         (CFG_ACTORW << MCCR4_ACTTORW_SHIFT) |
 215         (((CFG_BSTOPRE & 0x03c0) >> 6) << MCCR4_BSTOPRE6TO9_SHIFT));
 216 #elif defined(CONFIG_MPC8240)
 217         CONFIG_WRITE_WORD(MCCR4,
 218         (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) |
 219         (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
 220         MCCR4_BIT21 |
 221         (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
 222         ((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
 223         (((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) |
 224                   (CFG_SDMODE_BURSTLEN)) <<MCCR4_SDMODE_SHIFT) |
 225         (((CFG_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
 226 #elif defined(CONFIG_MPC8245)
 227         CONFIG_READ_WORD(MCCR1, val);
 228         val &= MCCR1_DBUS_SIZE0;    /* test for 64-bit mem bus */
 229
 230         CONFIG_WRITE_WORD(MCCR4,
 231                 (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) |
 232                 (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
 233                 (CFG_EXTROM ? MCCR4_EXTROM : 0) |
 234                 (CFG_REGDIMM ? MCCR4_REGDIMM : 0) |
 235                 (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
 236                 ((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
 237                 (CFG_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) |
 238                 (((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) |
 239                       (val ? 2 : 3)) << MCCR4_SDMODE_SHIFT)  |
 240                 (CFG_ACTORW << MCCR4_ACTTORW_SHIFT) |
 241                 (((CFG_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
 242 #else
 243 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
 244 #endif
 245
 246         CONFIG_WRITE_WORD(MSAR1,
 247                 ( (CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
 248                 (((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
 249                 (((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
 250                 (((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
 251         CONFIG_WRITE_WORD(EMSAR1,
 252                 ( (CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
 253                 (((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
 254                 (((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
 255                 (((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
 256         CONFIG_WRITE_WORD(MSAR2,
 257                 ( (CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
 258                 (((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
 259                 (((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
 260                 (((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
 261         CONFIG_WRITE_WORD(EMSAR2,
 262                 ( (CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
 263                 (((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
 264                 (((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
 265                 (((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
 266         CONFIG_WRITE_WORD(MEAR1,
 267                 ( (CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
 268                 (((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
 269                 (((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
 270                 (((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
 271         CONFIG_WRITE_WORD(EMEAR1,
 272                 ( (CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
 273                 (((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
 274                 (((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
 275                 (((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
 276         CONFIG_WRITE_WORD(MEAR2,
 277                 ( (CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
 278                 (((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
 279                 (((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
 280                 (((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
 281         CONFIG_WRITE_WORD(EMEAR2,
 282                 ( (CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
 283                 (((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
 284                 (((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
 285                 (((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
 286
 287         CONFIG_WRITE_BYTE(ODCR, CFG_ODCR);
 288 #ifdef CFG_DLL_MAX_DELAY
 289         CONFIG_WRITE_BYTE(MIOCR1, CFG_DLL_MAX_DELAY);   /* needed to make DLL lock */
 290 #endif
 291 #if defined(CFG_DLL_EXTEND) && defined(CFG_PCI_HOLD_DEL)
 292         CONFIG_WRITE_BYTE(PMCR2, CFG_DLL_EXTEND | CFG_PCI_HOLD_DEL);
 293 #endif
 294 #if defined(MIOCR2) && defined(CFG_SDRAM_DSCD)
 295         CONFIG_WRITE_BYTE(MIOCR2, CFG_SDRAM_DSCD);      /* change memory input */
 296 #endif /* setup & hold time */
 297
 298         CONFIG_WRITE_BYTE(MBER,
 299                  CFG_BANK0_ENABLE |
 300                 (CFG_BANK1_ENABLE << 1) |
 301                 (CFG_BANK2_ENABLE << 2) |
 302                 (CFG_BANK3_ENABLE << 3) |
 303                 (CFG_BANK4_ENABLE << 4) |
 304                 (CFG_BANK5_ENABLE << 5) |
 305                 (CFG_BANK6_ENABLE << 6) |
 306                 (CFG_BANK7_ENABLE << 7));
 307
 308 #ifdef CFG_PGMAX
 309         CONFIG_WRITE_BYTE(MPMR, CFG_PGMAX);
 310 #endif
 311
 312         /* ! Wait 200us before initialize other registers */
 313         /*FIXME: write a decent udelay wait */
 314         __asm__ __volatile__(
 315                 " mtctr %0 \n \
 316                 0: bdnz  0b\n"
 317                 :
 318                 : "r" (0x10000));
 319
 320         CONFIG_READ_WORD(MCCR1, val);
 321         CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */
 322         __asm__ __volatile__("eieio");
 323
 324 #endif /* !CONFIG_MOUSSE && !CONFIG_BMW */
 325 }
 326
 327
 328 #ifdef CONFIG_MOUSSE
 329 #ifdef INCLUDE_MPC107_REPORT
 330 struct MPC107_s {
 331         unsigned int iobase;
 332         char desc[120];
 333 } MPC107Regs[] = {
 334         { BMC_BASE +  0x00, "MPC107 Vendor/Device ID"           },
 335         { BMC_BASE +  0x04, "MPC107 PCI Command/Status Register" },
 336         { BMC_BASE +  0x08, "MPC107 Revision"                   },
 337         { BMC_BASE +  0x0C, "MPC107 Cache Line Size"            },
 338         { BMC_BASE +  0x10, "MPC107 LMBAR"                      },
 339         { BMC_BASE +  0x14, "MPC824x PCSR"                      },
 340         { BMC_BASE +  0xA8, "MPC824x PICR1"                     },
 341         { BMC_BASE +  0xAC, "MPC824x PICR2"                     },
 342         { BMC_BASE +  0x46, "MPC824x PACR"                      },
 343         { BMC_BASE + 0x310, "MPC824x ITWR"                      },
 344         { BMC_BASE + 0x300, "MPC824x OMBAR"                     },
 345         { BMC_BASE + 0x308, "MPC824x OTWR"                      },
 346         { BMC_BASE +  0x14, "MPC107 Peripheral Control and Status Register" },
 347         { BMC_BASE + 0x78, "MPC107 EUMBAR"                      },
 348         { BMC_BASE + 0xC0, "MPC107 Processor Bus Error Status"  },
 349         { BMC_BASE + 0xC4, "MPC107 PCI Bus Error Status"        },
 350         { BMC_BASE + 0xC8, "MPC107 Processor/PCI Error Address" },
 351         { BMC_BASE + 0xE0, "MPC107 AMBOR Register"              },
 352         { BMC_BASE + 0xF0, "MPC107 MCCR1 Register"              },
 353         { BMC_BASE + 0xF4, "MPC107 MCCR2 Register"              },
 354         { BMC_BASE + 0xF8, "MPC107 MCCR3 Register"              },
 355         { BMC_BASE + 0xFC, "MPC107 MCCR4 Register"              },
 356 };
 357 #define N_MPC107_Regs   (sizeof(MPC107Regs)/sizeof(MPC107Regs[0]))
 358 #endif /* INCLUDE_MPC107_REPORT */
 359 #endif /* CONFIG_MOUSSE */
 360
 361 /*
 362  * initialize higher level parts of CPU like time base and timers
 363  */
 364 int cpu_init_r (void)
 365 {
 366 #ifdef CONFIG_MOUSSE
 367 #ifdef INCLUDE_MPC107_REPORT
 368         unsigned int tmp = 0, i;
 369 #endif
 370         /*
 371          * Initialize the EUMBBAR (Embedded Util Mem Block Base Addr Reg).
 372          * This is necessary before the EPIC, DMA ctlr, I2C ctlr, etc. can
 373          * be accessed.
 374          */
 375
 376 #ifdef CONFIG_MPC8240                   /* only on MPC8240 */
 377         mpc824x_mpc107_setreg (EUMBBAR, EUMBBAR_VAL);
 378         /* MOT/SPS: Issue #10002, PCI (FD Alias enable) */
 379         mpc824x_mpc107_setreg (AMBOR, 0x000000C0);
 380 #endif
 381
 382
 383 #ifdef INCLUDE_MPC107_REPORT
 384         /* Check MPC824x PCI Device and Vendor ID */
 385         while ((tmp = mpc824x_mpc107_getreg (BMC_BASE)) != 0x31057) {
 386                 printf ("       MPC107: offset=0x%x, val = 0x%x\n",
 387                         BMC_BASE,
 388                         tmp);
 389         }
 390
 391         for (i = 0; i < N_MPC107_Regs; i++) {
 392                 printf ("       0x%x/%s = 0x%x\n",
 393                         MPC107Regs[i].iobase,
 394                         MPC107Regs[i].desc,
 395                         mpc824x_mpc107_getreg (MPC107Regs[i].iobase));
 396         }
 397
 398         printf ("IBAT0L = 0x%08X\n", mfspr (IBAT0L));
 399         printf ("IBAT0U = 0x%08X\n", mfspr (IBAT0U));
 400         printf ("IBAT1L = 0x%08X\n", mfspr (IBAT1L));
 401         printf ("IBAT1U = 0x%08X\n", mfspr (IBAT1U));
 402         printf ("IBAT2L = 0x%08X\n", mfspr (IBAT2L));
 403         printf ("IBAT2U = 0x%08X\n", mfspr (IBAT2U));
 404         printf ("IBAT3L = 0x%08X\n", mfspr (IBAT3L));
 405         printf ("IBAT3U = 0x%08X\n", mfspr (IBAT3U));
 406         printf ("DBAT0L = 0x%08X\n", mfspr (DBAT0L));
 407         printf ("DBAT0U = 0x%08X\n", mfspr (DBAT0U));
 408         printf ("DBAT1L = 0x%08X\n", mfspr (DBAT1L));
 409         printf ("DBAT1U = 0x%08X\n", mfspr (DBAT1U));
 410         printf ("DBAT2L = 0x%08X\n", mfspr (DBAT2L));
 411         printf ("DBAT2U = 0x%08X\n", mfspr (DBAT2U));
 412         printf ("DBAT3L = 0x%08X\n", mfspr (DBAT3L));
 413         printf ("DBAT3U = 0x%08X\n", mfspr (DBAT3U));
 414 #endif /* INCLUDE_MPC107_REPORT */
 415 #endif /* CONFIG_MOUSSE */
 416         return (0);
 417 }