3 * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
6 * Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/processor.h>
34 * When handling TLB or caches, we need to do it from P2 area.
36 #define jump_to_P2() \
38 unsigned long __dummy; \
39 __asm__ __volatile__( \
48 : "r" (0x20000000)); \
54 #define back_to_P1() \
56 unsigned long __dummy; \
57 __asm__ __volatile__( \
58 "nop;nop;nop;nop;nop;nop;nop\n\t" \
69 #define CACHE_UPDATED 2
71 static inline void cache_wback_all(void)
73 unsigned long addr
, data
, i
, j
;
76 for (i
= 0; i
< CACHE_OC_NUM_ENTRIES
; i
++) {
77 for (j
= 0; j
< CACHE_OC_NUM_WAYS
; j
++) {
78 addr
= CACHE_OC_ADDRESS_ARRAY
79 | (j
<< CACHE_OC_WAY_SHIFT
)
80 | (i
<< CACHE_OC_ENTRY_SHIFT
);
82 if (data
& CACHE_UPDATED
) {
83 data
&= ~CACHE_UPDATED
;
92 #define CACHE_ENABLE 0
93 #define CACHE_DISABLE 1
95 int cache_control(unsigned int cmd
)
102 if (ccr
& CCR_CACHE_ENABLE
)
105 if (cmd
== CACHE_DISABLE
)
106 outl(CCR_CACHE_STOP
, CCR
);
108 outl(CCR_CACHE_INIT
, CCR
);