cpu/pxa/usb.c

   1 /*
   2  * (C) Copyright 2006
   3  * Markus Klotzbuecher, DENX Software Engineering <mk@denx.de>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25
  26 #if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
  27 # if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
  28
  29 #include <asm/arch/pxa-regs.h>
  30 #include <usb.h>
  31
  32 int usb_cpu_init(void)
  33 {
  34 #if defined(CONFIG_CPU_MONAHANS)
  35         /* Enable USB host clock. */
  36         CKENA |= (CKENA_2_USBHOST |  CKENA_20_UDC);
  37         udelay(100);
  38 #endif
  39 #if defined(CONFIG_PXA27X)
  40         /* Enable USB host clock. */
  41         CKEN |= CKEN10_USBHOST;
  42 #endif
  43
  44 #if defined(CONFIG_CPU_MONAHANS)
  45         /* Configure Port 2 for Host (USB Client Registers) */
  46         UP2OCR = 0x3000c;
  47 #endif
  48
  49         UHCHR |= UHCHR_FHR;
  50         wait_ms(11);
  51         UHCHR &= ~UHCHR_FHR;
  52
  53         UHCHR |= UHCHR_FSBIR;
  54         while (UHCHR & UHCHR_FSBIR)
  55                 udelay(1);
  56
  57 #if defined(CONFIG_CPU_MONAHANS)
  58         UHCHR &= ~UHCHR_SSEP0;
  59 #endif
  60 #if defined(CONFIG_PXA27X)
  61         UHCHR &= ~UHCHR_SSEP2;
  62 #endif
  63         UHCHR &= ~UHCHR_SSEP1;
  64         UHCHR &= ~UHCHR_SSE;
  65
  66         return 0;
  67 }
  68
  69 int usb_cpu_stop(void)
  70 {
  71         UHCHR |= UHCHR_FHR;
  72         udelay(11);
  73         UHCHR &= ~UHCHR_FHR;
  74
  75         UHCCOMS |= 1;
  76         udelay(10);
  77
  78 #if defined(CONFIG_CPU_MONAHANS)
  79         UHCHR |= UHCHR_SSEP0;
  80 #endif
  81 #if defined(CONFIG_PXA27X)
  82         UHCHR |= UHCHR_SSEP2;
  83 #endif
  84         UHCHR |= UHCHR_SSEP1;
  85         UHCHR |= UHCHR_SSE;
  86
  87         return 0;
  88 }
  89
  90 int usb_cpu_init_fail(void)
  91 {
  92         UHCHR |= UHCHR_FHR;
  93         udelay(11);
  94         UHCHR &= ~UHCHR_FHR;
  95
  96         UHCCOMS |= 1;
  97         udelay(10);
  98
  99 #if defined(CONFIG_CPU_MONAHANS)
 100         UHCHR |= UHCHR_SSEP0;
 101 #endif
 102 #if defined(CONFIG_PXA27X)
 103         UHCHR |= UHCHR_SSEP2;
 104 #endif
 105         UHCHR |= UHCHR_SSEP1;
 106         UHCHR |= UHCHR_SSE;
 107
 108         return 0;
 109 }
 110
 111 # endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) */
 112 #endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */