2 * linux/arch/ppc/kernel/traps.c
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 * Modified by Cort Dougan (cort@cs.nmt.edu)
7 * and Paul Mackerras (paulus@cs.anu.edu.au)
10 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * This file handles the architecture-dependent parts of hardware exceptions
37 #include <asm/processor.h>
39 DECLARE_GLOBAL_DATA_PTR
;
41 #if defined(CONFIG_CMD_KGDB)
42 int (*debugger_exception_handler
)(struct pt_regs
*) = 0;
45 /* Returns 0 if exception not found and fixup otherwise. */
46 extern unsigned long search_exception_table(unsigned long);
48 /* THIS NEEDS CHANGING to use the board info structure.
50 #define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
52 static __inline__
void set_tsr(unsigned long val
)
54 #if defined(CONFIG_440)
55 asm volatile("mtspr 0x150, %0" : : "r" (val
));
57 asm volatile("mttsr %0" : : "r" (val
));
61 static __inline__
unsigned long get_esr(void)
65 #if defined(CONFIG_440)
66 asm volatile("mfspr %0, 0x03e" : "=r" (val
) :);
68 asm volatile("mfesr %0" : "=r" (val
) :);
73 #define ESR_MCI 0x80000000
74 #define ESR_PIL 0x08000000
75 #define ESR_PPR 0x04000000
76 #define ESR_PTR 0x02000000
77 #define ESR_DST 0x00800000
78 #define ESR_DIZ 0x00400000
79 #define ESR_U0F 0x00008000
81 #if defined(CONFIG_CMD_BEDBUG)
82 extern void do_bedbug_breakpoint(struct pt_regs
*);
86 * Trap & Exception support
90 print_backtrace(unsigned long *sp
)
95 printf("Call backtrace: ");
97 if ((uint
)sp
> END_OF_MEM
)
105 sp
= (unsigned long *)*sp
;
110 void show_regs(struct pt_regs
* regs
)
114 printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DEAR: %08lX\n",
115 regs
->nip
, regs
->xer
, regs
->link
, regs
, regs
->trap
, regs
->dar
);
116 printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
117 regs
->msr
, regs
->msr
&MSR_EE
? 1 : 0, regs
->msr
&MSR_PR
? 1 : 0,
118 regs
->msr
& MSR_FP
? 1 : 0,regs
->msr
&MSR_ME
? 1 : 0,
119 regs
->msr
&MSR_IR
? 1 : 0,
120 regs
->msr
&MSR_DR
? 1 : 0);
123 for (i
= 0; i
< 32; i
++) {
125 printf("GPR%02d: ", i
);
128 printf("%08lX ", regs
->gpr
[i
]);
137 _exception(int signr
, struct pt_regs
*regs
)
140 print_backtrace((unsigned long *)regs
->gpr
[1]);
145 MachineCheckException(struct pt_regs
*regs
)
147 unsigned long fixup
, val
;
148 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
154 if ((fixup
= search_exception_table(regs
->nip
)) != 0) {
158 mtspr(SPRN_MCSR
, val
);
162 #if defined(CONFIG_CMD_KGDB)
163 if (debugger_exception_handler
&& (*debugger_exception_handler
)(regs
))
167 printf("Machine Check Exception.\n");
168 printf("Caused by (from msr): ");
169 printf("regs %p ", regs
);
173 #if !defined(CONFIG_440)
175 printf("Instruction");
176 mtspr(ESR
, val
& ~ESR_IMCP
);
180 printf(" machine check.\n");
182 #elif defined(CONFIG_440)
184 printf("Instruction Synchronous Machine Check exception\n");
185 mtspr(SPRN_ESR
, val
& ~ESR_IMCP
);
189 printf("Instruction Read PLB Error\n");
191 printf("Data Read PLB Error\n");
193 printf("Data Write PLB Error\n");
195 printf("TLB Parity Error\n");
197 /*flush_instruction_cache(); */
198 printf("I-Cache Parity Error\n");
201 printf("D-Cache Search Parity Error\n");
203 printf("D-Cache Flush Parity Error\n");
205 printf("Machine Check exception is imprecise\n");
208 mtspr(SPRN_MCSR
, val
);
210 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
211 mfsdram(DDR0_00
, val
) ;
212 printf("DDR0: DDR0_00 %p\n", val
);
213 val
= (val
>> 16) & 0xff;
215 printf("DDR0: At least one interrupt active\n");
217 printf("DDR0: DRAM initialization complete.\n");
219 printf("DDR0: Multiple uncorrectable ECC events.\n");
223 printf("DDR0: Single uncorrectable ECC event.\n");
227 printf("DDR0: Multiple correctable ECC events.\n");
231 printf("DDR0: Single correctable ECC event.\n");
235 printf("Multiple accesses outside the defined"
236 " physical memory space detected\n");
238 printf("DDR0: Single access outside the defined"
239 " physical memory space detected.\n");
241 mfsdram(DDR0_01
, val
);
242 val
= (val
>> 8) & 0x7;
245 printf("DDR0: Write Out-of-Range command\n");
248 printf("DDR0: Read Out-of-Range command\n");
251 printf("DDR0: Masked write Out-of-Range command\n");
254 printf("DDR0: Wrap write Out-of-Range command\n");
257 printf("DDR0: Wrap read Out-of-Range command\n");
260 mfsdram(DDR0_01
, value2
);
261 printf("DDR0: No DDR0 error know 0x%x %p\n", val
, value2
);
263 mfsdram(DDR0_23
, val
);
264 if (((val
>> 16) & 0xff) && corr_ecc
)
265 printf("DDR0: Syndrome for correctable ECC event 0x%x\n",
267 mfsdram(DDR0_23
, val
);
268 if (((val
>> 8) & 0xff) && uncorr_ecc
)
269 printf("DDR0: Syndrome for uncorrectable ECC event 0x%x\n",
271 mfsdram(DDR0_33
, val
);
273 printf("DDR0: Address of command that caused an "
274 "Out-of-Range interrupt %p\n", val
);
275 mfsdram(DDR0_34
, val
);
276 if (val
&& uncorr_ecc
)
277 printf("DDR0: Address of uncorrectable ECC event %p\n", val
);
278 mfsdram(DDR0_35
, val
);
279 if (val
&& uncorr_ecc
)
280 printf("DDR0: Address of uncorrectable ECC event %p\n", val
);
281 mfsdram(DDR0_36
, val
);
282 if (val
&& uncorr_ecc
)
283 printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val
);
284 mfsdram(DDR0_37
, val
);
285 if (val
&& uncorr_ecc
)
286 printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val
);
287 mfsdram(DDR0_38
, val
);
289 printf("DDR0: Address of correctable ECC event %p\n", val
);
290 mfsdram(DDR0_39
, val
);
292 printf("DDR0: Address of correctable ECC event %p\n", val
);
293 mfsdram(DDR0_40
, val
);
295 printf("DDR0: Data of correctable ECC event 0x%08x\n", val
);
296 mfsdram(DDR0_41
, val
);
298 printf("DDR0: Data of correctable ECC event 0x%08x\n", val
);
299 #endif /* CONFIG_440EPX */
300 #endif /* CONFIG_440 */
302 print_backtrace((unsigned long *)regs
->gpr
[1]);
303 panic("machine check");
307 AlignmentException(struct pt_regs
*regs
)
309 #if defined(CONFIG_CMD_KGDB)
310 if (debugger_exception_handler
&& (*debugger_exception_handler
)(regs
))
315 print_backtrace((unsigned long *)regs
->gpr
[1]);
316 panic("Alignment Exception");
320 ProgramCheckException(struct pt_regs
*regs
)
324 #if defined(CONFIG_CMD_KGDB)
325 if (debugger_exception_handler
&& (*debugger_exception_handler
)(regs
))
332 if( esr_val
& ESR_PIL
)
333 printf( "** Illegal Instruction **\n" );
334 else if( esr_val
& ESR_PPR
)
335 printf( "** Privileged Instruction **\n" );
336 else if( esr_val
& ESR_PTR
)
337 printf( "** Trap Instruction **\n" );
339 print_backtrace((unsigned long *)regs
->gpr
[1]);
340 panic("Program Check Exception");
344 DecrementerPITException(struct pt_regs
*regs
)
347 * Reset PIT interrupt
352 * Call timer_interrupt routine in interrupts.c
354 timer_interrupt(NULL
);
359 UnknownException(struct pt_regs
*regs
)
361 #if defined(CONFIG_CMD_KGDB)
362 if (debugger_exception_handler
&& (*debugger_exception_handler
)(regs
))
366 printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
367 regs
->nip
, regs
->msr
, regs
->trap
);
372 DebugException(struct pt_regs
*regs
)
374 printf("Debugger trap at @ %lx\n", regs
->nip
);
376 #if defined(CONFIG_CMD_BEDBUG)
377 do_bedbug_breakpoint( regs
);
381 /* Probe an address by reading. If not present, return -1, otherwise
385 addr_probe(uint
*addr
)
390 __asm__
__volatile__( \
391 "1: lwz %0,0(%1)\n" \
395 ".section .fixup,\"ax\"\n" \
398 ".section __ex_table,\"a\"\n" \
402 : "=r" (retval
) : "r"(addr
));