cpu/ppc4xx/iop480_uart.c

   1 /*
   2  * (C) Copyright 2000-2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <commproc.h>
  26 #include <asm/processor.h>
  27 #include <asm/io.h>
  28 #include <watchdog.h>
  29 #include <asm/ppc4xx-intvec.h>
  30
  31 #ifdef CONFIG_SERIAL_MULTI
  32 #include <serial.h>
  33 #endif
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #ifdef CONFIG_IOP480
  38
  39 #define SPU_BASE         0x40000000
  40
  41 #define spu_LineStat_rc  0x00   /* Line Status Register (Read/Clear) */
  42 #define spu_LineStat_w   0x04   /* Line Status Register (Set) */
  43 #define spu_Handshk_rc   0x08   /* Handshake Status Register (Read/Clear) */
  44 #define spu_Handshk_w    0x0c   /* Handshake Status Register (Set) */
  45 #define spu_BRateDivh    0x10   /* Baud rate divisor high */
  46 #define spu_BRateDivl    0x14   /* Baud rate divisor low */
  47 #define spu_CtlReg       0x18   /* Control Register */
  48 #define spu_RxCmd        0x1c   /* Rx Command Register */
  49 #define spu_TxCmd        0x20   /* Tx Command Register */
  50 #define spu_RxBuff       0x24   /* Rx data buffer */
  51 #define spu_TxBuff       0x24   /* Tx data buffer */
  52
  53 /*-----------------------------------------------------------------------------+
  54   | Line Status Register.
  55   +-----------------------------------------------------------------------------*/
  56 #define asyncLSRport1           0x40000000
  57 #define asyncLSRport1set        0x40000004
  58 #define asyncLSRDataReady             0x80
  59 #define asyncLSRFramingError          0x40
  60 #define asyncLSROverrunError          0x20
  61 #define asyncLSRParityError           0x10
  62 #define asyncLSRBreakInterrupt        0x08
  63 #define asyncLSRTxHoldEmpty           0x04
  64 #define asyncLSRTxShiftEmpty          0x02
  65
  66 /*-----------------------------------------------------------------------------+
  67   | Handshake Status Register.
  68   +-----------------------------------------------------------------------------*/
  69 #define asyncHSRport1           0x40000008
  70 #define asyncHSRport1set        0x4000000c
  71 #define asyncHSRDsr                   0x80
  72 #define asyncLSRCts                   0x40
  73
  74 /*-----------------------------------------------------------------------------+
  75   | Control Register.
  76   +-----------------------------------------------------------------------------*/
  77 #define asyncCRport1            0x40000018
  78 #define asyncCRNormal                 0x00
  79 #define asyncCRLoopback               0x40
  80 #define asyncCRAutoEcho               0x80
  81 #define asyncCRDtr                    0x20
  82 #define asyncCRRts                    0x10
  83 #define asyncCRWordLength7            0x00
  84 #define asyncCRWordLength8            0x08
  85 #define asyncCRParityDisable          0x00
  86 #define asyncCRParityEnable           0x04
  87 #define asyncCREvenParity             0x00
  88 #define asyncCROddParity              0x02
  89 #define asyncCRStopBitsOne            0x00
  90 #define asyncCRStopBitsTwo            0x01
  91 #define asyncCRDisableDtrRts          0x00
  92
  93 /*-----------------------------------------------------------------------------+
  94   | Receiver Command Register.
  95   +-----------------------------------------------------------------------------*/
  96 #define asyncRCRport1           0x4000001c
  97 #define asyncRCRDisable               0x00
  98 #define asyncRCREnable                0x80
  99 #define asyncRCRIntDisable            0x00
 100 #define asyncRCRIntEnabled            0x20
 101 #define asyncRCRDMACh2                0x40
 102 #define asyncRCRDMACh3                0x60
 103 #define asyncRCRErrorInt              0x10
 104 #define asyncRCRPauseEnable           0x08
 105
 106 /*-----------------------------------------------------------------------------+
 107   | Transmitter Command Register.
 108   +-----------------------------------------------------------------------------*/
 109 #define asyncTCRport1           0x40000020
 110 #define asyncTCRDisable               0x00
 111 #define asyncTCREnable                0x80
 112 #define asyncTCRIntDisable            0x00
 113 #define asyncTCRIntEnabled            0x20
 114 #define asyncTCRDMACh2                0x40
 115 #define asyncTCRDMACh3                0x60
 116 #define asyncTCRTxEmpty               0x10
 117 #define asyncTCRErrorInt              0x08
 118 #define asyncTCRStopPause             0x04
 119 #define asyncTCRBreakGen              0x02
 120
 121 /*-----------------------------------------------------------------------------+
 122   | Miscellanies defines.
 123   +-----------------------------------------------------------------------------*/
 124 #define asyncTxBufferport1      0x40000024
 125 #define asyncRxBufferport1      0x40000024
 126 #define asyncDLABLsbport1       0x40000014
 127 #define asyncDLABMsbport1       0x40000010
 128 #define asyncXOFFchar                 0x13
 129 #define asyncXONchar                  0x11
 130
 131 /*
 132  * Minimal serial functions needed to use one of the SMC ports
 133  * as serial console interface.
 134  */
 135
 136 int serial_init (void)
 137 {
 138         volatile char val;
 139         unsigned short br_reg;
 140
 141         br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
 142
 143         /*
 144          * Init onboard UART
 145          */
 146         out_8((u8 *)SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */
 147         out_8((u8 *)SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
 148         out_8((u8 *)SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
 149         out_8((u8 *)SPU_BASE + spu_CtlReg, 0x08);       /* Set 8 bits, no parity and 1 stop bit */
 150         out_8((u8 *)SPU_BASE + spu_RxCmd, 0xb0);        /* Enable Rx */
 151         out_8((u8 *)SPU_BASE + spu_TxCmd, 0x9c);        /* Enable Tx */
 152         out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff);   /* Clear Handshake */
 153         val = in_8((u8 *)SPU_BASE + spu_RxBuff);        /* Dummy read, to clear receiver */
 154
 155         return (0);
 156 }
 157
 158 void serial_setbrg (void)
 159 {
 160         unsigned short br_reg;
 161
 162         br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
 163
 164         out_8((u8 *)SPU_BASE + spu_BRateDivl,
 165               (br_reg & 0x00ff)); /* Set baud rate divisor... */
 166         out_8((u8 *)SPU_BASE + spu_BRateDivh,
 167               ((br_reg & 0xff00) >> 8)); /* ... */
 168 }
 169
 170 void serial_putc (const char c)
 171 {
 172         if (c == '\n')
 173                 serial_putc ('\r');
 174
 175         /* load status from handshake register */
 176         if (in_8((u8 *)SPU_BASE + spu_Handshk_rc) != 00)
 177                 out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff);   /* Clear Handshake */
 178
 179         out_8((u8 *)SPU_BASE + spu_TxBuff, c);  /* Put char */
 180
 181         while ((in_8((u8 *)SPU_BASE + spu_LineStat_rc) & 04) != 04) {
 182                 if (in_8((u8 *)SPU_BASE + spu_Handshk_rc) != 00)
 183                         out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff);   /* Clear Handshake */
 184         }
 185 }
 186
 187 void serial_puts (const char *s)
 188 {
 189         while (*s) {
 190                 serial_putc (*s++);
 191         }
 192 }
 193
 194 int serial_getc ()
 195 {
 196         unsigned char status = 0;
 197
 198         while (1) {
 199                 status = in_8((u8 *)asyncLSRport1);
 200                 if ((status & asyncLSRDataReady) != 0x0) {
 201                         break;
 202                 }
 203                 if ((status & ( asyncLSRFramingError |
 204                                 asyncLSROverrunError |
 205                                 asyncLSRParityError  |
 206                                 asyncLSRBreakInterrupt )) != 0) {
 207                         (void) out_8((u8 *)asyncLSRport1,
 208                                      asyncLSRFramingError |
 209                                      asyncLSROverrunError |
 210                                      asyncLSRParityError  |
 211                                      asyncLSRBreakInterrupt );
 212                 }
 213         }
 214         return (0x000000ff & (int) in_8((u8 *)asyncRxBufferport1));
 215 }
 216
 217 int serial_tstc ()
 218 {
 219         unsigned char status;
 220
 221         status = in_8((u8 *)asyncLSRport1);
 222         if ((status & asyncLSRDataReady) != 0x0) {
 223                 return (1);
 224         }
 225         if ((status & ( asyncLSRFramingError |
 226                         asyncLSROverrunError |
 227                         asyncLSRParityError  |
 228                         asyncLSRBreakInterrupt )) != 0) {
 229                 (void) out_8((u8 *)asyncLSRport1,
 230                              asyncLSRFramingError |
 231                              asyncLSROverrunError |
 232                              asyncLSRParityError  |
 233                              asyncLSRBreakInterrupt);
 234         }
 235         return 0;
 236 }
 237
 238 #endif  /* CONFIG_IOP480 */