3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * This file is based on mpc4200fec.c,
6 * (C) Copyright Motorola, Inc., 2000
18 #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
19 defined(CONFIG_MPC8220_FEC)
21 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
22 #error "CONFIG_MII has to be defined!"
26 static void tfifo_print (char *devname
, mpc8220_fec_priv
* fec
);
27 static void rfifo_print (char *devname
, mpc8220_fec_priv
* fec
);
31 static u32
local_crc32 (char *string
, unsigned int crc_value
, int len
);
35 u8 data
[1500]; /* actual data */
36 int length
; /* actual length */
37 int used
; /* buffer in use or not */
38 u8 head
[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
41 int fec8220_miiphy_read (char *devname
, u8 phyAddr
, u8 regAddr
, u16
* retVal
);
42 int fec8220_miiphy_write (char *devname
, u8 phyAddr
, u8 regAddr
, u16 data
);
44 /********************************************************************/
46 static void mpc8220_fec_phydump (char *devname
)
49 u8 phyAddr
= CONFIG_PHY_ADDR
;
51 #if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */
52 /* regs to print: 0...7, 16...19, 21, 23, 24 */
53 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
54 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0,
56 /* regs to print: 0...8, 16...20 */
57 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
58 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
62 for (i
= 0; i
< 32; i
++) {
64 miiphy_read (devname
, phyAddr
, i
, &phyStatus
);
65 printf ("Mii reg %d: 0x%04x\n", i
, phyStatus
);
71 /********************************************************************/
72 static int mpc8220_fec_rbd_init (mpc8220_fec_priv
* fec
)
78 for (ix
= 0; ix
< FEC_RBD_NUM
; ix
++) {
80 data
= (char *) malloc (FEC_MAX_PKT_SIZE
);
82 printf ("RBD INIT FAILED\n");
85 fec
->rbdBase
[ix
].dataPointer
= (u32
) data
;
87 fec
->rbdBase
[ix
].status
= FEC_RBD_EMPTY
;
88 fec
->rbdBase
[ix
].dataLength
= 0;
93 * have the last RBD to close the ring
95 fec
->rbdBase
[ix
- 1].status
|= FEC_RBD_WRAP
;
101 /********************************************************************/
102 static void mpc8220_fec_tbd_init (mpc8220_fec_priv
* fec
)
106 for (ix
= 0; ix
< FEC_TBD_NUM
; ix
++) {
107 fec
->tbdBase
[ix
].status
= 0;
111 * Have the last TBD to close the ring
113 fec
->tbdBase
[ix
- 1].status
|= FEC_TBD_WRAP
;
116 * Initialize some indices
119 fec
->usedTbdIndex
= 0;
120 fec
->cleanTbdNum
= FEC_TBD_NUM
;
123 /********************************************************************/
124 static void mpc8220_fec_rbd_clean (mpc8220_fec_priv
* fec
, FEC_RBD
* pRbd
)
127 * Reset buffer descriptor as empty
129 if ((fec
->rbdIndex
) == (FEC_RBD_NUM
- 1))
130 pRbd
->status
= (FEC_RBD_WRAP
| FEC_RBD_EMPTY
);
132 pRbd
->status
= FEC_RBD_EMPTY
;
134 pRbd
->dataLength
= 0;
137 * Now, we have an empty RxBD, restart the SmartDMA receive task
139 DMA_TASK_ENABLE (FEC_RECV_TASK_NO
);
144 fec
->rbdIndex
= (fec
->rbdIndex
+ 1) % FEC_RBD_NUM
;
147 /********************************************************************/
148 static void mpc8220_fec_tbd_scrub (mpc8220_fec_priv
* fec
)
153 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
154 fec
->cleanTbdNum
, fec
->usedTbdIndex
);
158 * process all the consumed TBDs
160 while (fec
->cleanTbdNum
< FEC_TBD_NUM
) {
161 pUsedTbd
= &fec
->tbdBase
[fec
->usedTbdIndex
];
162 if (pUsedTbd
->status
& FEC_TBD_READY
) {
164 printf ("Cannot clean TBD %d, in use\n",
171 * clean this buffer descriptor
173 if (fec
->usedTbdIndex
== (FEC_TBD_NUM
- 1))
174 pUsedTbd
->status
= FEC_TBD_WRAP
;
176 pUsedTbd
->status
= 0;
179 * update some indeces for a correct handling of the TBD ring
182 fec
->usedTbdIndex
= (fec
->usedTbdIndex
+ 1) % FEC_TBD_NUM
;
186 /********************************************************************/
187 static void mpc8220_fec_set_hwaddr (mpc8220_fec_priv
* fec
, char *mac
)
189 u8 currByte
; /* byte for which to compute the CRC */
190 int byte
; /* loop - counter */
191 int bit
; /* loop - counter */
192 u32 crc
= 0xffffffff; /* initial value */
195 * The algorithm used is the following:
196 * we loop on each of the six bytes of the provided address,
197 * and we compute the CRC by left-shifting the previous
198 * value by one position, so that each bit in the current
199 * byte of the address may contribute the calculation. If
200 * the latter and the MSB in the CRC are different, then
201 * the CRC value so computed is also ex-ored with the
202 * "polynomium generator". The current byte of the address
203 * is also shifted right by one bit at each iteration.
204 * This is because the CRC generatore in hardware is implemented
205 * as a shift-register with as many ex-ores as the radixes
206 * in the polynomium. This suggests that we represent the
207 * polynomiumm itself as a 32-bit constant.
209 for (byte
= 0; byte
< 6; byte
++) {
210 currByte
= mac
[byte
];
211 for (bit
= 0; bit
< 8; bit
++) {
212 if ((currByte
& 0x01) ^ (crc
& 0x01)) {
214 crc
= crc
^ 0xedb88320;
225 * Set individual hash table register
228 fec
->eth
->iaddr1
= (1 << (crc
- 32));
229 fec
->eth
->iaddr2
= 0;
231 fec
->eth
->iaddr1
= 0;
232 fec
->eth
->iaddr2
= (1 << crc
);
236 * Set physical address
239 (mac
[0] << 24) + (mac
[1] << 16) + (mac
[2] << 8) + mac
[3];
240 fec
->eth
->paddr2
= (mac
[4] << 24) + (mac
[5] << 16) + 0x8808;
243 /********************************************************************/
244 static int mpc8220_fec_init (struct eth_device
*dev
, bd_t
* bis
)
246 mpc8220_fec_priv
*fec
= (mpc8220_fec_priv
*) dev
->priv
;
247 struct mpc8220_dma
*dma
= (struct mpc8220_dma
*) MMAP_DMA
;
248 const u8 phyAddr
= CONFIG_PHY_ADDR
; /* Only one PHY */
251 printf ("mpc8220_fec_init... Begin\n");
255 * Initialize RxBD/TxBD rings
257 mpc8220_fec_rbd_init (fec
);
258 mpc8220_fec_tbd_init (fec
);
261 * Set up Pin Muxing for FEC 1
263 *(vu_long
*) MMAP_PCFG
= 0;
264 *(vu_long
*) (MMAP_PCFG
+ 4) = 0;
266 * Clear FEC-Lite interrupt event register(IEVENT)
268 fec
->eth
->ievent
= 0xffffffff;
271 * Set interrupt mask register
273 fec
->eth
->imask
= 0x00000000;
276 * Set FEC-Lite receive control register(R_CNTRL):
278 if (fec
->xcv_type
== SEVENWIRE
) {
280 * Frame length=1518; 7-wire mode
282 fec
->eth
->r_cntrl
= 0x05ee0020; /*0x05ee0000;FIXME */
285 * Frame length=1518; MII mode;
287 fec
->eth
->r_cntrl
= 0x05ee0024; /*0x05ee0004;FIXME */
290 fec
->eth
->x_cntrl
= 0x00000000; /* half-duplex, heartbeat disabled */
291 if (fec
->xcv_type
!= SEVENWIRE
) {
293 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
294 * and do not drop the Preamble.
297 /*fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); */
298 /* No MII for 7-wire mode */
299 fec
->eth
->mii_speed
= 0x00000030;
303 * Set Opcode/Pause Duration Register
305 fec
->eth
->op_pause
= 0x00010020; /*FIXME0xffff0020; */
308 * Set Rx FIFO alarm and granularity value
310 fec
->eth
->rfifo_cntrl
= 0x0c000000;
311 fec
->eth
->rfifo_alarm
= 0x0000030c;
313 if (fec
->eth
->rfifo_status
& 0x00700000) {
314 printf ("mpc8220_fec_init() RFIFO error\n");
319 * Set Tx FIFO granularity value
321 /*fec->eth->tfifo_cntrl = 0x0c000000; */ /*tbd - rtm */
322 fec
->eth
->tfifo_cntrl
= 0x0e000000;
324 printf ("tfifo_status: 0x%08x\n", fec
->eth
->tfifo_status
);
325 printf ("tfifo_alarm: 0x%08x\n", fec
->eth
->tfifo_alarm
);
329 * Set transmit fifo watermark register(X_WMRK), default = 64
331 fec
->eth
->tfifo_alarm
= 0x00000080;
332 fec
->eth
->x_wmrk
= 0x2;
335 * Set individual address filter for unicast address
336 * and set physical address registers.
338 mpc8220_fec_set_hwaddr (fec
, (char *)(dev
->enetaddr
));
341 * Set multicast address filter
343 fec
->eth
->gaddr1
= 0x00000000;
344 fec
->eth
->gaddr2
= 0x00000000;
347 * Turn ON cheater FSM: ????
349 fec
->eth
->xmit_fsm
= 0x03000000;
352 /*#if defined(CONFIG_MPC5200)*/
354 * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't
355 * work w/ the current receive task.
357 dma
->PtdCntrl
|= 0x00000001;
361 * Set priority of different initiators
363 dma
->IPR0
= 7; /* always */
364 dma
->IPR3
= 6; /* Eth RX */
365 dma
->IPR4
= 5; /* Eth Tx */
368 * Clear SmartDMA task interrupt pending bits
370 DMA_CLEAR_IEVENT (FEC_RECV_TASK_NO
);
373 * Initialize SmartDMA parameters stored in SRAM
375 *(int *) FEC_TBD_BASE
= (int) fec
->tbdBase
;
376 *(int *) FEC_RBD_BASE
= (int) fec
->rbdBase
;
377 *(int *) FEC_TBD_NEXT
= (int) fec
->tbdBase
;
378 *(int *) FEC_RBD_NEXT
= (int) fec
->rbdBase
;
380 if (fec
->xcv_type
!= SEVENWIRE
) {
382 * Initialize PHY(LXT971A):
384 * Generally, on power up, the LXT971A reads its configuration
385 * pins to check for forced operation, If not cofigured for
386 * forced operation, it uses auto-negotiation/parallel detection
387 * to automatically determine line operating conditions.
388 * If the PHY device on the other side of the link supports
389 * auto-negotiation, the LXT971A auto-negotiates with it
390 * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
391 * support auto-negotiation, the LXT971A automatically detects
392 * the presence of either link pulses(10Mbps PHY) or Idle
393 * symbols(100Mbps) and sets its operating conditions accordingly.
395 * When auto-negotiation is controlled by software, the following
396 * steps are recommended.
399 * The physical address is dependent on hardware configuration.
406 * Reset PHY, then delay 300ns
408 miiphy_write (dev
->name
, phyAddr
, 0x0, 0x8000);
411 if (fec
->xcv_type
== MII10
) {
413 * Force 10Base-T, FDX operation
416 printf ("Forcing 10 Mbps ethernet link... ");
418 miiphy_read (dev
->name
, phyAddr
, 0x1, &phyStatus
);
420 miiphy_write(fec, phyAddr, 0x0, 0x0100);
422 miiphy_write (dev
->name
, phyAddr
, 0x0, 0x0180);
425 do { /* wait for link status to go down */
427 if ((timeout
--) == 0) {
429 printf ("hmmm, should not have waited...");
433 miiphy_read (dev
->name
, phyAddr
, 0x1, &phyStatus
);
437 } while ((phyStatus
& 0x0004)); /* !link up */
440 do { /* wait for link status to come back up */
442 if ((timeout
--) == 0) {
443 printf ("failed. Link is down.\n");
446 miiphy_read (dev
->name
, phyAddr
, 0x1, &phyStatus
);
450 } while (!(phyStatus
& 0x0004)); /* !link up */
455 } else { /* MII100 */
457 * Set the auto-negotiation advertisement register bits
459 miiphy_write (dev
->name
, phyAddr
, 0x4, 0x01e1);
462 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
464 miiphy_write (dev
->name
, phyAddr
, 0x0, 0x1200);
467 * Wait for AN completion
473 if ((timeout
--) == 0) {
475 printf ("PHY auto neg 0 failed...\n");
480 if (miiphy_read (dev
->name
, phyAddr
, 0x1, &phyStatus
) !=
483 printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus
);
487 } while (!(phyStatus
& 0x0004));
490 printf ("PHY auto neg complete! \n");
497 * Enable FEC-Lite controller
499 fec
->eth
->ecntrl
|= 0x00000006;
502 if (fec
->xcv_type
!= SEVENWIRE
)
503 mpc8220_fec_phydump (dev
->name
);
507 * Enable SmartDMA receive task
509 DMA_TASK_ENABLE (FEC_RECV_TASK_NO
);
512 printf ("mpc8220_fec_init... Done \n");
518 /********************************************************************/
519 static void mpc8220_fec_halt (struct eth_device
*dev
)
521 mpc8220_fec_priv
*fec
= (mpc8220_fec_priv
*) dev
->priv
;
522 int counter
= 0xffff;
525 if (fec
->xcv_type
!= SEVENWIRE
)
526 mpc8220_fec_phydump (dev
->name
);
530 * mask FEC chip interrupts
535 * issue graceful stop command to the FEC transmitter if necessary
537 fec
->eth
->x_cntrl
|= 0x00000001;
540 * wait for graceful stop to register
542 while ((counter
--) && (!(fec
->eth
->ievent
& 0x10000000)));
545 * Disable SmartDMA tasks
547 DMA_TASK_DISABLE (FEC_XMIT_TASK_NO
);
548 DMA_TASK_DISABLE (FEC_RECV_TASK_NO
);
551 * Disable the Ethernet Controller
553 fec
->eth
->ecntrl
&= 0xfffffffd;
556 * Clear FIFO status registers
558 fec
->eth
->rfifo_status
&= 0x00700000;
559 fec
->eth
->tfifo_status
&= 0x00700000;
561 fec
->eth
->reset_cntrl
= 0x01000000;
564 * Issue a reset command to the FEC chip
566 fec
->eth
->ecntrl
|= 0x1;
569 * wait at least 16 clock cycles
574 printf ("Ethernet task stopped\n");
579 /********************************************************************/
581 static void tfifo_print (char *devname
, mpc8220_fec_priv
* fec
)
583 u16 phyAddr
= CONFIG_PHY_ADDR
;
586 if ((fec
->eth
->tfifo_lrf_ptr
!= fec
->eth
->tfifo_lwf_ptr
)
587 || (fec
->eth
->tfifo_rdptr
!= fec
->eth
->tfifo_wrptr
)) {
589 miiphy_read (devname
, phyAddr
, 0x1, &phyStatus
);
590 printf ("\nphyStatus: 0x%04x\n", phyStatus
);
591 printf ("ecntrl: 0x%08x\n", fec
->eth
->ecntrl
);
592 printf ("ievent: 0x%08x\n", fec
->eth
->ievent
);
593 printf ("x_status: 0x%08x\n", fec
->eth
->x_status
);
594 printf ("tfifo: status 0x%08x\n", fec
->eth
->tfifo_status
);
596 printf (" control 0x%08x\n", fec
->eth
->tfifo_cntrl
);
597 printf (" lrfp 0x%08x\n", fec
->eth
->tfifo_lrf_ptr
);
598 printf (" lwfp 0x%08x\n", fec
->eth
->tfifo_lwf_ptr
);
599 printf (" alarm 0x%08x\n", fec
->eth
->tfifo_alarm
);
600 printf (" readptr 0x%08x\n", fec
->eth
->tfifo_rdptr
);
601 printf (" writptr 0x%08x\n", fec
->eth
->tfifo_wrptr
);
605 static void rfifo_print (char *devname
, mpc8220_fec_priv
* fec
)
607 u16 phyAddr
= CONFIG_PHY_ADDR
;
610 if ((fec
->eth
->rfifo_lrf_ptr
!= fec
->eth
->rfifo_lwf_ptr
)
611 || (fec
->eth
->rfifo_rdptr
!= fec
->eth
->rfifo_wrptr
)) {
613 miiphy_read (devname
, phyAddr
, 0x1, &phyStatus
);
614 printf ("\nphyStatus: 0x%04x\n", phyStatus
);
615 printf ("ecntrl: 0x%08x\n", fec
->eth
->ecntrl
);
616 printf ("ievent: 0x%08x\n", fec
->eth
->ievent
);
617 printf ("x_status: 0x%08x\n", fec
->eth
->x_status
);
618 printf ("rfifo: status 0x%08x\n", fec
->eth
->rfifo_status
);
620 printf (" control 0x%08x\n", fec
->eth
->rfifo_cntrl
);
621 printf (" lrfp 0x%08x\n", fec
->eth
->rfifo_lrf_ptr
);
622 printf (" lwfp 0x%08x\n", fec
->eth
->rfifo_lwf_ptr
);
623 printf (" alarm 0x%08x\n", fec
->eth
->rfifo_alarm
);
624 printf (" readptr 0x%08x\n", fec
->eth
->rfifo_rdptr
);
625 printf (" writptr 0x%08x\n", fec
->eth
->rfifo_wrptr
);
630 /********************************************************************/
632 static int mpc8220_fec_send (struct eth_device
*dev
, volatile void *eth_data
,
636 * This routine transmits one frame. This routine only accepts
637 * 6-byte Ethernet addresses.
639 mpc8220_fec_priv
*fec
= (mpc8220_fec_priv
*) dev
->priv
;
643 printf ("tbd status: 0x%04x\n", fec
->tbdBase
[0].status
);
644 tfifo_print (dev
->name
, fec
);
648 * Clear Tx BD ring at first
650 mpc8220_fec_tbd_scrub (fec
);
653 * Check for valid length of data.
655 if ((data_length
> 1500) || (data_length
<= 0)) {
660 * Check the number of vacant TxBDs.
662 if (fec
->cleanTbdNum
< 1) {
664 printf ("No available TxBDs ...\n");
670 * Get the first TxBD to send the mac header
672 pTbd
= &fec
->tbdBase
[fec
->tbdIndex
];
673 pTbd
->dataLength
= data_length
;
674 pTbd
->dataPointer
= (u32
) eth_data
;
675 pTbd
->status
|= FEC_TBD_LAST
| FEC_TBD_TC
| FEC_TBD_READY
;
676 fec
->tbdIndex
= (fec
->tbdIndex
+ 1) % FEC_TBD_NUM
;
679 printf ("DMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec
->tbdIndex
);
685 if (fec
->xcv_type
!= SEVENWIRE
) {
688 miiphy_read (dev
->name
, 0, 0x1, &phyStatus
);
692 * Enable SmartDMA transmit task
696 tfifo_print (dev
->name
, fec
);
699 DMA_TASK_ENABLE (FEC_XMIT_TASK_NO
);
702 tfifo_print (dev
->name
, fec
);
709 fec
->cleanTbdNum
-= 1;
712 printf ("smartDMA ethernet Tx task enabled\n");
715 * wait until frame is sent .
717 while (pTbd
->status
& FEC_TBD_READY
) {
720 printf ("TDB status = %04x\n", pTbd
->status
);
728 /********************************************************************/
729 static int mpc8220_fec_recv (struct eth_device
*dev
)
732 * This command pulls one frame from the card
734 mpc8220_fec_priv
*fec
= (mpc8220_fec_priv
*) dev
->priv
;
735 FEC_RBD
*pRbd
= &fec
->rbdBase
[fec
->rbdIndex
];
736 unsigned long ievent
;
737 int frame_length
, len
= 0;
741 printf ("mpc8220_fec_recv %d Start...\n", fec
->rbdIndex
);
746 * Check if any critical events have happened
748 ievent
= fec
->eth
->ievent
;
749 fec
->eth
->ievent
= ievent
;
750 if (ievent
& 0x20060000) {
751 /* BABT, Rx/Tx FIFO errors */
752 mpc8220_fec_halt (dev
);
753 mpc8220_fec_init (dev
, NULL
);
756 if (ievent
& 0x80000000) {
757 /* Heartbeat error */
758 fec
->eth
->x_cntrl
|= 0x00000001;
760 if (ievent
& 0x10000000) {
761 /* Graceful stop complete */
762 if (fec
->eth
->x_cntrl
& 0x00000001) {
763 mpc8220_fec_halt (dev
);
764 fec
->eth
->x_cntrl
&= ~0x00000001;
765 mpc8220_fec_init (dev
, NULL
);
769 if (!(pRbd
->status
& FEC_RBD_EMPTY
)) {
770 if ((pRbd
->status
& FEC_RBD_LAST
)
771 && !(pRbd
->status
& FEC_RBD_ERR
)
772 && ((pRbd
->dataLength
- 4) > 14)) {
775 * Get buffer address and size
777 frame
= (NBUF
*) pRbd
->dataPointer
;
778 frame_length
= pRbd
->dataLength
- 4;
784 printf ("recv data hdr:");
785 for (i
= 0; i
< 14; i
++)
786 printf ("%x ", *(frame
->head
+ i
));
791 * Fill the buffer and pass it to upper layers
793 /* memcpy(buff, frame->head, 14);
794 memcpy(buff + 14, frame->data, frame_length);*/
795 NetReceive ((volatile uchar
*) pRbd
->dataPointer
,
800 * Reset buffer descriptor as empty
802 mpc8220_fec_rbd_clean (fec
, pRbd
);
804 DMA_CLEAR_IEVENT (FEC_RECV_TASK_NO
);
809 /********************************************************************/
810 int mpc8220_fec_initialize (bd_t
* bis
)
812 mpc8220_fec_priv
*fec
;
814 #ifdef CONFIG_HAS_ETH1
815 mpc8220_fec_priv
*fec2
;
817 struct eth_device
*dev
;
819 char env_enetaddr
[6];
821 #ifdef CONFIG_HAS_ETH1
822 char env_enet1addr
[6];
826 fec
= (mpc8220_fec_priv
*) malloc (sizeof (*fec
));
827 dev
= (struct eth_device
*) malloc (sizeof (*dev
));
828 memset (dev
, 0, sizeof *dev
);
830 fec
->eth
= (ethernet_regs
*) MMAP_FEC1
;
831 #ifdef CONFIG_HAS_ETH1
832 fec2
= (mpc8220_fec_priv
*) malloc (sizeof (*fec
));
833 fec2
->eth
= (ethernet_regs
*) MMAP_FEC2
;
835 fec
->tbdBase
= (FEC_TBD
*) FEC_BD_BASE
;
837 (FEC_RBD
*) (FEC_BD_BASE
+ FEC_TBD_NUM
* sizeof (FEC_TBD
));
838 fec
->xcv_type
= MII100
;
840 dev
->priv
= (void *) fec
;
841 dev
->iobase
= MMAP_FEC1
;
842 dev
->init
= mpc8220_fec_init
;
843 dev
->halt
= mpc8220_fec_halt
;
844 dev
->send
= mpc8220_fec_send
;
845 dev
->recv
= mpc8220_fec_recv
;
847 sprintf (dev
->name
, "FEC ETHERNET");
850 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
851 miiphy_register (dev
->name
,
852 fec8220_miiphy_read
, fec8220_miiphy_write
);
856 * Try to set the mac address now. The fec mac address is
857 * a garbage after reset. When not using fec for booting
858 * the Linux fec driver will try to work with this garbage.
860 tmp
= getenv ("ethaddr");
862 for (i
= 0; i
< 6; i
++) {
864 tmp
? simple_strtoul (tmp
, &end
, 16) : 0;
866 tmp
= (*end
) ? end
+ 1 : end
;
868 mpc8220_fec_set_hwaddr (fec
, env_enetaddr
);
870 #ifdef CONFIG_HAS_ETH1
871 tmp
= getenv ("eth1addr");
873 for (i
= 0; i
< 6; i
++) {
875 tmp
? simple_strtoul (tmp
, &end
, 16) : 0;
877 tmp
= (*end
) ? end
+ 1 : end
;
879 mpc8220_fec_set_hwaddr (fec2
, env_enet1addr
);
886 /* MII-interface related functions */
887 /********************************************************************/
888 int fec8220_miiphy_read (char *devname
, u8 phyAddr
, u8 regAddr
, u16
* retVal
)
890 ethernet_regs
*eth
= (ethernet_regs
*) MMAP_FEC1
;
891 u32 reg
; /* convenient holder for the PHY register */
892 u32 phy
; /* convenient holder for the PHY */
893 int timeout
= 0xffff;
896 * reading from any PHY's register is done by properly
897 * programming the FEC's MII data register.
899 reg
= regAddr
<< FEC_MII_DATA_RA_SHIFT
;
900 phy
= phyAddr
<< FEC_MII_DATA_PA_SHIFT
;
903 (FEC_MII_DATA_ST
| FEC_MII_DATA_OP_RD
| FEC_MII_DATA_TA
| phy
907 * wait for the related interrupt
909 while ((timeout
--) && (!(eth
->ievent
& 0x00800000)));
913 printf ("Read MDIO failed...\n");
919 * clear mii interrupt bit
921 eth
->ievent
= 0x00800000;
924 * it's now safe to read the PHY's register
926 *retVal
= (u16
) eth
->mii_data
;
931 /********************************************************************/
932 int fec8220_miiphy_write (char *devname
, u8 phyAddr
, u8 regAddr
, u16 data
)
934 ethernet_regs
*eth
= (ethernet_regs
*) MMAP_FEC1
;
935 u32 reg
; /* convenient holder for the PHY register */
936 u32 phy
; /* convenient holder for the PHY */
937 int timeout
= 0xffff;
939 reg
= regAddr
<< FEC_MII_DATA_RA_SHIFT
;
940 phy
= phyAddr
<< FEC_MII_DATA_PA_SHIFT
;
942 eth
->mii_data
= (FEC_MII_DATA_ST
| FEC_MII_DATA_OP_WR
|
943 FEC_MII_DATA_TA
| phy
| reg
| data
);
946 * wait for the MII interrupt
948 while ((timeout
--) && (!(eth
->ievent
& 0x00800000)));
952 printf ("Write MDIO failed...\n");
958 * clear MII interrupt bit
960 eth
->ievent
= 0x00800000;
966 static u32
local_crc32 (char *string
, unsigned int crc_value
, int len
)
970 unsigned int crc
, count
;
976 * crc = 0xffffffff; * The initialized value should be 0xffffffff
980 for (i
= len
; --i
>= 0;) {
982 for (count
= 0; count
< 8; count
++) {
983 if ((c
& 0x01) ^ (crc
& 0x01)) {
985 crc
= crc
^ 0xedb88320;
994 * In big endian system, do byte swaping for crc value
1000 #endif /* CONFIG_MPC8220_FEC */