cpu/mpc512x/cpu_init.c

   1 /*
   2  * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
   3  * (C) Copyright 2007 DENX Software Engineering
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  * Derived from the MPC83xx code.
  24  *
  25  */
  26
  27 #include <common.h>
  28 #include <mpc512x.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 /*
  33  * Set up the memory map, initialize registers,
  34  */
  35 void cpu_init_f (volatile immap_t * im)
  36 {
  37         u32 ips_div;
  38
  39         /* Pointer is writable since we allocated a register for it */
  40         gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
  41
  42         /* Clear initial global data */
  43         memset ((void *) gd, 0, sizeof (gd_t));
  44
  45         /* system performance tweaking */
  46
  47 #ifdef CFG_ACR_PIPE_DEP
  48         /* Arbiter pipeline depth */
  49         im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
  50                           (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
  51 #endif
  52
  53 #ifdef CFG_ACR_RPTCNT
  54         /* Arbiter repeat count */
  55         im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) |
  56                            (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT));
  57 #endif
  58
  59         /* RSR - Reset Status Register - clear all status */
  60         gd->reset_status = im->reset.rsr;
  61         im->reset.rsr = ~(RSR_RES);
  62
  63         /*
  64          * RMR - Reset Mode Register - enable checkstop reset
  65          */
  66         im->reset.rmr = (RMR_CSRE & (1 << RMR_CSRE_SHIFT));
  67
  68         /* Set IPS-CSB divider: IPS = 1/2 CSB */
  69         ips_div = im->clk.scfr[0];
  70         ips_div &= ~(SCFR1_IPS_DIV_MASK);
  71         ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT;
  72         im->clk.scfr[0] = ips_div;
  73
  74         /*
  75          * Enable Time Base/Decrementer
  76          *
  77          * NOTICE: TB needs to be enabled as early as possible in order to
  78          * have udelay() working; if not enabled, usually leads to a hang, like
  79          * during FLASH chip identification etc.
  80          */
  81         im->sysconf.spcr |= SPCR_TBEN;
  82 }
  83
  84 int cpu_init_r (void)
  85 {
  86         return 0;
  87 }