cpu/ixp/pci.c

   1 /*
   2  * IXP PCI Init
   3  * (C) Copyright 2004 eslab.whut.edu.cn
   4  * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25
  26 #include <common.h>
  27
  28 #ifdef CONFIG_PCI
  29
  30 #include <asm/processor.h>
  31 #include <asm/io.h>
  32 #include <pci.h>
  33 #include <asm/arch/ixp425.h>
  34 #include <asm/arch/ixp425pci.h>
  35
  36 static void non_prefetch_read (unsigned int addr, unsigned int cmd,
  37                                unsigned int *data);
  38 static void non_prefetch_write (unsigned int addr, unsigned int cmd,
  39                                 unsigned int data);
  40 static void configure_pins (void);
  41 static void sys_pci_gpio_clock_config (void);
  42 static void pci_bus_scan (void);
  43 static int pci_device_exists (unsigned int deviceNo);
  44 static void sys_pci_bar_info_get (unsigned int devnum, unsigned int bus,
  45                                   unsigned int dev, unsigned int func);
  46 static void sys_pci_device_bars_write (void);
  47 static void calc_bars (PciBar * Bars[], unsigned int nBars,
  48                        unsigned int startAddr);
  49
  50 #define PCI_MEMORY_BUS          0x00000000
  51 #define PCI_MEMORY_PHY          0x48000000
  52 #define PCI_MEMORY_SIZE         0x04000000
  53
  54 #define PCI_MEM_BUS             0x40000000
  55 #define PCI_MEM_PHY             0x00000000
  56 #define PCI_MEM_SIZE            0x04000000
  57
  58 #define PCI_IO_BUS              0x40000000
  59 #define PCI_IO_PHY              0x50000000
  60 #define PCI_IO_SIZE             0x10000000
  61
  62 struct pci_controller hose;
  63
  64 unsigned int nDevices;
  65 unsigned int nMBars;
  66 unsigned int nIOBars;
  67 PciBar *memBars[IXP425_PCI_MAX_BAR];
  68 PciBar *ioBars[IXP425_PCI_MAX_BAR];
  69 PciDevice devices[IXP425_PCI_MAX_FUNC_ON_BUS];
  70
  71 int pci_read_config_dword (pci_dev_t dev, int where, unsigned int *val)
  72 {
  73         unsigned int retval;
  74         unsigned int addr;
  75
  76         /*address bits 31:28 specify the device 10:8 specify the function */
  77         /*Set the address to be read */
  78         addr = BIT ((31 - dev)) | (where & ~3);
  79         non_prefetch_read (addr, NP_CMD_CONFIGREAD, &retval);
  80
  81         *val = retval;
  82
  83         return (OK);
  84 }
  85
  86 int pci_read_config_word (pci_dev_t dev, int where, unsigned short *val)
  87 {
  88         unsigned int n;
  89         unsigned int retval;
  90         unsigned int addr;
  91         unsigned int byteEnables;
  92
  93         n = where % 4;
  94         /*byte enables are 4 bits active low, the position of each
  95            bit maps to the byte that it enables */
  96         byteEnables =
  97                 (~(BIT (n) | BIT ((n + 1)))) &
  98                 IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
  99         byteEnables = byteEnables << PCI_NP_CBE_BESL;
 100         /*address bits 31:28 specify the device 10:8 specify the function */
 101         /*Set the address to be read */
 102         addr = BIT ((31 - dev)) | (where & ~3);
 103         non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
 104
 105         /*Pick out the word we are interested in */
 106         *val = (retval >> (8 * n));
 107
 108         return (OK);
 109 }
 110
 111 int pci_read_config_byte (pci_dev_t dev, int where, unsigned char *val)
 112 {
 113         unsigned int retval;
 114         unsigned int n;
 115         unsigned int byteEnables;
 116         unsigned int addr;
 117
 118         n = where % 4;
 119         /*byte enables are 4 bits, active low, the position of each
 120            bit maps to the byte that it enables */
 121         byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
 122         byteEnables = byteEnables << PCI_NP_CBE_BESL;
 123
 124         /*address bits 31:28 specify the device, 10:8 specify the function */
 125         /*Set the address to be read */
 126         addr = BIT ((31 - dev)) | (where & ~3);
 127         non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
 128         /*Pick out the byte we are interested in */
 129         *val = (retval >> (8 * n));
 130
 131         return (OK);
 132 }
 133
 134 int pci_write_config_byte (pci_dev_t dev, int where, unsigned char val)
 135 {
 136         unsigned int addr;
 137         unsigned int byteEnables;
 138         unsigned int n;
 139         unsigned int ldata;
 140
 141         n = where % 4;
 142         /*byte enables are 4 bits active low, the position of each
 143            bit maps to the byte that it enables */
 144         byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
 145         byteEnables = byteEnables << PCI_NP_CBE_BESL;
 146         ldata = val << (8 * n);
 147         /*address bits 31:28 specify the device 10:8 specify the function */
 148         /*Set the address to be written */
 149         addr = BIT ((31 - dev)) | (where & ~3);
 150         non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
 151
 152         return (OK);
 153 }
 154
 155 int pci_write_config_word (pci_dev_t dev, int where, unsigned short val)
 156 {
 157         unsigned int addr;
 158         unsigned int byteEnables;
 159         unsigned int n;
 160         unsigned int ldata;
 161
 162         n = where % 4;
 163         /*byte enables are 4 bits active low, the position of each
 164            bit maps to the byte that it enables */
 165         byteEnables =
 166                 (~(BIT (n) | BIT ((n + 1)))) &
 167                 IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
 168         byteEnables = byteEnables << PCI_NP_CBE_BESL;
 169         ldata = val << (8 * n);
 170         /*address bits 31:28 specify the device 10:8 specify the function */
 171         /*Set the address to be written */
 172         addr = BIT (31 - dev) | (where & ~3);
 173         non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
 174
 175         return (OK);
 176 }
 177
 178 int pci_write_config_dword (pci_dev_t dev, int where, unsigned int val)
 179 {
 180         unsigned int addr;
 181
 182         /*address bits 31:28 specify the device 10:8 specify the function */
 183         /*Set the address to be written */
 184         addr = BIT (31 - dev) | (where & ~3);
 185         non_prefetch_write (addr, NP_CMD_CONFIGWRITE, val);
 186
 187         return (OK);
 188 }
 189
 190 void non_prefetch_read (unsigned int addr,
 191                         unsigned int cmd, unsigned int *data)
 192 {
 193         REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr);
 194
 195         /*set up and execute the read */
 196         REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd);
 197
 198         /*The result of the read is now in np_rdata */
 199         REG_READ (PCI_CSR_BASE, PCI_NP_RDATA_OFFSET, *data);
 200
 201         return;
 202 }
 203
 204 void non_prefetch_write (unsigned int addr,
 205                          unsigned int cmd, unsigned int data)
 206 {
 207
 208         REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr);
 209         /*set up the write */
 210         REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd);
 211         /*Execute the write by writing to NP_WDATA */
 212         REG_WRITE (PCI_CSR_BASE, PCI_NP_WDATA_OFFSET, data);
 213
 214         return;
 215 }
 216
 217 /*
 218  * PCI controller config registers are accessed through these functions
 219  * i.e. these allow us to set up our own BARs etc.
 220  */
 221 void crp_read (unsigned int offset, unsigned int *data)
 222 {
 223         REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET, offset);
 224         REG_READ (PCI_CSR_BASE, PCI_CRP_RDATA_OFFSET, *data);
 225 }
 226
 227 void crp_write (unsigned int offset, unsigned int data)
 228 {
 229         /*The CRP address register bit 16 indicates that we want to do a write */
 230         REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET,
 231                    PCI_CRP_WRITE | offset);
 232         REG_WRITE (PCI_CSR_BASE, PCI_CRP_WDATA_OFFSET, data);
 233 }
 234
 235 /*struct pci_controller *hose*/
 236 void pci_ixp_init (struct pci_controller *hose)
 237 {
 238         unsigned int regval;
 239
 240         hose->first_busno = 0;
 241         hose->last_busno = 0x00;
 242
 243         /* System memory space */
 244         pci_set_region (hose->regions + 0,
 245                         PCI_MEMORY_BUS,
 246                         PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_MEMORY);
 247
 248         /* PCI memory space */
 249         pci_set_region (hose->regions + 1,
 250                         PCI_MEM_BUS,
 251                         PCI_MEM_PHY, PCI_MEM_SIZE, PCI_REGION_MEM);
 252         /* PCI I/O space */
 253         pci_set_region (hose->regions + 2,
 254                         PCI_IO_BUS, PCI_IO_PHY, PCI_IO_SIZE, PCI_REGION_IO);
 255
 256         hose->region_count = 3;
 257
 258         pci_register_hose (hose);
 259
 260 /*
 261  ==========================================================
 262                 Init IXP PCI
 263  ==========================================================
 264 */
 265         REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
 266         regval |= 1 << 2;
 267         REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
 268
 269         configure_pins ();
 270
 271         READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval);
 272         WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval & (~(1 << 13)));
 273         udelay (533);
 274         sys_pci_gpio_clock_config ();
 275         REG_WRITE (PCI_CSR_BASE, PCI_INTEN_OFFSET, 0);
 276         udelay (100);
 277         READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval);
 278         WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval | (1 << 13));
 279         udelay (533);
 280         crp_write (PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_0_DEFAULT);
 281         crp_write (PCI_CFG_BASE_ADDRESS_1, IXP425_PCI_BAR_1_DEFAULT);
 282         crp_write (PCI_CFG_BASE_ADDRESS_2, IXP425_PCI_BAR_2_DEFAULT);
 283         crp_write (PCI_CFG_BASE_ADDRESS_3, IXP425_PCI_BAR_3_DEFAULT);
 284         crp_write (PCI_CFG_BASE_ADDRESS_4, IXP425_PCI_BAR_4_DEFAULT);
 285         crp_write (PCI_CFG_BASE_ADDRESS_5, IXP425_PCI_BAR_5_DEFAULT);
 286         /*Setup PCI-AHB and AHB-PCI address mappings */
 287         REG_WRITE (PCI_CSR_BASE, PCI_AHBMEMBASE_OFFSET,
 288                    IXP425_PCI_AHBMEMBASE_DEFAULT);
 289
 290         REG_WRITE (PCI_CSR_BASE, PCI_AHBIOBASE_OFFSET,
 291                    IXP425_PCI_AHBIOBASE_DEFAULT);
 292
 293         REG_WRITE (PCI_CSR_BASE, PCI_PCIMEMBASE_OFFSET,
 294                    IXP425_PCI_PCIMEMBASE_DEFAULT);
 295
 296         crp_write (PCI_CFG_SUB_VENDOR_ID, IXP425_PCI_SUB_VENDOR_SYSTEM);
 297
 298         REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
 299         regval |= PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS;
 300         REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
 301         crp_write (PCI_CFG_COMMAND, PCI_CFG_CMD_MAE | PCI_CFG_CMD_BME);
 302         udelay (1000);
 303
 304         pci_write_config_word (0, PCI_CFG_COMMAND, INITIAL_PCI_CMD);
 305         REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE
 306                    | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE);
 307 #ifdef CONFIG_PCI_SCAN_SHOW
 308         printf ("Device  bus  dev  func  deviceID  vendorID \n");
 309 #endif
 310         pci_bus_scan ();
 311 }
 312
 313 void configure_pins (void)
 314 {
 315         unsigned int regval;
 316
 317         /* Disable clock on GPIO PIN 14 */
 318         READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
 319         WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval & (~(1 << 8)));
 320         READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
 321
 322         READ_GPIO_REG (IXP425_GPIO_GPOER, regval);
 323         WRITE_GPIO_REG (IXP425_GPIO_GPOER,
 324                         (((~(3 << 13)) & regval) | (0xf << 8)));
 325         READ_GPIO_REG (IXP425_GPIO_GPOER, regval);
 326
 327         READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval);
 328         WRITE_GPIO_REG (IXP425_GPIO_GPIT2R,
 329                         (regval &
 330                          ((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1)));
 331         READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval);
 332
 333         READ_GPIO_REG (IXP425_GPIO_GPISR, regval);
 334         WRITE_GPIO_REG (IXP425_GPIO_GPISR, (regval | (0xf << 8)));
 335         READ_GPIO_REG (IXP425_GPIO_GPISR, regval);
 336 }
 337
 338 void sys_pci_gpio_clock_config (void)
 339 {
 340         unsigned int regval;
 341
 342         READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
 343         regval |= 0x1 << 4;
 344         WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
 345         READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
 346         regval |= 0x1 << 8;
 347         WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
 348 }
 349
 350 void pci_bus_scan (void)
 351 {
 352         unsigned int bus = 0, dev, func = 0;
 353         unsigned short data16;
 354         unsigned int data32;
 355         unsigned char intPin;
 356
 357         /* Assign first device to ourselves */
 358         devices[0].bus = 0;
 359         devices[0].device = 0;
 360         devices[0].func = 0;
 361
 362         crp_read (PCI_CFG_VENDOR_ID, &data32);
 363
 364         devices[0].vendor_id = data32 & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK;
 365         devices[0].device_id = data32 >> 16;
 366         devices[0].error = FALSE;
 367         devices[0].bar[NO_BAR].size = 0;        /*dummy - required */
 368
 369         nDevices = 1;
 370
 371         nMBars = 0;
 372         nIOBars = 0;
 373
 374         for (dev = 0; dev < IXP425_PCI_MAX_DEV; dev++) {
 375
 376                 /*Check whether a device is present */
 377                 if (pci_device_exists (dev) != TRUE) {
 378
 379                         /*Clear error bits in ISR, write 1 to clear */
 380                         REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE
 381                                    | PCI_ISR_PFE | PCI_ISR_PPE |
 382                                    PCI_ISR_AHBE);
 383                         continue;
 384                 }
 385
 386                 /*A device is present, add an entry to the array */
 387                 devices[nDevices].bus = bus;
 388                 devices[nDevices].device = dev;
 389                 devices[nDevices].func = func;
 390
 391                 pci_read_config_word (dev, PCI_CFG_VENDOR_ID, &data16);
 392
 393                 devices[nDevices].vendor_id = data16;
 394
 395                 pci_read_config_word (dev, PCI_CFG_DEVICE_ID, &data16);
 396                 devices[nDevices].device_id = data16;
 397
 398                 /*The device is functioning correctly, set error to FALSE */
 399                 devices[nDevices].error = FALSE;
 400
 401                 /*Figure out what BARs are on this device */
 402                 sys_pci_bar_info_get (nDevices, bus, dev, func);
 403                 /*Figure out what INTX# line the card uses */
 404                 pci_read_config_byte (dev, PCI_CFG_DEV_INT_PIN, &intPin);
 405
 406                 /*assign the appropriate irq line */
 407                 if (intPin > PCI_IRQ_LINES) {
 408                         devices[nDevices].error = TRUE;
 409                 } else if (intPin != 0) {
 410                         /*This device uses an interrupt line */
 411                         /*devices[nDevices].irq = ixp425PciIntTranslate[dev][intPin-1]; */
 412                         devices[nDevices].irq = intPin;
 413                 }
 414 #ifdef CONFIG_PCI_SCAN_SHOW
 415                 printf ("%06d    %03d %03d %04d  %08d      %08x\n", nDevices,
 416                         devices[nDevices].vendor_id);
 417 #endif
 418                 nDevices++;
 419
 420         }
 421
 422         calc_bars (memBars, nMBars, IXP425_PCI_BAR_MEM_BASE);
 423         sys_pci_device_bars_write ();
 424
 425         REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE
 426                    | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE);
 427 }
 428
 429 void sys_pci_bar_info_get (unsigned int devnum,
 430                            unsigned int bus,
 431                            unsigned int dev, unsigned int func)
 432 {
 433         unsigned int data32;
 434         unsigned int tmp;
 435         unsigned int size;
 436
 437         pci_write_config_dword (devnum,
 438                                 PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_QUERY);
 439         pci_read_config_dword (devnum, PCI_CFG_BASE_ADDRESS_0, &data32);
 440
 441         devices[devnum].bar[0].address = (data32 & 1);
 442
 443         if (data32 & 1) {
 444                 /* IO space */
 445                 tmp = data32 & ~0x3;
 446                 size = ~(tmp - 1);
 447                 devices[devnum].bar[0].size = size;
 448
 449                 if (nIOBars < IXP425_PCI_MAX_BAR) {
 450                         ioBars[nIOBars++] = &devices[devnum].bar[0];
 451                 }
 452         } else {
 453                 /* Mem space */
 454                 tmp = data32 & ~IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
 455                 size = ~(tmp - 1);
 456                 devices[devnum].bar[0].size = size;
 457
 458                 if (nMBars < IXP425_PCI_MAX_BAR) {
 459                         memBars[nMBars++] = &devices[devnum].bar[0];
 460                 } else {
 461                         devices[devnum].error = TRUE;
 462                 }
 463
 464         }
 465
 466         devices[devnum].bar[1].size = 0;
 467 }
 468
 469 void sortBars (PciBar * Bars[], unsigned int nBars)
 470 {
 471         unsigned int i, j;
 472         PciBar *tmp;
 473
 474         if (nBars == 0) {
 475                 return;
 476         }
 477
 478         /* Sort biggest to smallest */
 479         for (i = 0; i < nBars - 1; i++) {
 480                 for (j = i + 1; j < nBars; j++) {
 481                         if (Bars[j]->size > Bars[i]->size) {
 482                                 /* swap them */
 483                                 tmp = Bars[i];
 484                                 Bars[i] = Bars[j];
 485                                 Bars[j] = tmp;
 486                         }
 487                 }
 488         }
 489 }
 490
 491 void calc_bars (PciBar * Bars[], unsigned int nBars, unsigned int startAddr)
 492 {
 493         unsigned int i;
 494
 495         if (nBars == 0) {
 496                 return;
 497         }
 498
 499         for (i = 0; i < nBars; i++) {
 500                 Bars[i]->address |= startAddr;
 501                 startAddr += Bars[i]->size;
 502         }
 503 }
 504
 505 void sys_pci_device_bars_write (void)
 506 {
 507         unsigned int i;
 508         int addr;
 509
 510         for (i = 1; i < nDevices; i++) {
 511                 if (devices[i].error) {
 512                         continue;
 513                 }
 514
 515                 pci_write_config_dword (devices[i].device,
 516                                         PCI_CFG_BASE_ADDRESS_0,
 517                                         devices[i].bar[0].address);
 518                 addr = BIT (31 - devices[i].device) |
 519                         (0 << PCI_NP_AD_FUNCSL) |
 520                         (PCI_CFG_BASE_ADDRESS_0 & ~3);
 521                 pci_write_config_dword (devices[i].device,
 522                                         PCI_CFG_DEV_INT_LINE, devices[i].irq);
 523
 524                 pci_write_config_word (devices[i].device,
 525                                        PCI_CFG_COMMAND, INITIAL_PCI_CMD);
 526
 527         }
 528 }
 529
 530
 531 int pci_device_exists (unsigned int deviceNo)
 532 {
 533         unsigned int vendorId;
 534         unsigned int regval;
 535
 536         pci_read_config_dword (deviceNo, PCI_CFG_VENDOR_ID, &vendorId);
 537
 538         /* There are two ways to find out an empty device.
 539          *   1. check Master Abort bit after the access.
 540          *   2. check whether the vendor id read back is 0x0.
 541          */
 542         REG_READ (PCI_CSR_BASE, PCI_ISR_OFFSET, regval);
 543         if ((vendorId != 0x0) && ((regval & PCI_ISR_PFE) == 0)) {
 544                 return TRUE;
 545         }
 546         /*no device present, make sure that the master abort bit is reset */
 547
 548         REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PFE);
 549         return FALSE;
 550 }
 551
 552 pci_dev_t pci_find_devices (struct pci_device_id * ids, int devNo)
 553 {
 554         unsigned int i;
 555         unsigned int devdidvid;
 556         unsigned int didvid;
 557         unsigned int vendorId, deviceId;
 558
 559         vendorId = ids->vendor;
 560         deviceId = ids->device;
 561         didvid = ((deviceId << 16) & IXP425_PCI_TOP_WORD_OF_LONG_MASK) |
 562                 (vendorId & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK);
 563
 564         for (i = devNo + 1; i < nDevices; i++) {
 565
 566                 pci_read_config_dword (devices[i].device, PCI_CFG_VENDOR_ID,
 567                                        &devdidvid);
 568
 569                 if (devdidvid == didvid) {
 570                         return devices[i].device;
 571                 }
 572         }
 573         return -1;
 574 }
 575 #endif  /* CONFIG_PCI */