cpu/blackfin/reset.c

   1 /*
   2  * reset.c - logic for resetting the cpu
   3  *
   4  * Copyright (c) 2005-2008 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <common.h>
  10 #include <command.h>
  11 #include <asm/blackfin.h>
  12 #include "cpu.h"
  13
  14 /* A system soft reset makes external memory unusable so force
  15  * this function into L1.  We use the compiler ssync here rather
  16  * than SSYNC() because it's safe (no interrupts and such) and
  17  * we save some L1.  We do not need to force sanity in the SYSCR
  18  * register as the BMODE selection bit is cleared by the soft
  19  * reset while the Core B bit (on dual core parts) is cleared by
  20  * the core reset.
  21  */
  22 __attribute__ ((__l1_text__, __noreturn__))
  23 void bfin_reset(void)
  24 {
  25         /* Wait for completion of "system" events such as cache line
  26          * line fills so that we avoid infinite stalls later on as
  27          * much as possible.  This code is in L1, so it won't trigger
  28          * any such event after this point in time.
  29          */
  30         __builtin_bfin_ssync();
  31
  32         while (1) {
  33                 /* Initiate System software reset. */
  34                 bfin_write_SWRST(0x7);
  35
  36                 /* Due to the way reset is handled in the hardware, we need
  37                  * to delay for 7 SCLKS.  The only reliable way to do this is
  38                  * to calculate the CCLK/SCLK ratio and multiply 7.  For now,
  39                  * we'll assume worse case which is a 1:15 ratio.
  40                  */
  41                 asm(
  42                         "LSETUP (1f, 1f) LC0 = %0\n"
  43                         "1: nop;"
  44                         :
  45                         : "a" (15 * 7)
  46                         : "LC0", "LB0", "LT0"
  47                 );
  48
  49                 /* Clear System software reset */
  50                 bfin_write_SWRST(0);
  51
  52                 /* Wait for the SWRST write to complete.  Cannot rely on SSYNC
  53                  * though as the System state is all reset now.
  54                  */
  55                 asm(
  56                         "LSETUP (1f, 1f) LC1 = %0\n"
  57                         "1: nop;"
  58                         :
  59                         : "a" (15 * 1)
  60                         : "LC1", "LB1", "LT1"
  61                 );
  62
  63                 /* Issue core reset */
  64                 asm("raise 1");
  65         }
  66 }
  67
  68 /* We need to trampoline ourselves up into L1 since our linker
  69  * does not have relaxtion support and will only generate a
  70  * PC relative call with a 25 bit immediate.  This is not enough
  71  * to get us from the top of SDRAM into L1.
  72  */
  73 __attribute__ ((__noreturn__))
  74 static inline void bfin_reset_trampoline(void)
  75 {
  76         if (board_reset)
  77                 board_reset();
  78         while (1)
  79                 asm("jump (%0);" : : "a" (bfin_reset));
  80 }
  81
  82 __attribute__ ((__noreturn__))
  83 void bfin_reset_or_hang(void)
  84 {
  85 #ifdef CONFIG_PANIC_HANG
  86         hang();
  87 #else
  88         bfin_reset_trampoline();
  89 #endif
  90 }
  91
  92 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  93 {
  94         bfin_reset_trampoline();
  95         return 0;
  96 }