cpu/at32ap/hsdramc.c

   1 /*
   2  * Copyright (C) 2005-2006 Atmel Corporation
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22 #include <common.h>
  23
  24 #ifdef CFG_HSDRAMC
  25 #include <asm/io.h>
  26 #include <asm/sdram.h>
  27
  28 #include <asm/arch/clk.h>
  29 #include <asm/arch/memory-map.h>
  30
  31 #include "hsdramc1.h"
  32
  33 unsigned long sdram_init(const struct sdram_info *info)
  34 {
  35         unsigned long *sdram = (unsigned long *)uncached(info->phys_addr);
  36         unsigned long sdram_size;
  37         unsigned long tmp;
  38         unsigned long bus_hz;
  39         unsigned int i;
  40
  41         if (!info->refresh_period)
  42                 panic("ERROR: SDRAM refresh period == 0. "
  43                                 "Please update the board code\n");
  44
  45         tmp = (HSDRAMC1_BF(NC, info->col_bits - 8)
  46                | HSDRAMC1_BF(NR, info->row_bits - 11)
  47                | HSDRAMC1_BF(NB, info->bank_bits - 1)
  48                | HSDRAMC1_BF(CAS, info->cas)
  49                | HSDRAMC1_BF(TWR, info->twr)
  50                | HSDRAMC1_BF(TRC, info->trc)
  51                | HSDRAMC1_BF(TRP, info->trp)
  52                | HSDRAMC1_BF(TRCD, info->trcd)
  53                | HSDRAMC1_BF(TRAS, info->tras)
  54                | HSDRAMC1_BF(TXSR, info->txsr));
  55
  56 #ifdef CFG_SDRAM_16BIT
  57         tmp |= HSDRAMC1_BIT(DBW);
  58         sdram_size = 1 << (info->row_bits + info->col_bits
  59                            + info->bank_bits + 1);
  60 #else
  61         sdram_size = 1 << (info->row_bits + info->col_bits
  62                            + info->bank_bits + 2);
  63 #endif
  64
  65         hsdramc1_writel(CR, tmp);
  66
  67         /*
  68          * Initialization sequence for SDRAM, from the data sheet:
  69          *
  70          * 1. A minimum pause of 200 us is provided to precede any
  71          *    signal toggle.
  72          */
  73         udelay(200);
  74
  75         /*
  76          * 2. A Precharge All command is issued to the SDRAM
  77          */
  78         hsdramc1_writel(MR, HSDRAMC1_MODE_BANKS_PRECHARGE);
  79         hsdramc1_readl(MR);
  80         writel(0, sdram);
  81
  82         /*
  83          * 3. Eight auto-refresh (CBR) cycles are provided
  84          */
  85         hsdramc1_writel(MR, HSDRAMC1_MODE_AUTO_REFRESH);
  86         hsdramc1_readl(MR);
  87         for (i = 0; i < 8; i++)
  88                 writel(0, sdram);
  89
  90         /*
  91          * 4. A mode register set (MRS) cycle is issued to program
  92          *    SDRAM parameters, in particular CAS latency and burst
  93          *    length.
  94          *
  95          * CAS from info struct, burst length 1, serial burst type
  96          */
  97         hsdramc1_writel(MR, HSDRAMC1_MODE_LOAD_MODE);
  98         hsdramc1_readl(MR);
  99         writel(0, sdram + (info->cas << 4));
 100
 101         /*
 102          * 5. A Normal Mode command is provided, 3 clocks after tMRD
 103          *    is met.
 104          *
 105          * From the timing diagram, it looks like tMRD is 3
 106          * cycles...try a dummy read from the peripheral bus.
 107          */
 108         hsdramc1_readl(MR);
 109         hsdramc1_writel(MR, HSDRAMC1_MODE_NORMAL);
 110         hsdramc1_readl(MR);
 111         writel(0, sdram);
 112
 113         /*
 114          * 6. Write refresh rate into SDRAMC refresh timer count
 115          *    register (refresh rate = timing between refresh cycles).
 116          *
 117          * 15.6 us is a typical value for a burst of length one
 118          */
 119         bus_hz = get_sdram_clk_rate();
 120         hsdramc1_writel(TR, info->refresh_period);
 121
 122         printf("SDRAM: %u MB at address 0x%08lx\n",
 123                sdram_size >> 20, info->phys_addr);
 124
 125         printf("Testing SDRAM...");
 126         for (i = 0; i < sdram_size / 4; i++)
 127                 sdram[i] = i;
 128
 129         for (i = 0; i < sdram_size / 4; i++) {
 130                 tmp = sdram[i];
 131                 if (tmp != i) {
 132                         printf("FAILED at address 0x%08lx\n",
 133                                info->phys_addr + i * 4);
 134                         printf("SDRAM: read 0x%lx, expected 0x%lx\n", tmp, i);
 135                         return 0;
 136                 }
 137         }
 138
 139         puts("OK\n");
 140
 141         return sdram_size;
 142 }
 143
 144 #endif /* CFG_HSDRAMC */