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dynenv-harden.patch
[u-boot-openmoko/mini2440.git] / board / tqm8272 / tqm8272.c
blob7bd64012c4ba35a757ad2fe73e190c791b497b34
1 /*
2 * (C) Copyright 2006
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #include <common.h>
25 #include <ioports.h>
26 #include <mpc8260.h>
27
28 #include <command.h>
29 #ifdef CONFIG_PCI
30 #include <pci.h>
31 #include <asm/m8260_pci.h>
32 #endif
33 #if CONFIG_OF_FLAT_TREE
34 #include <ft_build.h>
35 #include <image.h>
36 #endif
37
38 #if 0
39 #define deb_printf(fmt,arg...) \
40 printf ("TQM8272 %s %s: " fmt,__FILE__, __FUNCTION__, ##arg)
41 #else
42 #define deb_printf(fmt,arg...) \
43 do { } while (0)
44 #endif
45
46 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
47 unsigned long board_get_cpu_clk_f (void);
48 #endif
49
50 /*
51 * I/O Port configuration table
52 *
53 * if conf is 1, then that port pin will be configured at boot time
54 * according to the five values podr/pdir/ppar/psor/pdat for that entry
55 */
56
57 const iop_conf_t iop_conf_tab[4][32] = {
58
59 /* Port A configuration */
60 { /* conf ppar psor pdir podr pdat */
61 /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */
62 /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */
63 /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */
64 /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */
65 /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */
66 /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */
67 /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
68 /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
69 /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
70 /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
71 /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
72 /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
73 /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
74 /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
75 /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */
76 /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */
77 /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */
78 /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */
79 /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */
80 /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */
81 /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */
82 /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */
83 /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
84 /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
85 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
86 /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
87 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
88 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
89 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
90 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
91 /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
92 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
93 },
94
95 /* Port B configuration */
96 { /* conf ppar psor pdir podr pdat */
97 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
98 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
99 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
100 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
101 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
102 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
103 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
104 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
105 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
106 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
107 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
108 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
109 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
110 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
111 /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
112 /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
113 /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
114 /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
115 /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
116 /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
117 /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
118 /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
119 /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
120 /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
121 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
122 /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
123 /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
124 /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
125 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
126 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
127 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
128 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
129 },
130
131 /* Port C */
132 { /* conf ppar psor pdir podr pdat */
133 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
134 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
135 /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
136 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
137 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
138 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
139 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
140 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
141 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
142 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
143 /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
144 /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
145 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
146 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
147 /* PC17 */ { 1, 0, 0, 1, 0, 0 }, /* PC17 MDC */
148 /* PC16 */ { 1, 0, 0, 0, 0, 0 }, /* PC16 MDIO*/
149 /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
150 /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
151 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
152 /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
153 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
154 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* PC10 */
155 /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* PC9 */
156 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
157 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
158 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
159 /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* PC5 SMC1 TXD */
160 /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* PC4 SMC1 RXD */
161 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
162 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
163 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
164 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
165 },
166
167 /* Port D */
168 { /* conf ppar psor pdir podr pdat */
169 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
170 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
171 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
172 /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
173 /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
174 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
175 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
176 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
177 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
178 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
179 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
180 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
181 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
182 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
183 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
184 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
185 #if defined(CONFIG_SOFT_I2C)
186 /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
187 /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
188 #else
189 #if defined(CONFIG_HARD_I2C)
190 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
191 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
192 #else /* normal I/O port pins */
193 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
194 /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
195 #endif
196 #endif
197 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
198 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
199 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
200 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
201 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
202 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
203 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
204 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
205 /* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PD5 */
206 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
207 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
208 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
209 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
210 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
211 }
212 };
213
214 #define _NOT_USED_ 0xFFFFFFFF
215
216 /* UPM pattern for bus clock = 66.7 MHz */
217 static const uint upmTable67[] =
218 {
219 /* Offset UPM Read Single RAM array entry -> NAND Read Data */
220 /* 0x00 */ 0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000,
221 /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
222
223 /* UPM Read Burst RAM array entry -> unused */
224 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
225 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
226
227 /* UPM Read Burst RAM array entry -> unused */
228 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
229 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
230
231 /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
232 /* 0x18 */ 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00,
233 /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
234
235 /* UPM Write Burst RAM array entry -> unused */
236 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
237 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
238 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
239 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
240
241 /* UPM Refresh Timer RAM array entry -> unused */
242 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
243 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
244 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
245
246 /* UPM Exception RAM array entry -> unsused */
247 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
248 };
249
250 /* UPM pattern for bus clock = 100 MHz */
251 static const uint upmTable100[] =
252 {
253 /* Offset UPM Read Single RAM array entry -> NAND Read Data */
254 /* 0x00 */ 0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
255 /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
256
257 /* UPM Read Burst RAM array entry -> unused */
258 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
259 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
260
261 /* UPM Read Burst RAM array entry -> unused */
262 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
263 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
264
265 /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
266 /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00,
267 /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
268
269 /* UPM Write Burst RAM array entry -> unused */
270 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
271 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
272 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
273 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
274
275 /* UPM Refresh Timer RAM array entry -> unused */
276 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
277 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
278 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
279
280 /* UPM Exception RAM array entry -> unsused */
281 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
282 };
283
284 /* UPM pattern for bus clock = 133.3 MHz */
285 static const uint upmTable133[] =
286 {
287 /* Offset UPM Read Single RAM array entry -> NAND Read Data */
288 /* 0x00 */ 0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
289 /* 0x04 */ 0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00,
290
291 /* UPM Read Burst RAM array entry -> unused */
292 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
293 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
294
295 /* UPM Read Burst RAM array entry -> unused */
296 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
297 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
298
299 /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
300 /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00,
301 /* 0x1C */ 0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
302
303 /* UPM Write Burst RAM array entry -> unused */
304 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
305 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
306 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
307 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
308
309 /* UPM Refresh Timer RAM array entry -> unused */
310 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
311 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
312 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
313
314 /* UPM Exception RAM array entry -> unsused */
315 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
316 };
317
318 static int chipsel = 0;
319
320 /* UPM pattern for slow init */
321 static const uint upmTableSlow[] =
322 {
323 /* Offset UPM Read Single RAM array entry */
324 /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcf00, 0x00ffdc00,
325 /* 0x04 */ 0x00ffce80, 0x00ffcc00, 0x00ffee00, 0x3fffcc07,
326
327 /* UPM Read Burst RAM array entry -> unused */
328 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
329 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
330
331 /* UPM Read Burst RAM array entry -> unused */
332 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
333 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
334
335 /* UPM Write Single RAM array entry */
336 /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffef00, 0x00fffc80,
337 /* 0x1C */ 0x00fffe00, 0x00ffec00, 0x0fffef00, 0x3fffec05,
338
339 /* UPM Write Burst RAM array entry -> unused */
340 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
341 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
342 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
343 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
344
345 /* UPM Refresh Timer RAM array entry -> unused */
346 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
347 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
348 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
349
350 /* UPM Exception RAM array entry -> unused */
351 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
352 };
353
354 /* UPM pattern for fast init */
355 static const uint upmTableFast[] =
356 {
357 /* Offset UPM Read Single RAM array entry */
358 /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcd80, 0x00ffdc00,
359 /* 0x04 */ 0x00ffdc00, 0x00ffcf00, 0x00ffec00, 0x3fffcc07,
360
361 /* UPM Read Burst RAM array entry -> unused */
362 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
363 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
364
365 /* UPM Read Burst RAM array entry -> unused */
366 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
367 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
368
369 /* UPM Write Single RAM array entry */
370 /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffee80, 0x00fffc00,
371 /* 0x1C */ 0x00fffc00, 0x00ffec00, 0x0fffef00, 0x3fffec05,
372
373 /* UPM Write Burst RAM array entry -> unused */
374 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
375 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
376 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
377 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
378
379 /* UPM Refresh Timer RAM array entry -> unused */
380 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
381 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
382 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
383
384 /* UPM Exception RAM array entry -> unused */
385 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
386 };
387
388
389 /* ------------------------------------------------------------------------- */
390
391 /* Check Board Identity:
392 */
393 int checkboard (void)
394 {
395 char *p = (char *) HWIB_INFO_START_ADDR;
396
397 puts ("Board: ");
398 if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) {
399 puts (p);
400 } else {
401 puts ("No HWIB assuming TQM8272");
402 }
403 putc ('\n');
404
405 return 0;
406 }
407
408 /* ------------------------------------------------------------------------- */
409 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
410 static int get_cas_latency (void)
411 {
412 /* get it from the option -ts in CIB */
413 /* default is 3 */
414 int ret = 3;
415 int pos = 0;
416 char *p = (char *) CIB_INFO_START_ADDR;
417
418 while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
419 if (*p < ' ' || *p > '~') { /* ASCII strings! */
420 return ret;
421 }
422 if (*p == '-') {
423 if ((p[1] == 't') && (p[2] == 's')) {
424 return (p[4] - '0');
425 }
426 }
427 p++;
428 pos++;
429 }
430 return ret;
431 }
432 #endif
433
434 static ulong set_sdram_timing (volatile uint *sdmr_ptr, ulong sdmr, int col)
435 {
436 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
437 int clk = board_get_cpu_clk_f ();
438 volatile immap_t *immr = (immap_t *)CFG_IMMR;
439 int busmode = (immr->im_siu_conf.sc_bcr & BCR_EBM ? 1 : 0);
440 int cas;
441
442 sdmr = sdmr & ~(PSDMR_RFRC_MSK | PSDMR_PRETOACT_MSK | PSDMR_WRC_MSK | \
443 PSDMR_BUFCMD);
444 if (busmode) {
445 switch (clk) {
446 case 66666666:
447 sdmr |= (PSDMR_RFRC_66MHZ_60X | \
448 PSDMR_PRETOACT_66MHZ_60X | \
449 PSDMR_WRC_66MHZ_60X | \
450 PSDMR_BUFCMD_66MHZ_60X);
451 break;
452 case 100000000:
453 sdmr |= (PSDMR_RFRC_100MHZ_60X | \
454 PSDMR_PRETOACT_100MHZ_60X | \
455 PSDMR_WRC_100MHZ_60X | \
456 PSDMR_BUFCMD_100MHZ_60X);
457 break;
458
459 }
460 } else {
461 switch (clk) {
462 case 66666666:
463 sdmr |= (PSDMR_RFRC_66MHZ_SINGLE | \
464 PSDMR_PRETOACT_66MHZ_SINGLE | \
465 PSDMR_WRC_66MHZ_SINGLE | \
466 PSDMR_BUFCMD_66MHZ_SINGLE);
467 break;
468 case 100000000:
469 sdmr |= (PSDMR_RFRC_100MHZ_SINGLE | \
470 PSDMR_PRETOACT_100MHZ_SINGLE | \
471 PSDMR_WRC_100MHZ_SINGLE | \
472 PSDMR_BUFCMD_100MHZ_SINGLE);
473 break;
474 case 133333333:
475 sdmr |= (PSDMR_RFRC_133MHZ_SINGLE | \
476 PSDMR_PRETOACT_133MHZ_SINGLE | \
477 PSDMR_WRC_133MHZ_SINGLE | \
478 PSDMR_BUFCMD_133MHZ_SINGLE);
479 break;
480 }
481 }
482 cas = get_cas_latency();
483 sdmr &=~ (PSDMR_CL_MSK | PSDMR_LDOTOPRE_MSK);
484 sdmr |= cas;
485 sdmr |= ((cas - 1) << 6);
486 return sdmr;
487 #else
488 return sdmr;
489 #endif
490 }
491
492 /* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
493 *
494 * This routine performs standard 8260 initialization sequence
495 * and calculates the available memory size. It may be called
496 * several times to try different SDRAM configurations on both
497 * 60x and local buses.
498 */
499 static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
500 ulong orx, volatile uchar * base, int col)
501 {
502 volatile uchar c = 0xff;
503 volatile uint *sdmr_ptr;
504 volatile uint *orx_ptr;
505 ulong maxsize, size;
506 int i;
507
508 /* We must be able to test a location outsize the maximum legal size
509 * to find out THAT we are outside; but this address still has to be
510 * mapped by the controller. That means, that the initial mapping has
511 * to be (at least) twice as large as the maximum expected size.
512 */
513 maxsize = (1 + (~orx | 0x7fff)) / 2;
514
515 /* Since CFG_SDRAM_BASE is always 0 (??), we assume that
516 * we are configuring CS1 if base != 0
517 */
518 sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
519 orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
520
521 *orx_ptr = orx;
522 sdmr = set_sdram_timing (sdmr_ptr, sdmr, col);
523 /*
524 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
525 *
526 * "At system reset, initialization software must set up the
527 * programmable parameters in the memory controller banks registers
528 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
529 * system software should execute the following initialization sequence
530 * for each SDRAM device.
531 *
532 * 1. Issue a PRECHARGE-ALL-BANKS command
533 * 2. Issue eight CBR REFRESH commands
534 * 3. Issue a MODE-SET command to initialize the mode register
535 *
536 * The initial commands are executed by setting P/LSDMR[OP] and
537 * accessing the SDRAM with a single-byte transaction."
538 *
539 * The appropriate BRx/ORx registers have already been set when we
540 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
541 */
542
543 *sdmr_ptr = sdmr | PSDMR_OP_PREA;
544 *base = c;
545
546 *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
547 for (i = 0; i < 8; i++)
548 *base = c;
549
550 *sdmr_ptr = sdmr | PSDMR_OP_MRW;
551 *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */
552
553 *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
554 *base = c;
555
556 size = get_ram_size((long *)base, maxsize);
557 *orx_ptr = orx | ~(size - 1);
558
559 return (size);
560 }
561
562 long int initdram (int board_type)
563 {
564 volatile immap_t *immap = (immap_t *) CFG_IMMR;
565 volatile memctl8260_t *memctl = &immap->im_memctl;
566
567 #ifndef CFG_RAMBOOT
568 long size8, size9;
569 #endif
570 long psize, lsize;
571
572 psize = 16 * 1024 * 1024;
573 lsize = 0;
574
575 memctl->memc_psrt = CFG_PSRT;
576 memctl->memc_mptpr = CFG_MPTPR;
577
578 #ifndef CFG_RAMBOOT
579 /* 60x SDRAM setup:
580 */
581 size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
582 (uchar *) CFG_SDRAM_BASE, 8);
583 size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL,
584 (uchar *) CFG_SDRAM_BASE, 9);
585
586 if (size8 < size9) {
587 psize = size9;
588 printf ("(60x:9COL - %ld MB, ", psize >> 20);
589 } else {
590 psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
591 (uchar *) CFG_SDRAM_BASE, 8);
592 printf ("(60x:8COL - %ld MB, ", psize >> 20);
593 }
594
595 #endif /* CFG_RAMBOOT */
596
597 icache_enable ();
598
599 return (psize);
600 }
601
602
603 static inline int scanChar (char *p, int len, unsigned long *number)
604 {
605 int akt = 0;
606
607 *number = 0;
608 while (akt < len) {
609 if ((*p >= '0') && (*p <= '9')) {
610 *number *= 10;
611 *number += *p - '0';
612 p += 1;
613 } else {
614 if (*p == '-') return akt;
615 return -1;
616 }
617 akt ++;
618 }
619 return akt;
620 }
621
622 typedef struct{
623 int Bus;
624 int flash;
625 int flash_nr;
626 int ram;
627 int ram_cs;
628 int nand;
629 int nand_cs;
630 int eeprom;
631 int can;
632 unsigned long cpunr;
633 unsigned long option;
634 int SecEng;
635 int cpucl;
636 int cpmcl;
637 int buscl;
638 int busclk_real_ok;
639 int busclk_real;
640 unsigned char OK;
641 unsigned char ethaddr[20];
642 } HWIB_INFO;
643
644 HWIB_INFO hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0,
645 0, 0, 0, 0, 0, 0};
646
647 static int dump_hwib(void)
648 {
649 HWIB_INFO *hw = &hwinf;
650 volatile immap_t *immr = (immap_t *)CFG_IMMR;
651 char *s = getenv("serial#");
652
653 if (hw->OK) {
654 printf ("HWIB on %x\n", HWIB_INFO_START_ADDR);
655 printf ("serial : %s\n", s);
656 printf ("ethaddr: %s\n", hw->ethaddr);
657 printf ("FLASH : %x nr:%d\n", hw->flash, hw->flash_nr);
658 printf ("RAM : %x cs:%d\n", hw->ram, hw->ram_cs);
659 printf ("CPU : %d\n", hw->cpunr);
660 printf ("CAN : %d\n", hw->can);
661 if (hw->eeprom) printf ("EEprom : %x\n", hw->eeprom);
662 else printf ("No EEprom\n");
663 if (hw->nand) {
664 printf ("NAND : %x\n", hw->nand);
665 printf ("NAND CS: %d\n", hw->nand_cs);
666 } else { printf ("No NAND\n");}
667 printf ("Bus %s mode.\n", (hw->Bus ? "60x" : "Single PQII"));
668 printf (" real : %s\n", (immr->im_siu_conf.sc_bcr & BCR_EBM ? \
669 "60x" : "Single PQII"));
670 printf ("Option : %x\n", hw->option);
671 printf ("%s Security Engine\n", (hw->SecEng ? "with" : "no"));
672 printf ("CPM Clk: %d\n", hw->cpmcl);
673 printf ("CPU Clk: %d\n", hw->cpucl);
674 printf ("Bus Clk: %d\n", hw->buscl);
675 if (hw->busclk_real_ok) {
676 printf (" real Clk: %d\n", hw->busclk_real);
677 }
678 printf ("CAS : %d\n", get_cas_latency());
679 } else {
680 printf("HWIB @%x not OK\n", HWIB_INFO_START_ADDR);
681 }
682 return 0;
683 }
684
685 static inline int search_real_busclk (int *clk)
686 {
687 int part = 0, pos = 0;
688 char *p = (char *) CIB_INFO_START_ADDR;
689 int ok = 0;
690
691 while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
692 if (*p < ' ' || *p > '~') { /* ASCII strings! */
693 return 0;
694 }
695 switch (part) {
696 default:
697 if (*p == '-') {
698 ++part;
699 }
700 break;
701 case 3:
702 if (*p == '-') {
703 ++part;
704 break;
705 }
706 if (*p == 'b') {
707 ok = 1;
708 p++;
709 break;
710 }
711 if (ok) {
712 switch (*p) {
713 case '6':
714 *clk = 66666666;
715 return 1;
716 break;
717 case '1':
718 if (p[1] == '3') {
719 *clk = 133333333;
720 } else {
721 *clk = 100000000;
722 }
723 return 1;
724 break;
725 }
726 }
727 break;
728 }
729 p++;
730 }
731 return 0;
732 }
733
734 int analyse_hwib (void)
735 {
736 char *p = (char *) HWIB_INFO_START_ADDR;
737 int anz;
738 int part = 1, i = 0, pos = 0;
739 HWIB_INFO *hw = &hwinf;
740
741 deb_printf(" %s pointer: %p\n", __FUNCTION__, p);
742 /* Head = TQM */
743 if (*((unsigned long *)p) != (unsigned long)CFG_HWINFO_MAGIC) {
744 deb_printf("No HWIB\n");
745 return -1;
746 }
747 p += 3;
748 if (scanChar (p, 4, &hw->cpunr) < 0) {
749 deb_printf("No CPU\n");
750 return -2;
751 }
752 p +=4;
753
754 hw->flash = 0x200000 << (*p - 'A');
755 p++;
756 hw->flash_nr = *p - '0';
757 p++;
758
759 hw->ram = 0x2000000 << (*p - 'A');
760 p++;
761 if (*p == '2') {
762 hw->ram_cs = 2;
763 p++;
764 }
765
766 if (*p == 'A') hw->can = 1;
767 if (*p == 'B') hw->can = 2;
768 p +=1;
769 p +=1; /* connector */
770 if (*p != '0') {
771 hw->eeprom = 0x1000 << (*p - 'A');
772 }
773 p++;
774
775 if ((*p < '0') || (*p > '9')) {
776 /* NAND before z-option */
777 hw->nand = 0x8000000 << (*p - 'A');
778 p++;
779 hw->nand_cs = *p - '0';
780 p += 2;
781 }
782 /* z-option */
783 anz = scanChar (p, 4, &hw->option);
784 if (anz < 0) {
785 deb_printf("No option\n");
786 return -3;
787 }
788 if (hw->option & 0x8) hw->Bus = 1;
789 p += anz;
790 if (*p != '-') {
791 deb_printf("No -\n");
792 return -4;
793 }
794 p++;
795 /* C option */
796 if (*p == 'E') {
797 hw->SecEng = 1;
798 p++;
799 }
800 switch (*p) {
801 case 'M': hw->cpucl = 266666666;
802 break;
803 case 'P': hw->cpucl = 300000000;
804 break;
805 case 'T': hw->cpucl = 400000000;
806 break;
807 default:
808 deb_printf("No CPU Clk: %c\n", *p);
809 return -5;
810 break;
811 }
812 p++;
813 switch (*p) {
814 case 'I': hw->cpmcl = 200000000;
815 break;
816 case 'M': hw->cpmcl = 300000000;
817 break;
818 default:
819 deb_printf("No CPM Clk\n");
820 return -6;
821 break;
822 }
823 p++;
824 switch (*p) {
825 case 'B': hw->buscl = 66666666;
826 break;
827 case 'E': hw->buscl = 100000000;
828 break;
829 case 'F': hw->buscl = 133333333;
830 break;
831 default:
832 deb_printf("No BUS Clk\n");
833 return -7;
834 break;
835 }
836 p++;
837
838 hw->OK = 1;
839 /* search MAC Address */
840 while ((*p != '\0') && (pos < CFG_HWINFO_SIZE)) {
841 if (*p < ' ' || *p > '~') { /* ASCII strings! */
842 return 0;
843 }
844 switch (part) {
845 default:
846 if (*p == ' ') {
847 ++part;
848 i = 0;
849 }
850 break;
851 case 3: /* Copy MAC address */
852 if (*p == ' ') {
853 ++part;
854 i = 0;
855 break;
856 }
857 hw->ethaddr[i++] = *p;
858 if ((i % 3) == 2)
859 hw->ethaddr[i++] = ':';
860 break;
861
862 }
863 p++;
864 }
865
866 hw->busclk_real_ok = search_real_busclk (&hw->busclk_real);
867 return 0;
868 }
869
870 #if defined(CONFIG_GET_CPU_STR_F)
871 /* !! This routine runs from Flash */
872 char get_cpu_str_f (char *buf)
873 {
874 char *p = (char *) HWIB_INFO_START_ADDR;
875 int i = 0;
876
877 buf[i++] = 'M';
878 buf[i++] = 'P';
879 buf[i++] = 'C';
880 if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) {
881 buf[i++] = *&p[3];
882 buf[i++] = *&p[4];
883 buf[i++] = *&p[5];
884 buf[i++] = *&p[6];
885 } else {
886 buf[i++] = '8';
887 buf[i++] = '2';
888 buf[i++] = '7';
889 buf[i++] = 'x';
890 }
891 buf[i++] = 0;
892 return 0;
893 }
894 #endif
895
896 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
897 /* !! This routine runs from Flash */
898 unsigned long board_get_cpu_clk_f (void)
899 {
900 char *p = (char *) HWIB_INFO_START_ADDR;
901 int i = 0;
902
903 if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) {
904 if (search_real_busclk (&i))
905 return i;
906 }
907 return CONFIG_8260_CLKIN;
908 }
909 #endif
910
911 #if CONFIG_BOARD_EARLY_INIT_R
912
913 static int can_test (unsigned long off)
914 {
915 volatile unsigned char *base = (unsigned char *) (CFG_CAN_BASE + off);
916
917 *(base + 0x17) = 'T';
918 *(base + 0x18) = 'Q';
919 *(base + 0x19) = 'M';
920 if ((*(base + 0x17) != 'T') ||
921 (*(base + 0x18) != 'Q') ||
922 (*(base + 0x19) != 'M')) {
923 return 0;
924 }
925 return 1;
926 }
927
928 static int can_config_one (unsigned long off)
929 {
930 volatile unsigned char *ctrl = (unsigned char *) (CFG_CAN_BASE + off);
931 volatile unsigned char *cpu_if = (unsigned char *) (CFG_CAN_BASE + off + 0x02);
932 volatile unsigned char *clkout = (unsigned char *) (CFG_CAN_BASE + off + 0x1f);
933 unsigned char temp;
934
935 *cpu_if = 0x45;
936 temp = *ctrl;
937 temp |= 0x40;
938 *ctrl = temp;
939 *clkout = 0x20;
940 temp = *ctrl;
941 temp &= ~0x40;
942 *ctrl = temp;
943 return 0;
944 }
945
946 static int can_config (void)
947 {
948 int ret = 0;
949 can_config_one (0);
950 if (hwinf.can == 2) {
951 can_config_one (0x100);
952 }
953 /* make Test if they really there */
954 ret += can_test (0);
955 ret += can_test (0x100);
956 return ret;
957 }
958
959 static int init_can (void)
960 {
961 volatile immap_t * immr = (immap_t *)CFG_IMMR;
962 volatile memctl8260_t *memctl = &immr->im_memctl;
963 int count = 0;
964
965 if ((hwinf.OK) && (hwinf.can)) {
966 memctl->memc_or4 = CFG_CAN_OR;
967 memctl->memc_br4 = CFG_CAN_BR;
968 /* upm Init */
969 upmconfig (UPMC, (uint *) upmTableFast,
970 sizeof (upmTableFast) / sizeof (uint));
971 memctl->memc_mcmr = (MxMR_DSx_3_CYCL |
972 MxMR_GPL_x4DIS |
973 MxMR_RLFx_2X |
974 MxMR_WLFx_2X |
975 MxMR_OP_NORM);
976 /* can configure */
977 count = can_config ();
978 printf ("CAN: %d @ %x\n", count, CFG_CAN_BASE);
979 if (hwinf.can != count) printf("!!! difference to HWIB\n");
980 } else {
981 printf ("CAN: No\n");
982 }
983 return 0;
984 }
985
986 int board_early_init_r(void)
987 {
988 analyse_hwib ();
989 init_can ();
990 return 0;
991 }
992 #endif
993
994 int do_hwib_dump (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
995 {
996 dump_hwib ();
997 return 0;
998 }
999
1000 U_BOOT_CMD(
1001 hwib, 1, 1, do_hwib_dump,
1002 "hwib - dump HWIB'\n",
1003 "\n"
1004 );
1005
1006 #ifdef CFG_UPDATE_FLASH_SIZE
1007 static int get_flash_timing (void)
1008 {
1009 /* get it from the option -tf in CIB */
1010 /* default is 0x00000c84 */
1011 int ret = 0x00000c84;
1012 int pos = 0;
1013 int nr = 0;
1014 char *p = (char *) CIB_INFO_START_ADDR;
1015
1016 while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
1017 if (*p < ' ' || *p > '~') { /* ASCII strings! */
1018 return ret;
1019 }
1020 if (*p == '-') {
1021 if ((p[1] == 't') && (p[2] == 'f')) {
1022 p += 6;
1023 ret = 0;
1024 while (nr < 8) {
1025 if ((*p >= '0') && (*p <= '9')) {
1026 ret *= 0x10;
1027 ret += *p - '0';
1028 p += 1;
1029 nr ++;
1030 } else if ((*p >= 'A') && (*p <= 'F')) {
1031 ret *= 10;
1032 ret += *p - '7';
1033 p += 1;
1034 nr ++;
1035 } else {
1036 if (nr < 8) return 0x00000c84;
1037 return ret;
1038 }
1039 }
1040 }
1041 }
1042 p++;
1043 pos++;
1044 }
1045 return ret;
1046 }
1047
1048 /* Update the Flash_Size and the Flash Timing */
1049 int update_flash_size (int flash_size)
1050 {
1051 volatile immap_t * immr = (immap_t *)CFG_IMMR;
1052 volatile memctl8260_t *memctl = &immr->im_memctl;
1053 unsigned long reg;
1054 unsigned long tim;
1055
1056 /* I must use reg, otherwise the board hang */
1057 reg = memctl->memc_or0;
1058 reg &= ~ORxU_AM_MSK;
1059 reg |= MEG_TO_AM(flash_size >> 20);
1060 tim = get_flash_timing ();
1061 reg &= ~0xfff;
1062 reg |= (tim & 0xfff);
1063 memctl->memc_or0 = reg;
1064 return 0;
1065 }
1066 #endif
1067
1068 #if defined(CONFIG_CMD_NAND)
1069
1070 #include <nand.h>
1071 #include <linux/mtd/mtd.h>
1072
1073 static u8 hwctl = 0;
1074
1075 static void upmnand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
1076 {
1077 switch (cmd) {
1078 case NAND_CTL_SETCLE:
1079 hwctl |= 0x1;
1080 break;
1081 case NAND_CTL_CLRCLE:
1082 hwctl &= ~0x1;
1083 break;
1084
1085 case NAND_CTL_SETALE:
1086 hwctl |= 0x2;
1087 break;
1088
1089 case NAND_CTL_CLRALE:
1090 hwctl &= ~0x2;
1091 break;
1092 }
1093 }
1094
1095 static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte)
1096 {
1097 struct nand_chip *this = mtdinfo->priv;
1098 ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
1099
1100 if (hwctl & 0x1) {
1101 WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS);
1102 } else if (hwctl & 0x2) {
1103 WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS);
1104 } else {
1105 WRITE_NAND(byte, base);
1106 }
1107 }
1108
1109 static u_char upmnand_read_byte(struct mtd_info *mtdinfo)
1110 {
1111 struct nand_chip *this = mtdinfo->priv;
1112 ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
1113
1114 return READ_NAND(base);
1115 }
1116
1117 static int tqm8272_dev_ready(struct mtd_info *mtdinfo)
1118 {
1119 /* constant delay (see also tR in the datasheet) */
1120 udelay(12); \
1121 return 1;
1122 }
1123
1124 #ifndef CONFIG_NAND_SPL
1125 static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
1126 {
1127 struct nand_chip *this = mtdinfo->priv;
1128 unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
1129 int i;
1130
1131 for (i = 0; i< len; i++)
1132 buf[i] = *base;
1133 }
1134
1135 static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
1136 {
1137 struct nand_chip *this = mtdinfo->priv;
1138 unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
1139 int i;
1140
1141 for (i = 0; i< len; i++)
1142 *base = buf[i];
1143 }
1144
1145 static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
1146 {
1147 struct nand_chip *this = mtdinfo->priv;
1148 unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
1149 int i;
1150
1151 for (i = 0; i < len; i++)
1152 if (buf[i] != *base)
1153 return -1;
1154 return 0;
1155 }
1156 #endif /* #ifndef CONFIG_NAND_SPL */
1157
1158 void board_nand_select_device(struct nand_chip *nand, int chip)
1159 {
1160 chipsel = chip;
1161 }
1162
1163 int board_nand_init(struct nand_chip *nand)
1164 {
1165 static int UpmInit = 0;
1166 volatile immap_t * immr = (immap_t *)CFG_IMMR;
1167 volatile memctl8260_t *memctl = &immr->im_memctl;
1168
1169 if (hwinf.nand == 0) return -1;
1170
1171 /* Setup the UPM */
1172 if (UpmInit == 0) {
1173 switch (hwinf.busclk_real) {
1174 case 100000000:
1175 upmconfig (UPMB, (uint *) upmTable100,
1176 sizeof (upmTable100) / sizeof (uint));
1177 break;
1178 case 133333333:
1179 upmconfig (UPMB, (uint *) upmTable133,
1180 sizeof (upmTable133) / sizeof (uint));
1181 break;
1182 default:
1183 upmconfig (UPMB, (uint *) upmTable67,
1184 sizeof (upmTable67) / sizeof (uint));
1185 break;
1186 }
1187 UpmInit = 1;
1188 }
1189
1190 /* Setup the memctrl */
1191 memctl->memc_or3 = CFG_NAND_OR;
1192 memctl->memc_br3 = CFG_NAND_BR;
1193 memctl->memc_mbmr = (MxMR_OP_NORM);
1194
1195 nand->eccmode = NAND_ECC_SOFT;
1196
1197 nand->hwcontrol = upmnand_hwcontrol;
1198 nand->read_byte = upmnand_read_byte;
1199 nand->write_byte = upmnand_write_byte;
1200 nand->dev_ready = tqm8272_dev_ready;
1201
1202 #ifndef CONFIG_NAND_SPL
1203 nand->write_buf = tqm8272_write_buf;
1204 nand->read_buf = tqm8272_read_buf;
1205 nand->verify_buf = tqm8272_verify_buf;
1206 #endif
1207
1208 /*
1209 * Select required NAND chip
1210 */
1211 board_nand_select_device(nand, 0);
1212 return 0;
1213 }
1214
1215 #endif
1216
1217 #ifdef CONFIG_PCI
1218 struct pci_controller hose;
1219
1220 int board_early_init_f (void)
1221 {
1222 volatile immap_t *immap = (immap_t *) CFG_IMMR;
1223
1224 immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
1225 return 0;
1226 }
1227
1228 extern void pci_mpc8250_init(struct pci_controller *);
1229
1230 void pci_init_board(void)
1231 {
1232 pci_mpc8250_init(&hose);
1233 }
1234 #endif
Fork of the u-boot for for Samsung based MINI2440 board