include/usbdcore_s3c2410.h

   1 /* linux/include/asm/arch-s3c2410/regs-udc.h
   2  *
   3  * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
   4  *
   5  * This include file is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  *  Changelog:
  11  *    01-08-2004        Initial creation
  12  *    12-09-2004        Cleanup for submission
  13  *    24-10-2004        Fixed S3C2410_UDC_MAXP_REG definition
  14  *    10-03-2005        Changed S3C2410_VA to S3C24XX_VA
  15  *    10-01-2007        Modify for u-boot
  16  */
  17
  18 #ifndef __ASM_ARCH_REGS_UDC_H
  19 #define __ASM_ARCH_REGS_UDC_H
  20
  21 #define S3C2410_UDC_REG_BASE_PHYS       0x52000000
  22 #define S3C2410_UDC_NUM_ENDPOINTS       5
  23
  24 #define S3C2410_USBDREG(x) (x + S3C2410_UDC_REG_BASE_PHYS)
  25
  26 #define S3C2410_UDC_FUNC_ADDR_REG       S3C2410_USBDREG(0x0140)
  27 #define S3C2410_UDC_PWR_REG             S3C2410_USBDREG(0x0144)
  28 #define S3C2410_UDC_EP_INT_REG          S3C2410_USBDREG(0x0148)
  29
  30 #define S3C2410_UDC_USB_INT_REG         S3C2410_USBDREG(0x0158)
  31 #define S3C2410_UDC_EP_INT_EN_REG       S3C2410_USBDREG(0x015c)
  32
  33 #define S3C2410_UDC_USB_INT_EN_REG      S3C2410_USBDREG(0x016c)
  34
  35 #define S3C2410_UDC_FRAME_NUM1_REG      S3C2410_USBDREG(0x0170)
  36 #define S3C2410_UDC_FRAME_NUM2_REG      S3C2410_USBDREG(0x0174)
  37
  38 #define S3C2410_UDC_EP0_FIFO_REG        S3C2410_USBDREG(0x01c0)
  39 #define S3C2410_UDC_EP1_FIFO_REG        S3C2410_USBDREG(0x01c4)
  40 #define S3C2410_UDC_EP2_FIFO_REG        S3C2410_USBDREG(0x01c8)
  41 #define S3C2410_UDC_EP3_FIFO_REG        S3C2410_USBDREG(0x01cc)
  42 #define S3C2410_UDC_EP4_FIFO_REG        S3C2410_USBDREG(0x01d0)
  43
  44 #define S3C2410_UDC_EP1_DMA_CON         S3C2410_USBDREG(0x0200)
  45 #define S3C2410_UDC_EP1_DMA_UNIT        S3C2410_USBDREG(0x0204)
  46 #define S3C2410_UDC_EP1_DMA_FIFO        S3C2410_USBDREG(0x0208)
  47 #define S3C2410_UDC_EP1_DMA_TTC_L       S3C2410_USBDREG(0x020c)
  48 #define S3C2410_UDC_EP1_DMA_TTC_M       S3C2410_USBDREG(0x0210)
  49 #define S3C2410_UDC_EP1_DMA_TTC_H       S3C2410_USBDREG(0x0214)
  50
  51 #define S3C2410_UDC_EP2_DMA_CON         S3C2410_USBDREG(0x0218)
  52 #define S3C2410_UDC_EP2_DMA_UNIT        S3C2410_USBDREG(0x021c)
  53 #define S3C2410_UDC_EP2_DMA_FIFO        S3C2410_USBDREG(0x0220)
  54 #define S3C2410_UDC_EP2_DMA_TTC_L       S3C2410_USBDREG(0x0224)
  55 #define S3C2410_UDC_EP2_DMA_TTC_M       S3C2410_USBDREG(0x0228)
  56 #define S3C2410_UDC_EP2_DMA_TTC_H       S3C2410_USBDREG(0x022c)
  57
  58 #define S3C2410_UDC_EP3_DMA_CON         S3C2410_USBDREG(0x0240)
  59 #define S3C2410_UDC_EP3_DMA_UNIT        S3C2410_USBDREG(0x0244)
  60 #define S3C2410_UDC_EP3_DMA_FIFO        S3C2410_USBDREG(0x0248)
  61 #define S3C2410_UDC_EP3_DMA_TTC_L       S3C2410_USBDREG(0x024c)
  62 #define S3C2410_UDC_EP3_DMA_TTC_M       S3C2410_USBDREG(0x0250)
  63 #define S3C2410_UDC_EP3_DMA_TTC_H       S3C2410_USBDREG(0x0254)
  64
  65 #define S3C2410_UDC_EP4_DMA_CON         S3C2410_USBDREG(0x0258)
  66 #define S3C2410_UDC_EP4_DMA_UNIT        S3C2410_USBDREG(0x025c)
  67 #define S3C2410_UDC_EP4_DMA_FIFO        S3C2410_USBDREG(0x0260)
  68 #define S3C2410_UDC_EP4_DMA_TTC_L       S3C2410_USBDREG(0x0264)
  69 #define S3C2410_UDC_EP4_DMA_TTC_M       S3C2410_USBDREG(0x0268)
  70 #define S3C2410_UDC_EP4_DMA_TTC_H       S3C2410_USBDREG(0x026c)
  71
  72 #define S3C2410_UDC_INDEX_REG           S3C2410_USBDREG(0x0178)
  73
  74 /* indexed registers */
  75
  76 #define S3C2410_UDC_MAXP_REG            S3C2410_USBDREG(0x0180)
  77
  78 #define S3C2410_UDC_EP0_CSR_REG         S3C2410_USBDREG(0x0184)
  79
  80 #define S3C2410_UDC_IN_CSR1_REG         S3C2410_USBDREG(0x0184)
  81 #define S3C2410_UDC_IN_CSR2_REG         S3C2410_USBDREG(0x0188)
  82
  83 #define S3C2410_UDC_OUT_CSR1_REG        S3C2410_USBDREG(0x0190)
  84 #define S3C2410_UDC_OUT_CSR2_REG        S3C2410_USBDREG(0x0194)
  85 #define S3C2410_UDC_OUT_FIFO_CNT1_REG   S3C2410_USBDREG(0x0198)
  86 #define S3C2410_UDC_OUT_FIFO_CNT2_REG   S3C2410_USBDREG(0x019c)
  87
  88
  89
  90 #define S3C2410_UDC_PWR_ISOUP           (1<<7) // R/W
  91 #define S3C2410_UDC_PWR_RESET           (1<<3) // R
  92 #define S3C2410_UDC_PWR_RESUME          (1<<2) // R/W
  93 #define S3C2410_UDC_PWR_SUSPEND         (1<<1) // R
  94 #define S3C2410_UDC_PWR_ENSUSPEND       (1<<0) // R/W
  95
  96 #define S3C2410_UDC_PWR_DEFAULT         0x00
  97
  98 #define S3C2410_UDC_INT_EP4             (1<<4) // R/W (clear only)
  99 #define S3C2410_UDC_INT_EP3             (1<<3) // R/W (clear only)
 100 #define S3C2410_UDC_INT_EP2             (1<<2) // R/W (clear only)
 101 #define S3C2410_UDC_INT_EP1             (1<<1) // R/W (clear only)
 102 #define S3C2410_UDC_INT_EP0             (1<<0) // R/W (clear only)
 103
 104 #define S3C2410_UDC_USBINT_RESET        (1<<2) // R/W (clear only)
 105 #define S3C2410_UDC_USBINT_RESUME       (1<<1) // R/W (clear only)
 106 #define S3C2410_UDC_USBINT_SUSPEND      (1<<0) // R/W (clear only)
 107
 108 #define S3C2410_UDC_INTE_EP4            (1<<4) // R/W
 109 #define S3C2410_UDC_INTE_EP3            (1<<3) // R/W
 110 #define S3C2410_UDC_INTE_EP2            (1<<2) // R/W
 111 #define S3C2410_UDC_INTE_EP1            (1<<1) // R/W
 112 #define S3C2410_UDC_INTE_EP0            (1<<0) // R/W
 113
 114 #define S3C2410_UDC_USBINTE_RESET       (1<<2) // R/W
 115 #define S3C2410_UDC_USBINTE_SUSPEND     (1<<0) // R/W
 116
 117
 118 #define S3C2410_UDC_INDEX_EP0           (0x00)
 119 #define S3C2410_UDC_INDEX_EP1           (0x01) // ??
 120 #define S3C2410_UDC_INDEX_EP2           (0x02) // ??
 121 #define S3C2410_UDC_INDEX_EP3           (0x03) // ??
 122 #define S3C2410_UDC_INDEX_EP4           (0x04) // ??
 123
 124 #define S3C2410_UDC_ICSR1_CLRDT         (1<<6) // R/W
 125 #define S3C2410_UDC_ICSR1_SENTSTL       (1<<5) // R/W (clear only)
 126 #define S3C2410_UDC_ICSR1_SENDSTL       (1<<4) // R/W
 127 #define S3C2410_UDC_ICSR1_FFLUSH        (1<<3) // W   (set only)
 128 #define S3C2410_UDC_ICSR1_UNDRUN        (1<<2) // R/W (clear only)
 129 #define S3C2410_UDC_ICSR1_PKTRDY        (1<<0) // R/W (set only)
 130
 131 #define S3C2410_UDC_ICSR2_AUTOSET       (1<<7) // R/W
 132 #define S3C2410_UDC_ICSR2_ISO           (1<<6) // R/W
 133 #define S3C2410_UDC_ICSR2_MODEIN        (1<<5) // R/W
 134 #define S3C2410_UDC_ICSR2_DMAIEN        (1<<4) // R/W
 135
 136 #define S3C2410_UDC_OCSR1_CLRDT         (1<<7) // R/W
 137 #define S3C2410_UDC_OCSR1_SENTSTL       (1<<6) // R/W (clear only)
 138 #define S3C2410_UDC_OCSR1_SENDSTL       (1<<5) // R/W
 139 #define S3C2410_UDC_OCSR1_FFLUSH        (1<<4) // R/W
 140 #define S3C2410_UDC_OCSR1_DERROR        (1<<3) // R
 141 #define S3C2410_UDC_OCSR1_OVRRUN        (1<<2) // R/W (clear only)
 142 #define S3C2410_UDC_OCSR1_PKTRDY        (1<<0) // R/W (clear only)
 143
 144 #define S3C2410_UDC_OCSR2_AUTOCLR       (1<<7) // R/W
 145 #define S3C2410_UDC_OCSR2_ISO           (1<<6) // R/W
 146 #define S3C2410_UDC_OCSR2_DMAIEN        (1<<5) // R/W
 147
 148 #define S3C2410_UDC_SETIX(X)    writel(X, S3C2410_UDC_INDEX_REG)
 149
 150 #define S3C2410_UDC_EP0_CSR_OPKRDY      (1<<0)
 151 #define S3C2410_UDC_EP0_CSR_IPKRDY      (1<<1)
 152 #define S3C2410_UDC_EP0_CSR_SENTSTL     (1<<2)
 153 #define S3C2410_UDC_EP0_CSR_DE          (1<<3)
 154 #define S3C2410_UDC_EP0_CSR_SE          (1<<4)
 155 #define S3C2410_UDC_EP0_CSR_SENDSTL     (1<<5)
 156 #define S3C2410_UDC_EP0_CSR_SOPKTRDY    (1<<6)
 157 #define S3C2410_UDC_EP0_CSR_SSE (1<<7)
 158
 159 #define S3C2410_UDC_MAXP_8              (1<<0)
 160 #define S3C2410_UDC_MAXP_16             (1<<1)
 161 #define S3C2410_UDC_MAXP_32             (1<<2)
 162 #define S3C2410_UDC_MAXP_64             (1<<3)
 163
 164 /****************** MACROS ******************/
 165 #define BIT_MASK        0xFF
 166
 167 #if 1
 168 #define maskl(v,m,a)      \
 169                 writel((readl(a) & ~(m))|((v)&(m)), (a))
 170 #else
 171 #define maskl(v,m,a)    do {                                    \
 172         unsigned long foo = readl(a);                           \
 173         unsigned long bar = (foo & ~(m)) | ((v)&(m));           \
 174         serial_printf("0x%08x:0x%x->0x%x\n", (a), foo, bar);    \
 175         writel(bar, (a));                                       \
 176 } while(0)
 177 #endif
 178
 179 #define clear_ep0_sst() do {                    \
 180         S3C2410_UDC_SETIX(0);                   \
 181         writel(0x00, S3C2410_UDC_EP0_CSR_REG);  \
 182 } while(0)
 183
 184 #define clear_ep0_se() do {                             \
 185         S3C2410_UDC_SETIX(0);                           \
 186         maskl(S3C2410_UDC_EP0_CSR_SSE,                  \
 187                 BIT_MASK, S3C2410_UDC_EP0_CSR_REG);     \
 188 } while(0)
 189
 190 #define clear_ep0_opr() do {                            \
 191         S3C2410_UDC_SETIX(0);                           \
 192         maskl(S3C2410_UDC_EP0_CSR_SOPKTRDY,             \
 193                 BIT_MASK, S3C2410_UDC_EP0_CSR_REG);     \
 194 } while(0)
 195
 196 #define set_ep0_ipr() do {                              \
 197         S3C2410_UDC_SETIX(0);                           \
 198         maskl(S3C2410_UDC_EP0_CSR_IPKRDY,               \
 199                 BIT_MASK, S3C2410_UDC_EP0_CSR_REG);     \
 200 } while(0)
 201
 202 #define set_ep0_de() do {                               \
 203         S3C2410_UDC_SETIX(0);                           \
 204         maskl(S3C2410_UDC_EP0_CSR_DE,                   \
 205                 BIT_MASK, S3C2410_UDC_EP0_CSR_REG);     \
 206 } while(0)
 207
 208 #define set_ep0_ss() do {                               \
 209         S3C2410_UDC_SETIX(0);                           \
 210         maskl(S3C2410_UDC_EP0_CSR_SENDSTL,              \
 211                 BIT_MASK, S3C2410_UDC_EP0_CSR_REG);     \
 212 } while(0)
 213
 214 #define set_ep0_de_out() do {                           \
 215         S3C2410_UDC_SETIX(0);                           \
 216         maskl((S3C2410_UDC_EP0_CSR_SOPKTRDY             \
 217                 | S3C2410_UDC_EP0_CSR_DE),              \
 218                 BIT_MASK, S3C2410_UDC_EP0_CSR_REG);     \
 219 } while(0)
 220
 221 #define set_ep0_sse_out() do {                          \
 222         S3C2410_UDC_SETIX(0);                           \
 223         maskl((S3C2410_UDC_EP0_CSR_SOPKTRDY             \
 224                 | S3C2410_UDC_EP0_CSR_SSE),             \
 225                 BIT_MASK, S3C2410_UDC_EP0_CSR_REG);     \
 226 } while(0)
 227
 228 #define set_ep0_de_in() do {                            \
 229         S3C2410_UDC_SETIX(0);                           \
 230         maskl((S3C2410_UDC_EP0_CSR_IPKRDY               \
 231                 | S3C2410_UDC_EP0_CSR_DE),              \
 232                 BIT_MASK, S3C2410_UDC_EP0_CSR_REG);     \
 233 } while(0)
 234
 235
 236 #if 0
 237
 238 #define clear_stall_ep1_out(base) do {                  \
 239         S3C2410_UDC_SETIX(base,EP1);                    \
 240         orl(0,base+S3C2410_UDC_OUT_CSR1_REG);           \
 241 } while(0)
 242
 243
 244 #define clear_stall_ep2_out(base) do {                  \
 245         S3C2410_UDC_SETIX(base,EP2);                    \
 246         orl(0, base+S3C2410_UDC_OUT_CSR1_REG);          \
 247 } while(0)
 248
 249
 250 #define clear_stall_ep3_out(base) do {                  \
 251         S3C2410_UDC_SETIX(base,EP3);                    \
 252         orl(0,base+S3C2410_UDC_OUT_CSR1_REG);           \
 253 } while(0)
 254
 255
 256 #define clear_stall_ep4_out(base) do {                  \
 257         S3C2410_UDC_SETIX(base,EP4);                    \
 258         orl(0, base+S3C2410_UDC_OUT_CSR1_REG);          \
 259 } while(0)
 260
 261 #endif
 262
 263 /* S3C2410 Endpoint parameters */
 264 #define EP0_MAX_PACKET_SIZE     16
 265 #define UDC_OUT_ENDPOINT        2
 266 #define UDC_OUT_PACKET_SIZE     64
 267 #define UDC_IN_ENDPOINT         1
 268 #define UDC_IN_PACKET_SIZE      64
 269 #define UDC_INT_ENDPOINT        5
 270 #define UDC_INT_PACKET_SIZE     16
 271 #define UDC_BULK_PACKET_SIZE    16
 272
 273 #endif