include/s3c2443.h

   1 /*
   2  * (C) Copyright 2007 OpenMoko, Inc.
   3  * Author: Harald Welte <laforge@openmoko.org>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __S3C2443_H
  25 #define __S3C2443_H
  26
  27 /* S3C2443 device base addresses */
  28 #define S3C24X0_MEMCTL_BASE             0x48000000
  29 #define S3C24X0_USB_HOST_BASE           0x49000000
  30 #define S3C24X0_INTERRUPT_BASE          0x4A000000
  31 #define S3C24X0_DMA_BASE                0x4B000000
  32 #define S3C24X0_CLOCK_POWER_BASE        0x4C000000
  33 #define S3C24X0_LCD_BASE                0x4D000000
  34 #define S3C2440_NAND_BASE               0x4E000000
  35 #define S3C24X0_UART_BASE               0x50000000
  36 #define S3C24X0_TIMER_BASE              0x51000000
  37 #define S3C24X0_USB_DEVICE_BASE         0x49800000
  38 //#define USB_DEVICE_PHYS_ADR           0x49800000
  39 #define S3C24X3_HSMMC_BASE              0x4A800000
  40 #define S3C24X3_HSSPI_BASE              0x52000000
  41 #define S3C24X0_WATCHDOG_BASE           0x53000000
  42 #define S3C24X0_I2C_BASE                0x54000000
  43 #define S3C24X0_I2S_BASE                0x55000000
  44 #define S3C24X0_GPIO_BASE               0x56000000
  45 #define S3C24X0_RTC_BASE                0x57000000
  46 #define S3C2440_ADC_BASE                0x58000000
  47 #define S3C24X0_SPI_BASE                0x59000000
  48 #define S3C2440_SDI_BASE                0x5A000000
  49 #define S3C2443_AC97_BASE               0x5A000000
  50
  51 #include <s3c24x0.h>
  52
  53 /* CLOCK & POWER MANAGEMENT (see S3C2443 manual chapter 2) */
  54 typedef struct {
  55         S3C24X0_REG32   LOCKCON0;
  56         S3C24X0_REG32   LOCKCON1;
  57         S3C24X0_REG32   OSCSET;
  58         S3C24X0_REG32   res1;
  59         S3C24X0_REG32   MPLLCON;
  60         S3C24X0_REG32   res2;
  61         S3C24X0_REG32   EPLLCON;
  62         S3C24X0_REG32   res3;
  63         S3C24X0_REG32   CLKSRC;
  64         S3C24X0_REG32   CLKDIV0;
  65         S3C24X0_REG32   CLKDIV1;
  66         S3C24X0_REG32   res4;
  67         S3C24X0_REG32   HCLKCON;
  68         S3C24X0_REG32   PCLKCON;
  69         S3C24X0_REG32   SCLKCON;
  70         S3C24X0_REG32   res5;
  71         S3C24X0_REG32   PWRMODE;
  72         S3C24X0_REG32   SWRST;
  73         S3C24X0_REG32   res6[2];
  74         S3C24X0_REG32   BUSPRI0;
  75         S3C24X0_REG32   res7[3];
  76 } /*__attribute__((__packed__))*/ S3C2443_CLOCK_POWER;
  77
  78 /* NAND FLASH (see S3C2443 manual chapter 7) */
  79 typedef struct {
  80         S3C24X0_REG32   NFCONF;
  81         S3C24X0_REG32   NFCONT;
  82         S3C24X0_REG32   NFCMD;
  83         S3C24X0_REG32   NFADDR;
  84         S3C24X0_REG32   NFDATA;
  85         S3C24X0_REG32   NFMECCD0;
  86         S3C24X0_REG32   NFMECCD1;
  87         S3C24X0_REG32   NFSECCD;
  88         S3C24X0_REG32   NFSBLK;
  89         S3C24X0_REG32   NFEBLK;
  90         S3C24X0_REG32   NFSTAT;
  91         S3C24X0_REG32   NFECCERR0;
  92         S3C24X0_REG32   NFECCERR1;
  93         S3C24X0_REG32   NFMECC0;
  94         S3C24X0_REG32   NFMECC1;
  95         S3C24X0_REG32   NFSECC;
  96         S3C24X0_REG32   NFMLCBITPT;
  97 } /*__attribute__((__packed__))*/ S3C2443_NAND;
  98
  99 /* STATIC MEMORY (see S3C2443 manual chapter 5) */
 100 struct s3c2443_sm_bank {
 101         S3C24X0_REG32   SMBIDCYR;
 102         S3C24X0_REG32   SMBWSTRDR;
 103         S3C24X0_REG32   SMBWSTWRR;
 104         S3C24X0_REG32   SMBWSTOENR;
 105         S3C24X0_REG32   SMBWSTWENR;
 106         S3C24X0_REG32   SMBCR;
 107         S3C24X0_REG32   SMBSR;
 108         S3C24X0_REG32   SMBWSTBRDR;
 109 };
 110
 111 typedef struct {
 112         struct s3c2443_sm_bank bank[5]; /* 0x4f000000..0x4f0000bf */
 113         S3C24X0_REG32   res[0x40];      /* 0x4f0000c0..0x4f0000ff */
 114         S3C24X0_REG32   SMBONETYPER;
 115         S3C24X0_REG32   SMCSR;
 116         S3C24X0_REG32   SMCCR;
 117 } /*__attribute__((__packed__))*/ S3C2443_SMEM;
 118
 119
 120 /* MOBILE DRAM (see S3C2443 manual chapter 6) */
 121 typedef struct {
 122         S3C24X0_REG32   BANKCFG;
 123         S3C24X0_REG32   BANKCON1;
 124         S3C24X0_REG32   BANKCON2;
 125         S3C24X0_REG32   BANKCON3;
 126         S3C24X0_REG32   REFRESH;
 127         S3C24X0_REG32   TIMEOUT;
 128 } /*__attribute__((__packed__))*/ S3C2443_MDRAM
 129
 130 #endif /* __S3C2443_H */