include/s3c2440.h

   1 /*
   2  * (C) Copyright 2003
   3  * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /************************************************
  25  * NAME     : s3c2440.h
  26  * Version  : 2007.
  27  *
  28  * Based on S3C2410X User's manual Rev 1.1
  29  ************************************************/
  30
  31 #ifndef __S3C2440_H__
  32 #define __S3C2440_H__
  33
  34 #define S3C24X0_UART_CHANNELS   3
  35 #define S3C24X0_SPI_CHANNELS    2
  36
  37 /* S3C2440 only supports 512 Byte HW ECC */
  38 #define S3C2440_ECCSIZE         512
  39 #define S3C2440_ECCBYTES        3
  40
  41 /* S3C2440 device base addresses */
  42 #define S3C24X0_MEMCTL_BASE             0x48000000
  43 #define S3C24X0_USB_HOST_BASE           0x49000000
  44 #define S3C24X0_INTERRUPT_BASE          0x4A000000
  45 #define S3C24X0_DMA_BASE                0x4B000000
  46 #define S3C24X0_CLOCK_POWER_BASE        0x4C000000
  47 #define S3C24X0_LCD_BASE                0x4D000000
  48 #define S3C2440_NAND_BASE               0x4E000000
  49 #define S3C24X0_UART_BASE               0x50000000
  50 #define S3C24X0_TIMER_BASE              0x51000000
  51 #define S3C24X0_USB_DEVICE_BASE         0x52000140
  52 #define USB_DEVICE_PHYS_ADR             0x52000000
  53 #define S3C24X0_WATCHDOG_BASE           0x53000000
  54 #define S3C24X0_I2C_BASE                0x54000000
  55 #define S3C24X0_I2S_BASE                0x55000000
  56 #define S3C24X0_GPIO_BASE               0x56000000
  57 #define S3C24X0_RTC_BASE                0x57000000
  58 #define S3C2440_ADC_BASE                0x58000000
  59 #define S3C24X0_SPI_BASE                0x59000000
  60 #define S3C2440_SDI_BASE                0x5A000000
  61
  62 #define oNFCONF                 0x00
  63 #define oNFCONT                 0x04
  64
  65 #ifndef __ASSEMBLER__
  66
  67 /* include common stuff */
  68 #include <s3c24x0.h>
  69
  70 typedef enum {
  71         S3C24X0_UART0,
  72         S3C24X0_UART1,
  73         S3C24X0_UART2
  74 } S3C24X0_UARTS_NR;
  75
  76 static inline S3C24X0_MEMCTL * S3C24X0_GetBase_MEMCTL(void)
  77 {
  78         return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE;
  79 }
  80 static inline S3C24X0_USB_HOST * S3C24X0_GetBase_USB_HOST(void)
  81 {
  82         return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE;
  83 }
  84 static inline S3C24X0_INTERRUPT * S3C24X0_GetBase_INTERRUPT(void)
  85 {
  86         return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE;
  87 }
  88 static inline S3C24X0_DMAS * S3C24X0_GetBase_DMAS(void)
  89 {
  90         return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE;
  91 }
  92 static inline S3C24X0_CLOCK_POWER * S3C24X0_GetBase_CLOCK_POWER(void)
  93 {
  94         return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE;
  95 }
  96 static inline S3C24X0_LCD * S3C24X0_GetBase_LCD(void)
  97 {
  98         return (S3C24X0_LCD * const)S3C24X0_LCD_BASE;
  99 }
 100 static inline S3C2440_NAND * S3C2440_GetBase_NAND(void)
 101 {
 102         return (S3C2440_NAND * const)S3C2440_NAND_BASE;
 103 }
 104 static inline S3C24X0_UART * S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
 105 {
 106         return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000));
 107 }
 108 static inline S3C24X0_TIMERS * S3C24X0_GetBase_TIMERS(void)
 109 {
 110         return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE;
 111 }
 112 static inline S3C24X0_USB_DEVICE * S3C24X0_GetBase_USB_DEVICE(void)
 113 {
 114         return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE;
 115 }
 116 static inline S3C24X0_WATCHDOG * S3C24X0_GetBase_WATCHDOG(void)
 117 {
 118         return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE;
 119 }
 120 static inline S3C24X0_I2C * S3C24X0_GetBase_I2C(void)
 121 {
 122         return (S3C24X0_I2C * const)S3C24X0_I2C_BASE;
 123 }
 124 static inline S3C24X0_I2S * S3C24X0_GetBase_I2S(void)
 125 {
 126         return (S3C24X0_I2S * const)S3C24X0_I2S_BASE;
 127 }
 128 static inline S3C24X0_GPIO * S3C24X0_GetBase_GPIO(void)
 129 {
 130         return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE;
 131 }
 132 static inline S3C24X0_RTC * S3C24X0_GetBase_RTC(void)
 133 {
 134         return (S3C24X0_RTC * const)S3C24X0_RTC_BASE;
 135 }
 136 /*
 137 static inline S3C2440_ADC * S3C2440_GetBase_ADC(void)
 138 {
 139         return (S3C2440_ADC * const)S3C2440_ADC_BASE;
 140 }
 141 static inline S3C24X0_SPI * S3C24X0_GetBase_SPI(void)
 142 {
 143         return (S3C24X0_SPI * const)S3C24X0_SPI_BASE;
 144 }
 145 */
 146 static inline S3C2410_SDI * S3C2410_GetBase_SDI(void)
 147 {
 148         return (S3C2410_SDI * const)S3C2440_SDI_BASE;
 149 }
 150
 151 #endif /* __ASSEMBLER__ */
 152
 153 /* ISR */
 154 #define pISR_RESET              (*(unsigned *)(_ISR_STARTADDRESS+0x0))
 155 #define pISR_UNDEF              (*(unsigned *)(_ISR_STARTADDRESS+0x4))
 156 #define pISR_SWI                (*(unsigned *)(_ISR_STARTADDRESS+0x8))
 157 #define pISR_PABORT             (*(unsigned *)(_ISR_STARTADDRESS+0xC))
 158 #define pISR_DABORT             (*(unsigned *)(_ISR_STARTADDRESS+0x10))
 159 #define pISR_RESERVED           (*(unsigned *)(_ISR_STARTADDRESS+0x14))
 160 #define pISR_IRQ                (*(unsigned *)(_ISR_STARTADDRESS+0x18))
 161 #define pISR_FIQ                (*(unsigned *)(_ISR_STARTADDRESS+0x1C))
 162
 163 #define pISR_EINT0              (*(unsigned *)(_ISR_STARTADDRESS+0x20))
 164 #define pISR_EINT1              (*(unsigned *)(_ISR_STARTADDRESS+0x24))
 165 #define pISR_EINT2              (*(unsigned *)(_ISR_STARTADDRESS+0x28))
 166 #define pISR_EINT3              (*(unsigned *)(_ISR_STARTADDRESS+0x2C))
 167 #define pISR_EINT4_7            (*(unsigned *)(_ISR_STARTADDRESS+0x30))
 168 #define pISR_EINT8_23           (*(unsigned *)(_ISR_STARTADDRESS+0x34))
 169 #define pISR_BAT_FLT            (*(unsigned *)(_ISR_STARTADDRESS+0x3C))
 170 #define pISR_TICK               (*(unsigned *)(_ISR_STARTADDRESS+0x40))
 171 #define pISR_WDT                (*(unsigned *)(_ISR_STARTADDRESS+0x44))
 172 #define pISR_TIMER0             (*(unsigned *)(_ISR_STARTADDRESS+0x48))
 173 #define pISR_TIMER1             (*(unsigned *)(_ISR_STARTADDRESS+0x4C))
 174 #define pISR_TIMER2             (*(unsigned *)(_ISR_STARTADDRESS+0x50))
 175 #define pISR_TIMER3             (*(unsigned *)(_ISR_STARTADDRESS+0x54))
 176 #define pISR_TIMER4             (*(unsigned *)(_ISR_STARTADDRESS+0x58))
 177 #define pISR_UART2              (*(unsigned *)(_ISR_STARTADDRESS+0x5C))
 178 #define pISR_NOTUSED            (*(unsigned *)(_ISR_STARTADDRESS+0x60))
 179 #define pISR_DMA0               (*(unsigned *)(_ISR_STARTADDRESS+0x64))
 180 #define pISR_DMA1               (*(unsigned *)(_ISR_STARTADDRESS+0x68))
 181 #define pISR_DMA2               (*(unsigned *)(_ISR_STARTADDRESS+0x6C))
 182 #define pISR_DMA3               (*(unsigned *)(_ISR_STARTADDRESS+0x70))
 183 #define pISR_SDI                (*(unsigned *)(_ISR_STARTADDRESS+0x74))
 184 #define pISR_SPI0               (*(unsigned *)(_ISR_STARTADDRESS+0x78))
 185 #define pISR_UART1              (*(unsigned *)(_ISR_STARTADDRESS+0x7C))
 186 #define pISR_USBD               (*(unsigned *)(_ISR_STARTADDRESS+0x84))
 187 #define pISR_USBH               (*(unsigned *)(_ISR_STARTADDRESS+0x88))
 188 #define pISR_IIC                (*(unsigned *)(_ISR_STARTADDRESS+0x8C))
 189 #define pISR_UART0              (*(unsigned *)(_ISR_STARTADDRESS+0x90))
 190 #define pISR_SPI1               (*(unsigned *)(_ISR_STARTADDRESS+0x94))
 191 #define pISR_RTC                (*(unsigned *)(_ISR_STARTADDRESS+0x98))
 192 #define pISR_ADC                (*(unsigned *)(_ISR_STARTADDRESS+0xA0))
 193
 194
 195 /* PENDING BIT */
 196 #define BIT_EINT0               (0x1)
 197 #define BIT_EINT1               (0x1<<1)
 198 #define BIT_EINT2               (0x1<<2)
 199 #define BIT_EINT3               (0x1<<3)
 200 #define BIT_EINT4_7             (0x1<<4)
 201 #define BIT_EINT8_23            (0x1<<5)
 202 #define BIT_BAT_FLT             (0x1<<7)
 203 #define BIT_TICK                (0x1<<8)
 204 #define BIT_WDT                 (0x1<<9)
 205 #define BIT_TIMER0              (0x1<<10)
 206 #define BIT_TIMER1              (0x1<<11)
 207 #define BIT_TIMER2              (0x1<<12)
 208 #define BIT_TIMER3              (0x1<<13)
 209 #define BIT_TIMER4              (0x1<<14)
 210 #define BIT_UART2               (0x1<<15)
 211 #define BIT_LCD                 (0x1<<16)
 212 #define BIT_DMA0                (0x1<<17)
 213 #define BIT_DMA1                (0x1<<18)
 214 #define BIT_DMA2                (0x1<<19)
 215 #define BIT_DMA3                (0x1<<20)
 216 #define BIT_SDI                 (0x1<<21)
 217 #define BIT_SPI0                (0x1<<22)
 218 #define BIT_UART1               (0x1<<23)
 219 #define BIT_USBD                (0x1<<25)
 220 #define BIT_USBH                (0x1<<26)
 221 #define BIT_IIC                 (0x1<<27)
 222 #define BIT_UART0               (0x1<<28)
 223 #define BIT_SPI1                (0x1<<29)
 224 #define BIT_RTC                 (0x1<<30)
 225 #define BIT_ADC                 (0x1<<31)
 226 #define BIT_ALLMSK              (0xFFFFFFFF)
 227
 228 #define ClearPending(bit) {\
 229                  rSRCPND = bit;\
 230                  rINTPND = bit;\
 231                  rINTPND;\
 232                  }
 233 /* Wait until rINTPND is changed for the case that the ISR is very short. */
 234
 235 #define __REG(x)        (*(volatile unsigned long *)(x))
 236 #define __REGl(x)       (*(volatile unsigned long *)(x))
 237 #define __REGw(x)       (*(volatile unsigned short *)(x))
 238 #define __REGb(x)       (*(volatile unsigned char *)(x))
 239 #define __REG2(x,y)     (*(volatile unsigned long *)((x) + (y)))
 240
 241 /*
 242  *  * Nand flash controller
 243  *   */
 244
 245 #define NFDATA8                 (*(volatile unsigned char *)0x4E000010)
 246 #define NFDATA16                (*(volatile unsigned short *)0x4E000010)
 247 #define NFDATA32                (*(volatile unsigned *)0x4E000010)
 248
 249 #define NFCONF                  __REG(0x4E000000)
 250 #define NFCONT                  __REG(0x4E000004)
 251 #define NFCMD                  __REG(0x4E000008)
 252 #define NFADDR                  __REGb(0x4E00000C)
 253 #define NFMECCD0                __REG(0x4E000014)
 254 #define NFMECCD1                __REG(0x4E000018)
 255 #define NFSECCD                 __REG(0x4E00001C)
 256 #define NFSTAT                  __REG(0x4E000020)
 257 #define NFESTAT0                __REG(0x4E000024)
 258 #define NFESTAT1                __REG(0x4E000028)
 259 #define NFMECC0                 __REG(0x4E00002C)
 260 #define NFMECC1                 __REG(0x4E000030)
 261 #define NFSECC                  __REG(0x4E000034)
 262 #define NFSBLK                  __REG(0x4E000038)
 263
 264
 265 #define S3C2410_MISCCR_USBDEV       (0<<3)
 266 #define S3C2410_MISCCR_USBHOST      (1<<3)
 267
 268 #define S3C2410_MISCCR_CLK0_MPLL    (0<<4)
 269 #define S3C2410_MISCCR_CLK0_UPLL    (1<<4)
 270 #define S3C2410_MISCCR_CLK0_FCLK    (2<<4)
 271 #define S3C2410_MISCCR_CLK0_HCLK    (3<<4)
 272 #define S3C2410_MISCCR_CLK0_PCLK    (4<<4)
 273 #define S3C2410_MISCCR_CLK0_DCLK0   (5<<4)
 274 #define S3C2410_MISCCR_CLK0_MASK    (7<<4)
 275
 276 #define S3C2410_MISCCR_CLK1_MPLL    (0<<8)
 277 #define S3C2410_MISCCR_CLK1_UPLL    (1<<8)
 278 #define S3C2410_MISCCR_CLK1_FCLK    (2<<8)
 279 #define S3C2410_MISCCR_CLK1_HCLK    (3<<8)
 280 #define S3C2410_MISCCR_CLK1_PCLK    (4<<8)
 281 #define S3C2410_MISCCR_CLK1_DCLK1   (5<<8)
 282 #define S3C2410_MISCCR_CLK1_MASK    (7<<8)
 283
 284 #define S3C2410_MISCCR_USBSUSPND0   (1<<12)
 285 #define S3C2410_MISCCR_USBSUSPND1   (1<<13)
 286
 287 #define S3C2410_MISCCR_nRSTCON      (1<<16)
 288
 289 #define S3C2410_MISCCR_nEN_SCLK0    (1<<17)
 290 #define S3C2410_MISCCR_nEN_SCLK1    (1<<18)
 291 #define S3C2410_MISCCR_nEN_SCLKE    (1<<19)
 292 #define S3C2410_MISCCR_SDSLEEP      (7<<17)
 293
 294 #define S3C2410_CLKSLOW_UCLK_OFF        (1<<7)
 295 #define S3C2410_CLKSLOW_MPLL_OFF        (1<<5)
 296 #define S3C2410_CLKSLOW_SLOW            (1<<4)
 297 #define S3C2410_CLKSLOW_SLOWVAL(x)      (x)
 298 #define S3C2410_CLKSLOW_GET_SLOWVAL(x)  ((x) & 7)
 299
 300 #endif /*__S3C2440_H__*/