include/s3c2400.h

   1 /*
   2  * (C) Copyright 2003
   3  * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /************************************************
  25  * NAME     : s3c2400.h
  26  * Version  : 31.3.2003
  27  *
  28  * Based on S3C2400X User's manual Rev 1.1
  29  ************************************************/
  30
  31 #ifndef __S3C2400_H__
  32 #define __S3C2400_H__
  33
  34 #define S3C24X0_UART_CHANNELS   2
  35 #define S3C24X0_SPI_CHANNELS    1
  36 #define PALETTE                 (0x14A00400)    /* SJS */
  37
  38 typedef enum {
  39         S3C24X0_UART0,
  40         S3C24X0_UART1,
  41 } S3C24X0_UARTS_NR;
  42
  43 /* S3C2400 device base addresses */
  44 #define S3C24X0_MEMCTL_BASE             0x14000000
  45 #define S3C24X0_USB_HOST_BASE           0x14200000
  46 #define S3C24X0_INTERRUPT_BASE          0x14400000
  47 #define S3C24X0_DMA_BASE                0x14600000
  48 #define S3C24X0_CLOCK_POWER_BASE        0x14800000
  49 #define S3C24X0_LCD_BASE                0x14A00000
  50 #define S3C24X0_UART_BASE               0x15000000
  51 #define S3C24X0_TIMER_BASE              0x15100000
  52 #define S3C24X0_USB_DEVICE_BASE         0x15200140
  53 #define S3C24X0_WATCHDOG_BASE           0x15300000
  54 #define S3C24X0_I2C_BASE                0x15400000
  55 #define S3C24X0_I2S_BASE                0x15508000
  56 #define S3C24X0_GPIO_BASE               0x15600000
  57 #define S3C24X0_RTC_BASE                0x15700000
  58 #define S3C24X0_ADC_BASE                0x15800000
  59 #define S3C24X0_SPI_BASE                0x15900000
  60 #define S3C2400_MMC_BASE                0x15A00000
  61
  62 /* include common stuff */
  63 #include <s3c24x0.h>
  64
  65
  66 static inline S3C24X0_MEMCTL * S3C24X0_GetBase_MEMCTL(void)
  67 {
  68         return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE;
  69 }
  70 static inline S3C24X0_USB_HOST * S3C24X0_GetBase_USB_HOST(void)
  71 {
  72         return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE;
  73 }
  74 static inline S3C24X0_INTERRUPT * S3C24X0_GetBase_INTERRUPT(void)
  75 {
  76         return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE;
  77 }
  78 static inline S3C24X0_DMAS * S3C24X0_GetBase_DMAS(void)
  79 {
  80         return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE;
  81 }
  82 static inline S3C24X0_CLOCK_POWER * S3C24X0_GetBase_CLOCK_POWER(void)
  83 {
  84         return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE;
  85 }
  86 static inline S3C24X0_LCD * S3C24X0_GetBase_LCD(void)
  87 {
  88         return (S3C24X0_LCD * const)S3C24X0_LCD_BASE;
  89 }
  90 static inline S3C24X0_UART * S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
  91 {
  92         return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000));
  93 }
  94 static inline S3C24X0_TIMERS * S3C24X0_GetBase_TIMERS(void)
  95 {
  96         return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE;
  97 }
  98 static inline S3C24X0_USB_DEVICE * S3C24X0_GetBase_USB_DEVICE(void)
  99 {
 100         return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE;
 101 }
 102 static inline S3C24X0_WATCHDOG * S3C24X0_GetBase_WATCHDOG(void)
 103 {
 104         return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE;
 105 }
 106 static inline S3C24X0_I2C * S3C24X0_GetBase_I2C(void)
 107 {
 108         return (S3C24X0_I2C * const)S3C24X0_I2C_BASE;
 109 }
 110 static inline S3C24X0_I2S * S3C24X0_GetBase_I2S(void)
 111 {
 112         return (S3C24X0_I2S * const)S3C24X0_I2S_BASE;
 113 }
 114 static inline S3C24X0_GPIO * S3C24X0_GetBase_GPIO(void)
 115 {
 116         return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE;
 117 }
 118 static inline S3C24X0_RTC * S3C24X0_GetBase_RTC(void)
 119 {
 120         return (S3C24X0_RTC * const)S3C24X0_RTC_BASE;
 121 }
 122 static inline S3C2400_ADC * S3C2400_GetBase_ADC(void)
 123 {
 124         return (S3C2400_ADC * const)S3C24X0_ADC_BASE;
 125 }
 126 static inline S3C24X0_SPI * S3C24X0_GetBase_SPI(void)
 127 {
 128         return (S3C24X0_SPI * const)S3C24X0_SPI_BASE;
 129 }
 130 static inline S3C2400_MMC * S3C2400_GetBase_MMC(void)
 131 {
 132         return (S3C2400_MMC * const)S3C2400_MMC_BASE;
 133 }
 134
 135 #if 0
 136 /* Memory control */
 137 #define rBWSCON         (*(volatile unsigned *)0x14000000)
 138 #define rBANKCON0       (*(volatile unsigned *)0x14000004)
 139 #define rBANKCON1       (*(volatile unsigned *)0x14000008)
 140 #define rBANKCON2       (*(volatile unsigned *)0x1400000C)
 141 #define rBANKCON3       (*(volatile unsigned *)0x14000010)
 142 #define rBANKCON4       (*(volatile unsigned *)0x14000014)
 143 #define rBANKCON5       (*(volatile unsigned *)0x14000018)
 144 #define rBANKCON6       (*(volatile unsigned *)0x1400001C)
 145 #define rBANKCON7       (*(volatile unsigned *)0x14000020)
 146 #define rREFRESH        (*(volatile unsigned *)0x14000024)
 147 #define rBANKSIZE       (*(volatile unsigned *)0x14000028)
 148 #define rMRSRB6         (*(volatile unsigned *)0x1400002C)
 149 #define rMRSRB7         (*(volatile unsigned *)0x14000030)
 150
 151
 152 /* INTERRUPT */
 153 #define rSRCPND         (*(volatile unsigned *)0x14400000)
 154 #define rINTMOD         (*(volatile unsigned *)0x14400004)
 155 #define rINTMSK         (*(volatile unsigned *)0x14400008)
 156 #define rPRIORITY       (*(volatile unsigned *)0x1440000C)
 157 #define rINTPND         (*(volatile unsigned *)0x14400010)
 158 #define rINTOFFSET      (*(volatile unsigned *)0x14400014)
 159
 160
 161 /* DMA */
 162 #define rDISRC0         (*(volatile unsigned *)0x14600000)
 163 #define rDIDST0         (*(volatile unsigned *)0x14600004)
 164 #define rDCON0          (*(volatile unsigned *)0x14600008)
 165 #define rDSTAT0         (*(volatile unsigned *)0x1460000C)
 166 #define rDCSRC0         (*(volatile unsigned *)0x14600010)
 167 #define rDCDST0         (*(volatile unsigned *)0x14600014)
 168 #define rDMASKTRIG0     (*(volatile unsigned *)0x14600018)
 169 #define rDISRC1         (*(volatile unsigned *)0x14600020)
 170 #define rDIDST1         (*(volatile unsigned *)0x14600024)
 171 #define rDCON1          (*(volatile unsigned *)0x14600028)
 172 #define rDSTAT1         (*(volatile unsigned *)0x1460002C)
 173 #define rDCSRC1         (*(volatile unsigned *)0x14600030)
 174 #define rDCDST1         (*(volatile unsigned *)0x14600034)
 175 #define rDMASKTRIG1     (*(volatile unsigned *)0x14600038)
 176 #define rDISRC2         (*(volatile unsigned *)0x14600040)
 177 #define rDIDST2         (*(volatile unsigned *)0x14600044)
 178 #define rDCON2          (*(volatile unsigned *)0x14600048)
 179 #define rDSTAT2         (*(volatile unsigned *)0x1460004C)
 180 #define rDCSRC2         (*(volatile unsigned *)0x14600050)
 181 #define rDCDST2         (*(volatile unsigned *)0x14600054)
 182 #define rDMASKTRIG2     (*(volatile unsigned *)0x14600058)
 183 #define rDISRC3         (*(volatile unsigned *)0x14600060)
 184 #define rDIDST3         (*(volatile unsigned *)0x14600064)
 185 #define rDCON3          (*(volatile unsigned *)0x14600068)
 186 #define rDSTAT3         (*(volatile unsigned *)0x1460006C)
 187 #define rDCSRC3         (*(volatile unsigned *)0x14600070)
 188 #define rDCDST3         (*(volatile unsigned *)0x14600074)
 189 #define rDMASKTRIG3     (*(volatile unsigned *)0x14600078)
 190
 191
 192 /* CLOCK & POWER MANAGEMENT */
 193 #define rLOCKTIME       (*(volatile unsigned *)0x14800000)
 194 #define rMPLLCON        (*(volatile unsigned *)0x14800004)
 195 #define rUPLLCON        (*(volatile unsigned *)0x14800008)
 196 #define rCLKCON         (*(volatile unsigned *)0x1480000C)
 197 #define rCLKSLOW        (*(volatile unsigned *)0x14800010)
 198 #define rCLKDIVN        (*(volatile unsigned *)0x14800014)
 199
 200
 201 /* LCD CONTROLLER */
 202 #define rLCDCON1        (*(volatile unsigned *)0x14A00000)
 203 #define rLCDCON2        (*(volatile unsigned *)0x14A00004)
 204 #define rLCDCON3        (*(volatile unsigned *)0x14A00008)
 205 #define rLCDCON4        (*(volatile unsigned *)0x14A0000C)
 206 #define rLCDCON5        (*(volatile unsigned *)0x14A00010)
 207 #define rLCDSADDR1      (*(volatile unsigned *)0x14A00014)
 208 #define rLCDSADDR2      (*(volatile unsigned *)0x14A00018)
 209 #define rLCDSADDR3      (*(volatile unsigned *)0x14A0001C)
 210 #define rREDLUT         (*(volatile unsigned *)0x14A00020)
 211 #define rGREENLUT       (*(volatile unsigned *)0x14A00024)
 212 #define rBLUELUT        (*(volatile unsigned *)0x14A00028)
 213 #define rDP1_2          (*(volatile unsigned *)0x14A0002C)
 214 #define rDP4_7          (*(volatile unsigned *)0x14A00030)
 215 #define rDP3_5          (*(volatile unsigned *)0x14A00034)
 216 #define rDP2_3          (*(volatile unsigned *)0x14A00038)
 217 #define rDP5_7          (*(volatile unsigned *)0x14A0003c)
 218 #define rDP3_4          (*(volatile unsigned *)0x14A00040)
 219 #define rDP4_5          (*(volatile unsigned *)0x14A00044)
 220 #define rDP6_7          (*(volatile unsigned *)0x14A00048)
 221 #define rDITHMODE       (*(volatile unsigned *)0x14A0004C)
 222 #define rTPAL           (*(volatile unsigned *)0x14A00050)
 223 #define PALETTE         (0x14A00400)    /* SJS */
 224
 225
 226 /* UART */
 227 #define rULCON0         (*(volatile unsigned char *)0x15000000)
 228 #define rUCON0          (*(volatile unsigned short *)0x15000004)
 229 #define rUFCON0         (*(volatile unsigned char *)0x15000008)
 230 #define rUMCON0         (*(volatile unsigned char *)0x1500000C)
 231 #define rUTRSTAT0       (*(volatile unsigned char *)0x15000010)
 232 #define rUERSTAT0       (*(volatile unsigned char *)0x15000014)
 233 #define rUFSTAT0        (*(volatile unsigned short *)0x15000018)
 234 #define rUMSTAT0        (*(volatile unsigned char *)0x1500001C)
 235 #define rUBRDIV0        (*(volatile unsigned short *)0x15000028)
 236
 237 #define rULCON1         (*(volatile unsigned char *)0x15004000)
 238 #define rUCON1          (*(volatile unsigned short *)0x15004004)
 239 #define rUFCON1         (*(volatile unsigned char *)0x15004008)
 240 #define rUMCON1         (*(volatile unsigned char *)0x1500400C)
 241 #define rUTRSTAT1       (*(volatile unsigned char *)0x15004010)
 242 #define rUERSTAT1       (*(volatile unsigned char *)0x15004014)
 243 #define rUFSTAT1        (*(volatile unsigned short *)0x15004018)
 244 #define rUMSTAT1        (*(volatile unsigned char *)0x1500401C)
 245 #define rUBRDIV1        (*(volatile unsigned short *)0x15004028)
 246
 247 #ifdef __BIG_ENDIAN
 248 #define rUTXH0          (*(volatile unsigned char *)0x15000023)
 249 #define rURXH0          (*(volatile unsigned char *)0x15000027)
 250 #define rUTXH1          (*(volatile unsigned char *)0x15004023)
 251 #define rURXH1          (*(volatile unsigned char *)0x15004027)
 252
 253 #define WrUTXH0(ch)     (*(volatile unsigned char *)0x15000023)=(unsigned char)(ch)
 254 #define RdURXH0()       (*(volatile unsigned char *)0x15000027)
 255 #define WrUTXH1(ch)     (*(volatile unsigned char *)0x15004023)=(unsigned char)(ch)
 256 #define RdURXH1()       (*(volatile unsigned char *)0x15004027)
 257
 258 #define UTXH0           (0x15000020+3)  /* byte_access address by DMA */
 259 #define URXH0           (0x15000024+3)
 260 #define UTXH1           (0x15004020+3)
 261 #define URXH1           (0x15004024+3)
 262
 263 #else /* Little Endian */
 264 #define rUTXH0          (*(volatile unsigned char *)0x15000020)
 265 #define rURXH0          (*(volatile unsigned char *)0x15000024)
 266 #define rUTXH1          (*(volatile unsigned char *)0x15004020)
 267 #define rURXH1          (*(volatile unsigned char *)0x15004024)
 268
 269 #define WrUTXH0(ch)     (*(volatile unsigned char *)0x15000020)=(unsigned char)(ch)
 270 #define RdURXH0()       (*(volatile unsigned char *)0x15000024)
 271 #define WrUTXH1(ch)     (*(volatile unsigned char *)0x15004020)=(unsigned char)(ch)
 272 #define RdURXH1()       (*(volatile unsigned char *)0x15004024)
 273
 274 #define UTXH0           (0x15000020)    /* byte_access address by DMA */
 275 #define URXH0           (0x15000024)
 276 #define UTXH1           (0x15004020)
 277 #define URXH1           (0x15004024)
 278 #endif
 279
 280
 281 /* PWM TIMER */
 282 #define rTCFG0          (*(volatile unsigned *)0x15100000)
 283 #define rTCFG1          (*(volatile unsigned *)0x15100004)
 284 #define rTCON           (*(volatile unsigned *)0x15100008)
 285 #define rTCNTB0         (*(volatile unsigned *)0x1510000C)
 286 #define rTCMPB0         (*(volatile unsigned *)0x15100010)
 287 #define rTCNTO0         (*(volatile unsigned *)0x15100014)
 288 #define rTCNTB1         (*(volatile unsigned *)0x15100018)
 289 #define rTCMPB1         (*(volatile unsigned *)0x1510001C)
 290 #define rTCNTO1         (*(volatile unsigned *)0x15100020)
 291 #define rTCNTB2         (*(volatile unsigned *)0x15100024)
 292 #define rTCMPB2         (*(volatile unsigned *)0x15100028)
 293 #define rTCNTO2         (*(volatile unsigned *)0x1510002C)
 294 #define rTCNTB3         (*(volatile unsigned *)0x15100030)
 295 #define rTCMPB3         (*(volatile unsigned *)0x15100034)
 296 #define rTCNTO3         (*(volatile unsigned *)0x15100038)
 297 #define rTCNTB4         (*(volatile unsigned *)0x1510003C)
 298 #define rTCNTO4         (*(volatile unsigned *)0x15100040)
 299
 300
 301 /* USB DEVICE */
 302 #define rFUNC_ADDR_REG  (*(volatile unsigned *)0x15200140)
 303 #define rPWR_REG        (*(volatile unsigned *)0x15200144)
 304 #define rINT_REG        (*(volatile unsigned *)0x15200148)
 305 #define rINT_MASK_REG   (*(volatile unsigned *)0x1520014C)
 306 #define rFRAME_NUM_REG  (*(volatile unsigned *)0x15200150)
 307 #define rRESUME_CON_REG (*(volatile unsigned *)0x15200154)
 308 #define rEP0_CSR        (*(volatile unsigned *)0x15200160)
 309 #define rEP0_MAXP       (*(volatile unsigned *)0x15200164)
 310 #define rEP0_OUT_CNT    (*(volatile unsigned *)0x15200168)
 311 #define rEP0_FIFO       (*(volatile unsigned *)0x1520016C)
 312 #define rEP1_IN_CSR     (*(volatile unsigned *)0x15200180)
 313 #define rEP1_IN_MAXP    (*(volatile unsigned *)0x15200184)
 314 #define rEP1_FIFO       (*(volatile unsigned *)0x15200188)
 315 #define rEP2_IN_CSR     (*(volatile unsigned *)0x15200190)
 316 #define rEP2_IN_MAXP    (*(volatile unsigned *)0x15200194)
 317 #define rEP2_FIFO       (*(volatile unsigned *)0x15200198)
 318 #define rEP3_OUT_CSR    (*(volatile unsigned *)0x152001A0)
 319 #define rEP3_OUT_MAXP   (*(volatile unsigned *)0x152001A4)
 320 #define rEP3_OUT_CNT    (*(volatile unsigned *)0x152001A8)
 321 #define rEP3_FIFO       (*(volatile unsigned *)0x152001AC)
 322 #define rEP4_OUT_CSR    (*(volatile unsigned *)0x152001B0)
 323 #define rEP4_OUT_MAXP   (*(volatile unsigned *)0x152001B4)
 324 #define rEP4_OUT_CNT    (*(volatile unsigned *)0x152001B8)
 325 #define rEP4_FIFO       (*(volatile unsigned *)0x152001BC)
 326 #define rDMA_CON        (*(volatile unsigned *)0x152001C0)
 327 #define rDMA_UNIT       (*(volatile unsigned *)0x152001C4)
 328 #define rDMA_FIFO       (*(volatile unsigned *)0x152001C8)
 329 #define rDMA_TX         (*(volatile unsigned *)0x152001CC)
 330 #define rTEST_MODE      (*(volatile unsigned *)0x152001F4)
 331 #define rIN_CON_REG     (*(volatile unsigned *)0x152001F8)
 332
 333
 334 /* WATCH DOG TIMER */
 335 #define rWTCON          (*(volatile unsigned *)0x15300000)
 336 #define rWTDAT          (*(volatile unsigned *)0x15300004)
 337 #define rWTCNT          (*(volatile unsigned *)0x15300008)
 338
 339
 340 /* IIC */
 341 #define rIICCON         (*(volatile unsigned *)0x15400000)
 342 #define rIICSTAT        (*(volatile unsigned *)0x15400004)
 343 #define rIICADD         (*(volatile unsigned *)0x15400008)
 344 #define rIICDS          (*(volatile unsigned *)0x1540000C)
 345
 346
 347 /* IIS */
 348 #define rIISCON         (*(volatile unsigned *)0x15508000)
 349 #define rIISMOD         (*(volatile unsigned *)0x15508004)
 350 #define rIISPSR         (*(volatile unsigned *)0x15508008)
 351 #define rIISFIFCON      (*(volatile unsigned *)0x1550800C)
 352
 353 #ifdef __BIG_ENDIAN
 354 #define IISFIF          ((volatile unsigned short *)0x15508012)
 355
 356 #else /* Little Endian */
 357 #define IISFIF          ((volatile unsigned short *)0x15508010)
 358 #endif
 359
 360
 361 /* I/O PORT */
 362 #define rPACON          (*(volatile unsigned *)0x15600000)
 363 #define rPADAT          (*(volatile unsigned *)0x15600004)
 364
 365 #define rPBCON          (*(volatile unsigned *)0x15600008)
 366 #define rPBDAT          (*(volatile unsigned *)0x1560000C)
 367 #define rPBUP           (*(volatile unsigned *)0x15600010)
 368
 369 #define rPCCON          (*(volatile unsigned *)0x15600014)
 370 #define rPCDAT          (*(volatile unsigned *)0x15600018)
 371 #define rPCUP           (*(volatile unsigned *)0x1560001C)
 372
 373 #define rPDCON          (*(volatile unsigned *)0x15600020)
 374 #define rPDDAT          (*(volatile unsigned *)0x15600024)
 375 #define rPDUP           (*(volatile unsigned *)0x15600028)
 376
 377 #define rPECON          (*(volatile unsigned *)0x1560002C)
 378 #define rPEDAT          (*(volatile unsigned *)0x15600030)
 379 #define rPEUP           (*(volatile unsigned *)0x15600034)
 380
 381 #define rPFCON          (*(volatile unsigned *)0x15600038)
 382 #define rPFDAT          (*(volatile unsigned *)0x1560003C)
 383 #define rPFUP           (*(volatile unsigned *)0x15600040)
 384
 385 #define rPGCON          (*(volatile unsigned *)0x15600044)
 386 #define rPGDAT          (*(volatile unsigned *)0x15600048)
 387 #define rPGUP           (*(volatile unsigned *)0x1560004C)
 388
 389 #define rOPENCR         (*(volatile unsigned *)0x15600050)
 390 #define rMISCCR         (*(volatile unsigned *)0x15600054)
 391 #define rEXTINT         (*(volatile unsigned *)0x15600058)
 392
 393
 394 /* RTC */
 395 #ifdef __BIG_ENDIAN
 396 #define rRTCCON         (*(volatile unsigned char *)0x15700043)
 397 #define rRTCALM         (*(volatile unsigned char *)0x15700053)
 398 #define rALMSEC         (*(volatile unsigned char *)0x15700057)
 399 #define rALMMIN         (*(volatile unsigned char *)0x1570005B)
 400 #define rALMHOUR        (*(volatile unsigned char *)0x1570005F)
 401 #define rALMDAY         (*(volatile unsigned char *)0x15700063)
 402 #define rALMMON         (*(volatile unsigned char *)0x15700067)
 403 #define rALMYEAR        (*(volatile unsigned char *)0x1570006B)
 404 #define rRTCRST         (*(volatile unsigned char *)0x1570006F)
 405 #define rBCDSEC         (*(volatile unsigned char *)0x15700073)
 406 #define rBCDMIN         (*(volatile unsigned char *)0x15700077)
 407 #define rBCDHOUR        (*(volatile unsigned char *)0x1570007B)
 408 #define rBCDDAY         (*(volatile unsigned char *)0x1570007F)
 409 #define rBCDDATE        (*(volatile unsigned char *)0x15700083)
 410 #define rBCDMON         (*(volatile unsigned char *)0x15700087)
 411 #define rBCDYEAR        (*(volatile unsigned char *)0x1570008B)
 412 #define rTICINT         (*(volatile unsigned char *)0x15700047)
 413
 414 #else /* Little Endian */
 415 #define rRTCCON         (*(volatile unsigned char *)0x15700040)
 416 #define rRTCALM         (*(volatile unsigned char *)0x15700050)
 417 #define rALMSEC         (*(volatile unsigned char *)0x15700054)
 418 #define rALMMIN         (*(volatile unsigned char *)0x15700058)
 419 #define rALMHOUR        (*(volatile unsigned char *)0x1570005C)
 420 #define rALMDAY         (*(volatile unsigned char *)0x15700060)
 421 #define rALMMON         (*(volatile unsigned char *)0x15700064)
 422 #define rALMYEAR        (*(volatile unsigned char *)0x15700068)
 423 #define rRTCRST         (*(volatile unsigned char *)0x1570006C)
 424 #define rBCDSEC         (*(volatile unsigned char *)0x15700070)
 425 #define rBCDMIN         (*(volatile unsigned char *)0x15700074)
 426 #define rBCDHOUR        (*(volatile unsigned char *)0x15700078)
 427 #define rBCDDAY         (*(volatile unsigned char *)0x1570007C)
 428 #define rBCDDATE        (*(volatile unsigned char *)0x15700080)
 429 #define rBCDMON         (*(volatile unsigned char *)0x15700084)
 430 #define rBCDYEAR        (*(volatile unsigned char *)0x15700088)
 431 #define rTICINT         (*(volatile unsigned char *)0x15700044)
 432 #endif
 433
 434
 435 /* ADC */
 436 #define rADCCON         (*(volatile unsigned *)0x15800000)
 437 #define rADCDAT         (*(volatile unsigned *)0x15800004)
 438
 439
 440 /* SPI */
 441 #define rSPCON          (*(volatile unsigned *)0x15900000)
 442 #define rSPSTA          (*(volatile unsigned *)0x15900004)
 443 #define rSPPIN          (*(volatile unsigned *)0x15900008)
 444 #define rSPPRE          (*(volatile unsigned *)0x1590000C)
 445 #define rSPTDAT         (*(volatile unsigned *)0x15900010)
 446 #define rSPRDAT         (*(volatile unsigned *)0x15900014)
 447
 448
 449 /* MMC INTERFACE */
 450 #define rMMCON          (*(volatile unsigned *)0x15a00000)
 451 #define rMMCRR          (*(volatile unsigned *)0x15a00004)
 452 #define rMMFCON         (*(volatile unsigned *)0x15a00008)
 453 #define rMMSTA          (*(volatile unsigned *)0x15a0000C)
 454 #define rMMFSTA         (*(volatile unsigned *)0x15a00010)
 455 #define rMMPRE          (*(volatile unsigned *)0x15a00014)
 456 #define rMMLEN          (*(volatile unsigned *)0x15a00018)
 457 #define rMMCR7          (*(volatile unsigned *)0x15a0001C)
 458 #define rMMRSP0         (*(volatile unsigned *)0x15a00020)
 459 #define rMMRSP1         (*(volatile unsigned *)0x15a00024)
 460 #define rMMRSP2         (*(volatile unsigned *)0x15a00028)
 461 #define rMMRSP3         (*(volatile unsigned *)0x15a0002C)
 462 #define rMMCMD0         (*(volatile unsigned *)0x15a00030)
 463 #define rMMCMD1         (*(volatile unsigned *)0x15a00034)
 464 #define rMMCR16         (*(volatile unsigned *)0x15a00038)
 465 #define rMMDAT          (*(volatile unsigned *)0x15a0003C)
 466
 467
 468 /* ISR */
 469 #define pISR_RESET      (*(unsigned *)(_ISR_STARTADDRESS+0x0))
 470 #define pISR_UNDEF      (*(unsigned *)(_ISR_STARTADDRESS+0x4))
 471 #define pISR_SWI        (*(unsigned *)(_ISR_STARTADDRESS+0x8))
 472 #define pISR_PABORT     (*(unsigned *)(_ISR_STARTADDRESS+0xC))
 473 #define pISR_DABORT     (*(unsigned *)(_ISR_STARTADDRESS+0x10))
 474 #define pISR_RESERVED   (*(unsigned *)(_ISR_STARTADDRESS+0x14))
 475 #define pISR_IRQ        (*(unsigned *)(_ISR_STARTADDRESS+0x18))
 476 #define pISR_FIQ        (*(unsigned *)(_ISR_STARTADDRESS+0x1C))
 477
 478 #define pISR_EINT0      (*(unsigned *)(_ISR_STARTADDRESS+0x20))
 479 #define pISR_EINT1      (*(unsigned *)(_ISR_STARTADDRESS+0x24))
 480 #define pISR_EINT2      (*(unsigned *)(_ISR_STARTADDRESS+0x28))
 481 #define pISR_EINT3      (*(unsigned *)(_ISR_STARTADDRESS+0x2C))
 482 #define pISR_EINT4      (*(unsigned *)(_ISR_STARTADDRESS+0x30))
 483 #define pISR_EINT5      (*(unsigned *)(_ISR_STARTADDRESS+0x34))
 484 #define pISR_EINT6      (*(unsigned *)(_ISR_STARTADDRESS+0x38))
 485 #define pISR_EINT7      (*(unsigned *)(_ISR_STARTADDRESS+0x3C))
 486 #define pISR_TICK       (*(unsigned *)(_ISR_STARTADDRESS+0x40))
 487 #define pISR_WDT        (*(unsigned *)(_ISR_STARTADDRESS+0x44))
 488 #define pISR_TIMER0     (*(unsigned *)(_ISR_STARTADDRESS+0x48))
 489 #define pISR_TIMER1     (*(unsigned *)(_ISR_STARTADDRESS+0x4C))
 490 #define pISR_TIMER2     (*(unsigned *)(_ISR_STARTADDRESS+0x50))
 491 #define pISR_TIMER3     (*(unsigned *)(_ISR_STARTADDRESS+0x54))
 492 #define pISR_TIMER4     (*(unsigned *)(_ISR_STARTADDRESS+0x58))
 493 #define pISR_UERR01     (*(unsigned *)(_ISR_STARTADDRESS+0x5C))
 494 #define pISR_NOTUSED    (*(unsigned *)(_ISR_STARTADDRESS+0x60))
 495 #define pISR_DMA0       (*(unsigned *)(_ISR_STARTADDRESS+0x64))
 496 #define pISR_DMA1       (*(unsigned *)(_ISR_STARTADDRESS+0x68))
 497 #define pISR_DMA2       (*(unsigned *)(_ISR_STARTADDRESS+0x6C))
 498 #define pISR_DMA3       (*(unsigned *)(_ISR_STARTADDRESS+0x70))
 499 #define pISR_MMC        (*(unsigned *)(_ISR_STARTADDRESS+0x74))
 500 #define pISR_SPI        (*(unsigned *)(_ISR_STARTADDRESS+0x78))
 501 #define pISR_URXD0      (*(unsigned *)(_ISR_STARTADDRESS+0x7C))
 502 #define pISR_URXD1      (*(unsigned *)(_ISR_STARTADDRESS+0x80))
 503 #define pISR_USBD       (*(unsigned *)(_ISR_STARTADDRESS+0x84))
 504 #define pISR_USBH       (*(unsigned *)(_ISR_STARTADDRESS+0x88))
 505 #define pISR_IIC        (*(unsigned *)(_ISR_STARTADDRESS+0x8C))
 506 #define pISR_UTXD0      (*(unsigned *)(_ISR_STARTADDRESS+0x90))
 507 #define pISR_UTXD1      (*(unsigned *)(_ISR_STARTADDRESS+0x94))
 508 #define pISR_RTC        (*(unsigned *)(_ISR_STARTADDRESS+0x98))
 509 #define pISR_ADC        (*(unsigned *)(_ISR_STARTADDRESS+0xA0))
 510
 511
 512 /* PENDING BIT */
 513 #define BIT_EINT0       (0x1)
 514 #define BIT_EINT1       (0x1<<1)
 515 #define BIT_EINT2       (0x1<<2)
 516 #define BIT_EINT3       (0x1<<3)
 517 #define BIT_EINT4       (0x1<<4)
 518 #define BIT_EINT5       (0x1<<5)
 519 #define BIT_EINT6       (0x1<<6)
 520 #define BIT_EINT7       (0x1<<7)
 521 #define BIT_TICK        (0x1<<8)
 522 #define BIT_WDT         (0x1<<9)
 523 #define BIT_TIMER0      (0x1<<10)
 524 #define BIT_TIMER1      (0x1<<11)
 525 #define BIT_TIMER2      (0x1<<12)
 526 #define BIT_TIMER3      (0x1<<13)
 527 #define BIT_TIMER4      (0x1<<14)
 528 #define BIT_UERR01      (0x1<<15)
 529 #define BIT_NOTUSED     (0x1<<16)
 530 #define BIT_DMA0        (0x1<<17)
 531 #define BIT_DMA1        (0x1<<18)
 532 #define BIT_DMA2        (0x1<<19)
 533 #define BIT_DMA3        (0x1<<20)
 534 #define BIT_MMC         (0x1<<21)
 535 #define BIT_SPI         (0x1<<22)
 536 #define BIT_URXD0       (0x1<<23)
 537 #define BIT_URXD1       (0x1<<24)
 538 #define BIT_USBD        (0x1<<25)
 539 #define BIT_USBH        (0x1<<26)
 540 #define BIT_IIC         (0x1<<27)
 541 #define BIT_UTXD0       (0x1<<28)
 542 #define BIT_UTXD1       (0x1<<29)
 543 #define BIT_RTC         (0x1<<30)
 544 #define BIT_ADC         (0x1<<31)
 545 #define BIT_ALLMSK      (0xFFFFFFFF)
 546
 547 #define ClearPending(bit) {\
 548                  rSRCPND = bit;\
 549                  rINTPND = bit;\
 550                  rINTPND;\
 551                  }
 552 /* Wait until rINTPND is changed for the case that the ISR is very short. */
 553 #endif
 554 #endif /*__S3C2400_H__*/