include/ppc440.h

   1 /*----------------------------------------------------------------------------+
   2 |
   3 |       This source code has been made available to you by IBM on an AS-IS
   4 |       basis.  Anyone receiving this source is licensed under IBM
   5 |       copyrights to use it in any way he or she deems fit, including
   6 |       copying it, modifying it, compiling it, and redistributing it either
   7 |       with or without modifications.  No license under IBM patents or
   8 |       patent applications is to be implied by the copyright license.
   9 |
  10 |       Any user of this software should understand that IBM cannot provide
  11 |       technical support for this software and will not be responsible for
  12 |       any consequences resulting from the use of this software.
  13 |
  14 |       Any person who transfers this source code or any derivative work
  15 |       must include the IBM copyright notice, this paragraph, and the
  16 |       preceding two paragraphs in the transferred software.
  17 |
  18 |       COPYRIGHT   I B M   CORPORATION 1999
  19 |       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  20 +----------------------------------------------------------------------------*/
  21
  22 /*
  23  * (C) Copyright 2006
  24  * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
  25  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
  26  * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
  27  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
  28  * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
  29  *
  30  * This program is free software; you can redistribute it and/or
  31  * modify it under the terms of the GNU General Public License as
  32  * published by the Free Software Foundation; either version 2 of
  33  * the License, or (at your option) any later version.
  34  *
  35  * This program is distributed in the hope that it will be useful,
  36  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  37  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  38  * GNU General Public License for more details.
  39  *
  40  * You should have received a copy of the GNU General Public License
  41  * along with this program; if not, write to the Free Software
  42  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  43  * MA 02111-1307 USA
  44  */
  45
  46 #ifndef __PPC440_H__
  47 #define __PPC440_H__
  48
  49 #define CFG_DCACHE_SIZE         (32 << 10)      /* For AMCC 440 CPUs    */
  50
  51 /*--------------------------------------------------------------------- */
  52 /* Special Purpose Registers                                            */
  53 /*--------------------------------------------------------------------- */
  54 #define  xer_reg 0x001
  55 #define  lr_reg 0x008
  56 #define  dec    0x016   /* decrementer */
  57 #define  srr0   0x01a   /* save/restore register 0 */
  58 #define  srr1   0x01b   /* save/restore register 1 */
  59 #define  pid    0x030   /* process id */
  60 #define  decar  0x036   /* decrementer auto-reload */
  61 #define  csrr0  0x03a   /* critical save/restore register 0 */
  62 #define  csrr1  0x03b   /* critical save/restore register 1 */
  63 #define  dear   0x03d   /* data exception address register */
  64 #define  esr    0x03e   /* exception syndrome register */
  65 #define  ivpr   0x03f   /* interrupt prefix register */
  66 #define  usprg0 0x100   /* user special purpose register general 0 */
  67 #define  usprg1 0x110   /* user special purpose register general 1 */
  68 #define  tblr   0x10c   /* time base lower, read only */
  69 #define  tbur   0x10d   /* time base upper, read only */
  70 #define  sprg1  0x111   /* special purpose register general 1 */
  71 #define  sprg2  0x112   /* special purpose register general 2 */
  72 #define  sprg3  0x113   /* special purpose register general 3 */
  73 #define  sprg4  0x114   /* special purpose register general 4 */
  74 #define  sprg5  0x115   /* special purpose register general 5 */
  75 #define  sprg6  0x116   /* special purpose register general 6 */
  76 #define  sprg7  0x117   /* special purpose register general 7 */
  77 #define  tbl    0x11c   /* time base lower (supervisor)*/
  78 #define  tbu    0x11d   /* time base upper (supervisor)*/
  79 #define  pir    0x11e   /* processor id register */
  80 /*#define  pvr  0x11f    processor version register */
  81 #define  dbsr   0x130   /* debug status register */
  82 #define  dbcr0  0x134   /* debug control register 0 */
  83 #define  dbcr1  0x135   /* debug control register 1 */
  84 #define  dbcr2  0x136   /* debug control register 2 */
  85 #define  iac1   0x138   /* instruction address compare 1 */
  86 #define  iac2   0x139   /* instruction address compare 2 */
  87 #define  iac3   0x13a   /* instruction address compare 3 */
  88 #define  iac4   0x13b   /* instruction address compare 4 */
  89 #define  dac1   0x13c   /* data address compare 1 */
  90 #define  dac2   0x13d   /* data address compare 2 */
  91 #define  dvc1   0x13e   /* data value compare 1 */
  92 #define  dvc2   0x13f   /* data value compare 2 */
  93 #define  tsr    0x150   /* timer status register */
  94 #define  tcr    0x154   /* timer control register */
  95 #define  ivor0  0x190   /* interrupt vector offset register 0 */
  96 #define  ivor1  0x191   /* interrupt vector offset register 1 */
  97 #define  ivor2  0x192   /* interrupt vector offset register 2 */
  98 #define  ivor3  0x193   /* interrupt vector offset register 3 */
  99 #define  ivor4  0x194   /* interrupt vector offset register 4 */
 100 #define  ivor5  0x195   /* interrupt vector offset register 5 */
 101 #define  ivor6  0x196   /* interrupt vector offset register 6 */
 102 #define  ivor7  0x197   /* interrupt vector offset register 7 */
 103 #define  ivor8  0x198   /* interrupt vector offset register 8 */
 104 #define  ivor9  0x199   /* interrupt vector offset register 9 */
 105 #define  ivor10 0x19a   /* interrupt vector offset register 10 */
 106 #define  ivor11 0x19b   /* interrupt vector offset register 11 */
 107 #define  ivor12 0x19c   /* interrupt vector offset register 12 */
 108 #define  ivor13 0x19d   /* interrupt vector offset register 13 */
 109 #define  ivor14 0x19e   /* interrupt vector offset register 14 */
 110 #define  ivor15 0x19f   /* interrupt vector offset register 15 */
 111 #if defined(CONFIG_440)
 112 #define  mcsrr0 0x23a   /* machine check save/restore register 0 */
 113 #define  mcsrr1 0x23b   /* mahcine check save/restore register 1 */
 114 #define  mcsr   0x23c   /* machine check status register */
 115 #endif
 116 #define  inv0   0x370   /* instruction cache normal victim 0 */
 117 #define  inv1   0x371   /* instruction cache normal victim 1 */
 118 #define  inv2   0x372   /* instruction cache normal victim 2 */
 119 #define  inv3   0x373   /* instruction cache normal victim 3 */
 120 #define  itv0   0x374   /* instruction cache transient victim 0 */
 121 #define  itv1   0x375   /* instruction cache transient victim 1 */
 122 #define  itv2   0x376   /* instruction cache transient victim 2 */
 123 #define  itv3   0x377   /* instruction cache transient victim 3 */
 124 #define  dnv0   0x390   /* data cache normal victim 0 */
 125 #define  dnv1   0x391   /* data cache normal victim 1 */
 126 #define  dnv2   0x392   /* data cache normal victim 2 */
 127 #define  dnv3   0x393   /* data cache normal victim 3 */
 128 #define  dtv0   0x394   /* data cache transient victim 0 */
 129 #define  dtv1   0x395   /* data cache transient victim 1 */
 130 #define  dtv2   0x396   /* data cache transient victim 2 */
 131 #define  dtv3   0x397   /* data cache transient victim 3 */
 132 #define  dvlim  0x398   /* data cache victim limit */
 133 #define  ivlim  0x399   /* instruction cache victim limit */
 134 #define  rstcfg 0x39b   /* reset configuration */
 135 #define  dcdbtrl 0x39c  /* data cache debug tag register low */
 136 #define  dcdbtrh 0x39d  /* data cache debug tag register high */
 137 #define  icdbtrl 0x39e  /* instruction cache debug tag register low */
 138 #define  icdbtrh 0x39f  /* instruction cache debug tag register high */
 139 #define  mmucr  0x3b2   /* mmu control register */
 140 #define  ccr0   0x3b3   /* core configuration register 0 */
 141 #define  ccr1   0x378   /* core configuration for 440x5 only */
 142 #define  icdbdr 0x3d3   /* instruction cache debug data register */
 143 #define  dbdr   0x3f3   /* debug data register */
 144
 145 /******************************************************************************
 146  * DCRs & Related
 147  ******************************************************************************/
 148
 149 /*-----------------------------------------------------------------------------
 150  | Clocking Controller
 151  +----------------------------------------------------------------------------*/
 152 /* values for clkcfga register - indirect addressing of these regs */
 153 #define clk_clkukpd     0x0020
 154 #define clk_pllc        0x0040
 155 #define clk_plld        0x0060
 156 #define clk_primad      0x0080
 157 #define clk_primbd      0x00a0
 158 #define clk_opbd        0x00c0
 159 #define clk_perd        0x00e0
 160 #define clk_mald        0x0100
 161 #define clk_spcid       0x0120
 162 #define clk_icfg        0x0140
 163
 164 /* 440gx sdr register definations */
 165 #define sdr_sdstp0      0x0020      /* */
 166 #define sdr_sdstp1      0x0021      /* */
 167 #define SDR_PINSTP      0x0040
 168 #define sdr_sdcs        0x0060
 169 #define sdr_ecid0       0x0080
 170 #define sdr_ecid1       0x0081
 171 #define sdr_ecid2       0x0082
 172 #define sdr_jtag        0x00c0
 173 #if !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
 174 #define sdr_ddrdl       0x00e0
 175 #else
 176 #define sdr_cfg         0x00e0
 177 #define SDR_CFG_LT2_MASK          0x01000000 /* Leakage test 2*/
 178 #define SDR_CFG_64_32BITS_MASK    0x01000000 /* Switch DDR 64 bits or 32 bits */
 179 #define SDR_CFG_32BITS            0x00000000  /* 32 bits */
 180 #define SDR_CFG_64BITS            0x01000000  /* 64 bits */
 181 #define SDR_CFG_MC_V2518_MASK     0x02000000 /* Low VDD2518 (2.5 or 1.8V) */
 182 #define SDR_CFG_MC_V25            0x00000000  /* 2.5 V */
 183 #define SDR_CFG_MC_V18            0x02000000  /* 1.8 V */
 184 #endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */
 185 #define sdr_ebc         0x0100
 186 #define sdr_uart0       0x0120  /* UART0 Config */
 187 #define sdr_uart1       0x0121  /* UART1 Config */
 188 #define sdr_uart2       0x0122  /* UART2 Config */
 189 #define sdr_uart3       0x0123  /* UART3 Config */
 190 #define sdr_cp440       0x0180
 191 #define sdr_xcr         0x01c0
 192 #define sdr_xpllc       0x01c1
 193 #define sdr_xplld       0x01c2
 194 #define sdr_srst        0x0200
 195 #define sdr_slpipe      0x0220
 196 #define sdr_amp0        0x0240  /* Override PLB4 prioritiy for up to 8 masters */
 197 #define sdr_amp1        0x0241  /* Override PLB3 prioritiy for up to 8 masters */
 198 #define sdr_mirq0       0x0260
 199 #define sdr_mirq1       0x0261
 200 #define sdr_maltbl      0x0280
 201 #define sdr_malrbl      0x02a0
 202 #define sdr_maltbs      0x02c0
 203 #define sdr_malrbs      0x02e0
 204 #define sdr_pci0        0x0300
 205 #define sdr_usb0        0x0320
 206 #define sdr_cust0       0x4000
 207 #define sdr_cust1       0x4002
 208 #define sdr_pfc0        0x4100  /* Pin Function 0 */
 209 #define sdr_pfc1        0x4101  /* Pin Function 1 */
 210 #define sdr_plbtr       0x4200
 211 #define sdr_mfr         0x4300  /* SDR0_MFR reg */
 212
 213 /*-----------------------------------------------------------------------------
 214  | SDRAM Controller
 215  +----------------------------------------------------------------------------*/
 216 /* values for memcfga register - indirect addressing of these regs          */
 217 #define mem_besr0_clr   0x0000  /* bus error status reg 0 (clr)             */
 218 #define mem_besr0_set   0x0004  /* bus error status reg 0 (set)             */
 219 #define mem_besr1_clr   0x0008  /* bus error status reg 1 (clr)             */
 220 #define mem_besr1_set   0x000c  /* bus error status reg 1 (set)             */
 221 #define mem_bear        0x0010  /* bus error address reg                    */
 222 #define mem_mirq_clr    0x0011  /* bus master interrupt (clr)               */
 223 #define mem_mirq_set    0x0012  /* bus master interrupt (set)               */
 224 #define mem_slio        0x0018  /* ddr sdram slave interface options        */
 225 #define mem_cfg0        0x0020  /* ddr sdram options 0                      */
 226 #define mem_cfg1        0x0021  /* ddr sdram options 1                      */
 227 #define mem_devopt      0x0022  /* ddr sdram device options                 */
 228 #define mem_mcsts       0x0024  /* memory controller status                 */
 229 #define mem_rtr         0x0030  /* refresh timer register                   */
 230 #define mem_pmit        0x0034  /* power management idle timer              */
 231 #define mem_uabba       0x0038  /* plb UABus base address                   */
 232 #define mem_b0cr        0x0040  /* ddr sdram bank 0 configuration           */
 233 #define mem_b1cr        0x0044  /* ddr sdram bank 1 configuration           */
 234 #define mem_b2cr        0x0048  /* ddr sdram bank 2 configuration           */
 235 #define mem_b3cr        0x004c  /* ddr sdram bank 3 configuration           */
 236 #define mem_tr0         0x0080  /* sdram timing register 0                  */
 237 #define mem_tr1         0x0081  /* sdram timing register 1                  */
 238 #define mem_clktr       0x0082  /* ddr clock timing register                */
 239 #define mem_wddctr      0x0083  /* write data/dm/dqs clock timing reg       */
 240 #define mem_dlycal      0x0084  /* delay line calibration register          */
 241 #define mem_eccesr      0x0098  /* ECC error status                         */
 242
 243 #ifdef CONFIG_440GX
 244 #define sdr_amp         0x0240
 245 #define sdr_xpllc       0x01c1
 246 #define sdr_xplld       0x01c2
 247 #define sdr_xcr         0x01c0
 248 #define sdr_sdstp2      0x4001
 249 #define sdr_sdstp3      0x4003
 250 #endif  /* CONFIG_440GX */
 251
 252 /*----------------------------------------------------------------------------+
 253 | Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
 254 +----------------------------------------------------------------------------*/
 255 #define CCR0_PRE                0x40000000
 256 #define CCR0_CRPE               0x08000000
 257 #define CCR0_DSTG               0x00200000
 258 #define CCR0_DAPUIB             0x00100000
 259 #define CCR0_DTB                0x00008000
 260 #define CCR0_GICBT              0x00004000
 261 #define CCR0_GDCBT              0x00002000
 262 #define CCR0_FLSTA              0x00000100
 263 #define CCR0_ICSLC_MASK         0x0000000C
 264 #define CCR0_ICSLT_MASK         0x00000003
 265 #define CCR1_TCS_MASK           0x00000080
 266 #define CCR1_TCS_INTCLK         0x00000000
 267 #define CCR1_TCS_EXTCLK         0x00000080
 268 #define MMUCR_SWOA              0x01000000
 269 #define MMUCR_U1TE              0x00400000
 270 #define MMUCR_U2SWOAE           0x00200000
 271 #define MMUCR_DULXE             0x00800000
 272 #define MMUCR_IULXE             0x00400000
 273 #define MMUCR_STS               0x00100000
 274 #define MMUCR_STID_MASK         0x000000FF
 275
 276 #ifdef CONFIG_440SPE
 277 #undef sdr_sdstp2
 278 #define sdr_sdstp2      0x0022
 279 #undef sdr_sdstp3
 280 #define sdr_sdstp3      0x0023
 281 #define sdr_ddr0        0x00E1
 282 #define sdr_uart2       0x0122
 283 #define sdr_xcr0        0x01c0
 284 /* #define sdr_xcr1     0x01c3  only one PCIX - SG */
 285 /* #define sdr_xcr2     0x01c6  only one PCIX - SG */
 286 #define sdr_xpllc0      0x01c1
 287 #define sdr_xplld0      0x01c2
 288 #define sdr_xpllc1      0x01c4  /*notRCW  - SG */
 289 #define sdr_xplld1      0x01c5  /*notRCW  - SG */
 290 #define sdr_xpllc2      0x01c7  /*notRCW  - SG */
 291 #define sdr_xplld2      0x01c8  /*notRCW  - SG */
 292 #define sdr_amp0        0x0240
 293 #define sdr_amp1        0x0241
 294 #define sdr_cust2       0x4004
 295 #define sdr_cust3       0x4006
 296 #define sdr_sdstp4      0x4001
 297 #define sdr_sdstp5      0x4003
 298 #define sdr_sdstp6      0x4005
 299 #define sdr_sdstp7      0x4007
 300
 301 /******************************************************************************
 302  * PCI express defines
 303  ******************************************************************************/
 304 #define SDR0_PE0UTLSET1         0x00000300      /* PE0 Upper transaction layer conf setting */
 305 #define SDR0_PE0UTLSET2         0x00000301      /* PE0 Upper transaction layer conf setting 2 */
 306 #define SDR0_PE0DLPSET          0x00000302      /* PE0 Data link & logical physical configuration */
 307 #define SDR0_PE0LOOP            0x00000303      /* PE0 Loopback interface status */
 308 #define SDR0_PE0RCSSET          0x00000304      /* PE0 Reset, clock & shutdown setting */
 309 #define SDR0_PE0RCSSTS          0x00000305      /* PE0 Reset, clock & shutdown status */
 310 #define SDR0_PE0HSSSET1L0       0x00000306      /* PE0 HSS Control Setting 1: Lane 0 */
 311 #define SDR0_PE0HSSSET2L0       0x00000307      /* PE0 HSS Control Setting 2: Lane 0 */
 312 #define SDR0_PE0HSSSTSL0        0x00000308      /* PE0 HSS Control Status : Lane 0 */
 313 #define SDR0_PE0HSSSET1L1       0x00000309      /* PE0 HSS Control Setting 1: Lane 1 */
 314 #define SDR0_PE0HSSSET2L1       0x0000030A      /* PE0 HSS Control Setting 2: Lane 1 */
 315 #define SDR0_PE0HSSSTSL1        0x0000030B      /* PE0 HSS Control Status : Lane 1 */
 316 #define SDR0_PE0HSSSET1L2       0x0000030C      /* PE0 HSS Control Setting 1: Lane 2 */
 317 #define SDR0_PE0HSSSET2L2       0x0000030D      /* PE0 HSS Control Setting 2: Lane 2 */
 318 #define SDR0_PE0HSSSTSL2        0x0000030E      /* PE0 HSS Control Status : Lane 2 */
 319 #define SDR0_PE0HSSSET1L3       0x0000030F      /* PE0 HSS Control Setting 1: Lane 3 */
 320 #define SDR0_PE0HSSSET2L3       0x00000310      /* PE0 HSS Control Setting 2: Lane 3 */
 321 #define SDR0_PE0HSSSTSL3        0x00000311      /* PE0 HSS Control Status : Lane 3 */
 322 #define SDR0_PE0HSSSET1L4       0x00000312      /* PE0 HSS Control Setting 1: Lane 4 */
 323 #define SDR0_PE0HSSSET2L4       0x00000313      /* PE0 HSS Control Setting 2: Lane 4 */
 324 #define SDR0_PE0HSSSTSL4        0x00000314      /* PE0 HSS Control Status : Lane 4 */
 325 #define SDR0_PE0HSSSET1L5       0x00000315      /* PE0 HSS Control Setting 1: Lane 5 */
 326 #define SDR0_PE0HSSSET2L5       0x00000316      /* PE0 HSS Control Setting 2: Lane 5 */
 327 #define SDR0_PE0HSSSTSL5        0x00000317      /* PE0 HSS Control Status : Lane 5 */
 328 #define SDR0_PE0HSSSET1L6       0x00000318      /* PE0 HSS Control Setting 1: Lane 6 */
 329 #define SDR0_PE0HSSSET2L6       0x00000319      /* PE0 HSS Control Setting 2: Lane 6 */
 330 #define SDR0_PE0HSSSTSL6        0x0000031A      /* PE0 HSS Control Status : Lane 6 */
 331 #define SDR0_PE0HSSSET1L7       0x0000031B      /* PE0 HSS Control Setting 1: Lane 7 */
 332 #define SDR0_PE0HSSSET2L7       0x0000031C      /* PE0 HSS Control Setting 2: Lane 7 */
 333 #define SDR0_PE0HSSSTSL7        0x0000031D      /* PE0 HSS Control Status : Lane 7 */
 334 #define SDR0_PE0HSSSEREN        0x0000031E      /* PE0 Serdes Transmitter Enable */
 335 #define SDR0_PE0LANEABCD        0x0000031F      /* PE0 Lanes ABCD affectation */
 336 #define SDR0_PE0LANEEFGH        0x00000320      /* PE0 Lanes EFGH affectation */
 337
 338 #define SDR0_PE1UTLSET1         0x00000340      /* PE1 Upper transaction layer conf setting */
 339 #define SDR0_PE1UTLSET2         0x00000341      /* PE1 Upper transaction layer conf setting 2 */
 340 #define SDR0_PE1DLPSET          0x00000342      /* PE1 Data link & logical physical configuration */
 341 #define SDR0_PE1LOOP            0x00000343      /* PE1 Loopback interface status */
 342 #define SDR0_PE1RCSSET          0x00000344      /* PE1 Reset, clock & shutdown setting */
 343 #define SDR0_PE1RCSSTS          0x00000345      /* PE1 Reset, clock & shutdown status */
 344 #define SDR0_PE1HSSSET1L0       0x00000346      /* PE1 HSS Control Setting 1: Lane 0 */
 345 #define SDR0_PE1HSSSET2L0       0x00000347      /* PE1 HSS Control Setting 2: Lane 0 */
 346 #define SDR0_PE1HSSSTSL0        0x00000348      /* PE1 HSS Control Status : Lane 0 */
 347 #define SDR0_PE1HSSSET1L1       0x00000349      /* PE1 HSS Control Setting 1: Lane 1 */
 348 #define SDR0_PE1HSSSET2L1       0x0000034A      /* PE1 HSS Control Setting 2: Lane 1 */
 349 #define SDR0_PE1HSSSTSL1        0x0000034B      /* PE1 HSS Control Status : Lane 1 */
 350 #define SDR0_PE1HSSSET1L2       0x0000034C      /* PE1 HSS Control Setting 1: Lane 2 */
 351 #define SDR0_PE1HSSSET2L2       0x0000034D      /* PE1 HSS Control Setting 2: Lane 2 */
 352 #define SDR0_PE1HSSSTSL2        0x0000034E      /* PE1 HSS Control Status : Lane 2 */
 353 #define SDR0_PE1HSSSET1L3       0x0000034F      /* PE1 HSS Control Setting 1: Lane 3 */
 354 #define SDR0_PE1HSSSET2L3       0x00000350      /* PE1 HSS Control Setting 2: Lane 3 */
 355 #define SDR0_PE1HSSSTSL3        0x00000351      /* PE1 HSS Control Status : Lane 3 */
 356 #define SDR0_PE1HSSSEREN        0x00000352      /* PE1 Serdes Transmitter Enable */
 357 #define SDR0_PE1LANEABCD        0x00000353      /* PE1 Lanes ABCD affectation */
 358 #define SDR0_PE2UTLSET1         0x00000370      /* PE2 Upper transaction layer conf setting */
 359 #define SDR0_PE2UTLSET2         0x00000371      /* PE2 Upper transaction layer conf setting 2 */
 360 #define SDR0_PE2DLPSET          0x00000372      /* PE2 Data link & logical physical configuration */
 361 #define SDR0_PE2LOOP            0x00000373      /* PE2 Loopback interface status */
 362 #define SDR0_PE2RCSSET          0x00000374      /* PE2 Reset, clock & shutdown setting */
 363 #define SDR0_PE2RCSSTS          0x00000375      /* PE2 Reset, clock & shutdown status */
 364 #define SDR0_PE2HSSSET1L0       0x00000376      /* PE2 HSS Control Setting 1: Lane 0 */
 365 #define SDR0_PE2HSSSET2L0       0x00000377      /* PE2 HSS Control Setting 2: Lane 0 */
 366 #define SDR0_PE2HSSSTSL0        0x00000378      /* PE2 HSS Control Status : Lane 0 */
 367 #define SDR0_PE2HSSSET1L1       0x00000379      /* PE2 HSS Control Setting 1: Lane 1 */
 368 #define SDR0_PE2HSSSET2L1       0x0000037A      /* PE2 HSS Control Setting 2: Lane 1 */
 369 #define SDR0_PE2HSSSTSL1        0x0000037B      /* PE2 HSS Control Status : Lane 1 */
 370 #define SDR0_PE2HSSSET1L2       0x0000037C      /* PE2 HSS Control Setting 1: Lane 2 */
 371 #define SDR0_PE2HSSSET2L2       0x0000037D      /* PE2 HSS Control Setting 2: Lane 2 */
 372 #define SDR0_PE2HSSSTSL2        0x0000037E      /* PE2 HSS Control Status : Lane 2 */
 373 #define SDR0_PE2HSSSET1L3       0x0000037F      /* PE2 HSS Control Setting 1: Lane 3 */
 374 #define SDR0_PE2HSSSET2L3       0x00000380      /* PE2 HSS Control Setting 2: Lane 3 */
 375 #define SDR0_PE2HSSSTSL3        0x00000381      /* PE2 HSS Control Status : Lane 3 */
 376 #define SDR0_PE2HSSSEREN        0x00000382      /* PE2 Serdes Transmitter Enable */
 377 #define SDR0_PE2LANEABCD        0x00000383      /* PE2 Lanes ABCD affectation */
 378 #define SDR0_PEGPLLSET1         0x000003A0      /* PE Pll LC Tank Setting1 */
 379 #define SDR0_PEGPLLSET2         0x000003A1      /* PE Pll LC Tank Setting2 */
 380 #define SDR0_PEGPLLSTS          0x000003A2      /* PE Pll LC Tank Status */
 381 #endif /* CONFIG_440SPE */
 382
 383 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
 384     defined(CONFIG_460EX) || defined(CONFIG_460GT)
 385 /*----------------------------------------------------------------------------+
 386 | SDRAM Controller
 387 +----------------------------------------------------------------------------*/
 388 /*-----------------------------------------------------------------------------+
 389 | SDRAM DLYCAL Options
 390 +-----------------------------------------------------------------------------*/
 391 #define SDRAM_DLYCAL_DLCV_MASK          0x000003FC
 392 #define SDRAM_DLYCAL_DLCV_ENCODE(x)     (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
 393 #define SDRAM_DLYCAL_DLCV_DECODE(x)     (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
 394
 395 /*----------------------------------------------------------------------------+
 396 | Memory queue defines
 397 +----------------------------------------------------------------------------*/
 398 /* A REVOIR versus RWC  - SG*/
 399 #define SDRAMQ_DCR_BASE 0x040
 400
 401 #define SDRAM_R0BAS     (SDRAMQ_DCR_BASE+0x0)   /* rank 0 base address & size  */
 402 #define SDRAM_R1BAS     (SDRAMQ_DCR_BASE+0x1)   /* rank 1 base address & size  */
 403 #define SDRAM_R2BAS     (SDRAMQ_DCR_BASE+0x2)   /* rank 2 base address & size  */
 404 #define SDRAM_R3BAS     (SDRAMQ_DCR_BASE+0x3)   /* rank 3 base address & size  */
 405 #define SDRAM_CONF1HB   (SDRAMQ_DCR_BASE+0x5)   /* configuration 1 HB          */
 406 #define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7)   /* error status HB             */
 407 #define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8)   /* error address upper 32 HB   */
 408 #define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9)   /* error address lower 32 HB   */
 409 #define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA)   /* PLB base address upper 32 LL */
 410 #define SDRAM_CONF1LL   (SDRAMQ_DCR_BASE+0xB)   /* configuration 1 LL          */
 411 #define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC)   /* error status LL             */
 412 #define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD)   /* error address upper 32 LL   */
 413 #define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE)   /* error address lower 32 LL   */
 414 #define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF)   /* configuration between paths */
 415 #define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10)  /* PLB base address upper 32 LL */
 416
 417 /*-----------------------------------------------------------------------------+
 418 |  Memory Bank 0-7 configuration
 419 +-----------------------------------------------------------------------------*/
 420 #if defined(CONFIG_440SPE) || \
 421     defined(CONFIG_460EX) || defined(CONFIG_460GT)
 422 #define SDRAM_RXBAS_SDBA_MASK           0xFFE00000      /* Base address */
 423 #define SDRAM_RXBAS_SDBA_ENCODE(n)      ((((unsigned long)(n))&0xFFE00000)>>2)
 424 #define SDRAM_RXBAS_SDBA_DECODE(n)      ((((unsigned long)(n))&0xFFE00000)<<2)
 425 #endif /* CONFIG_440SPE */
 426 #if defined(CONFIG_440SP)
 427 #define SDRAM_RXBAS_SDBA_MASK           0xFF800000      /* Base address */
 428 #define SDRAM_RXBAS_SDBA_ENCODE(n)      ((((unsigned long)(n))&0xFF800000))
 429 #define SDRAM_RXBAS_SDBA_DECODE(n)      ((((unsigned long)(n))&0xFF800000))
 430 #endif /* CONFIG_440SP */
 431 #define SDRAM_RXBAS_SDSZ_MASK           0x0000FFC0      /* Size         */
 432 #define SDRAM_RXBAS_SDSZ_ENCODE(n)      ((((unsigned long)(n))&0x3FF)<<6)
 433 #define SDRAM_RXBAS_SDSZ_DECODE(n)      ((((unsigned long)(n))>>6)&0x3FF)
 434 #define SDRAM_RXBAS_SDSZ_0              0x00000000      /*   0M         */
 435 #define SDRAM_RXBAS_SDSZ_8              0x0000FFC0      /*   8M         */
 436 #define SDRAM_RXBAS_SDSZ_16             0x0000FF80      /*  16M         */
 437 #define SDRAM_RXBAS_SDSZ_32             0x0000FF00      /*  32M         */
 438 #define SDRAM_RXBAS_SDSZ_64             0x0000FE00      /*  64M         */
 439 #define SDRAM_RXBAS_SDSZ_128            0x0000FC00      /* 128M         */
 440 #define SDRAM_RXBAS_SDSZ_256            0x0000F800      /* 256M         */
 441 #define SDRAM_RXBAS_SDSZ_512            0x0000F000      /* 512M         */
 442 #define SDRAM_RXBAS_SDSZ_1024           0x0000E000      /* 1024M        */
 443 #define SDRAM_RXBAS_SDSZ_2048           0x0000C000      /* 2048M        */
 444 #define SDRAM_RXBAS_SDSZ_4096           0x00008000      /* 4096M        */
 445
 446 /*----------------------------------------------------------------------------+
 447 | Memory controller defines
 448 +----------------------------------------------------------------------------*/
 449 /* A REVOIR versus specs 4 bank  - SG*/
 450 #define SDRAM_MCSTAT    0x14    /* memory controller status                  */
 451 #define SDRAM_MCOPT1    0x20    /* memory controller options 1               */
 452 #define SDRAM_MCOPT2    0x21    /* memory controller options 2               */
 453 #define SDRAM_MODT0     0x22    /* on die termination for bank 0             */
 454 #define SDRAM_MODT1     0x23    /* on die termination for bank 1             */
 455 #define SDRAM_MODT2     0x24    /* on die termination for bank 2             */
 456 #define SDRAM_MODT3     0x25    /* on die termination for bank 3             */
 457 #define SDRAM_CODT      0x26    /* on die termination for controller         */
 458 #define SDRAM_VVPR      0x27    /* variable VRef programmming                */
 459 #define SDRAM_OPARS     0x28    /* on chip driver control setup              */
 460 #define SDRAM_OPART     0x29    /* on chip driver control trigger            */
 461 #define SDRAM_RTR       0x30    /* refresh timer                             */
 462 #define SDRAM_PMIT      0x34    /* power management idle timer               */
 463 #define SDRAM_MB0CF     0x40    /* memory bank 0 configuration               */
 464 #define SDRAM_MB1CF     0x44    /* memory bank 1 configuration               */
 465 #define SDRAM_MB2CF     0x48
 466 #define SDRAM_MB3CF     0x4C
 467 #define SDRAM_INITPLR0  0x50    /* manual initialization control             */
 468 #define SDRAM_INITPLR1  0x51    /* manual initialization control             */
 469 #define SDRAM_INITPLR2  0x52    /* manual initialization control             */
 470 #define SDRAM_INITPLR3  0x53    /* manual initialization control             */
 471 #define SDRAM_INITPLR4  0x54    /* manual initialization control             */
 472 #define SDRAM_INITPLR5  0x55    /* manual initialization control             */
 473 #define SDRAM_INITPLR6  0x56    /* manual initialization control             */
 474 #define SDRAM_INITPLR7  0x57    /* manual initialization control             */
 475 #define SDRAM_INITPLR8  0x58    /* manual initialization control             */
 476 #define SDRAM_INITPLR9  0x59    /* manual initialization control             */
 477 #define SDRAM_INITPLR10 0x5a    /* manual initialization control             */
 478 #define SDRAM_INITPLR11 0x5b    /* manual initialization control             */
 479 #define SDRAM_INITPLR12 0x5c    /* manual initialization control             */
 480 #define SDRAM_INITPLR13 0x5d    /* manual initialization control             */
 481 #define SDRAM_INITPLR14 0x5e    /* manual initialization control             */
 482 #define SDRAM_INITPLR15 0x5f    /* manual initialization control             */
 483 #define SDRAM_RQDC      0x70    /* read DQS delay control                    */
 484 #define SDRAM_RFDC      0x74    /* read feedback delay control               */
 485 #define SDRAM_RDCC      0x78    /* read data capture control                 */
 486 #define SDRAM_DLCR      0x7A    /* delay line calibration                    */
 487 #define SDRAM_CLKTR     0x80    /* DDR clock timing                          */
 488 #define SDRAM_WRDTR     0x81    /* write data, DQS, DM clock, timing         */
 489 #define SDRAM_SDTR1     0x85    /* DDR SDRAM timing 1                        */
 490 #define SDRAM_SDTR2     0x86    /* DDR SDRAM timing 2                        */
 491 #define SDRAM_SDTR3     0x87    /* DDR SDRAM timing 3                        */
 492 #define SDRAM_MMODE     0x88    /* memory mode                               */
 493 #define SDRAM_MEMODE    0x89    /* memory extended mode                      */
 494 #define SDRAM_ECCCR     0x98    /* ECC error status                          */
 495 #define SDRAM_CID       0xA4    /* core ID                                   */
 496 #define SDRAM_RID       0xA8    /* revision ID                               */
 497 #define SDRAM_RTSR      0xB1    /* run time status tracking                  */
 498
 499 /*-----------------------------------------------------------------------------+
 500 |  Memory Controller Status
 501 +-----------------------------------------------------------------------------*/
 502 #define SDRAM_MCSTAT_MIC_MASK           0x80000000      /* Memory init status mask      */
 503 #define SDRAM_MCSTAT_MIC_NOTCOMP        0x00000000      /* Mem init not complete        */
 504 #define SDRAM_MCSTAT_MIC_COMP           0x80000000      /* Mem init complete            */
 505 #define SDRAM_MCSTAT_SRMS_MASK          0x40000000      /* Mem self refresh stat mask   */
 506 #define SDRAM_MCSTAT_SRMS_NOT_SF        0x00000000      /* Mem not in self refresh      */
 507 #define SDRAM_MCSTAT_SRMS_SF            0x40000000      /* Mem in self refresh          */
 508 #define SDRAM_MCSTAT_IDLE_MASK          0x20000000      /* Mem self refresh stat mask   */
 509 #define SDRAM_MCSTAT_IDLE_NOT           0x00000000      /* Mem contr not idle           */
 510 #define SDRAM_MCSTAT_IDLE               0x20000000      /* Mem contr idle               */
 511
 512 /*-----------------------------------------------------------------------------+
 513 |  Memory Controller Options 1
 514 +-----------------------------------------------------------------------------*/
 515 #define SDRAM_MCOPT1_MCHK_MASK          0x30000000 /* Memory data err check mask*/
 516 #define SDRAM_MCOPT1_MCHK_NON           0x00000000 /* No ECC generation         */
 517 #define SDRAM_MCOPT1_MCHK_GEN           0x20000000 /* ECC generation            */
 518 #define SDRAM_MCOPT1_MCHK_CHK           0x10000000 /* ECC generation and check  */
 519 #define SDRAM_MCOPT1_MCHK_CHK_REP       0x30000000 /* ECC generation, chk, report*/
 520 #define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((unsigned long)(n))>>28)&0x3)
 521 #define SDRAM_MCOPT1_RDEN_MASK          0x08000000 /* Registered DIMM mask      */
 522 #define SDRAM_MCOPT1_RDEN               0x08000000 /* Registered DIMM enable    */
 523 #define SDRAM_MCOPT1_PMU_MASK           0x06000000 /* Page management unit mask */
 524 #define SDRAM_MCOPT1_PMU_CLOSE          0x00000000 /* PMU Close                 */
 525 #define SDRAM_MCOPT1_PMU_OPEN           0x04000000 /* PMU Open                  */
 526 #define SDRAM_MCOPT1_PMU_AUTOCLOSE      0x02000000 /* PMU AutoClose             */
 527 #define SDRAM_MCOPT1_DMWD_MASK          0x01000000 /* DRAM width mask           */
 528 #define SDRAM_MCOPT1_DMWD_32            0x00000000 /* 32 bits                   */
 529 #define SDRAM_MCOPT1_DMWD_64            0x01000000 /* 64 bits                   */
 530 #define SDRAM_MCOPT1_UIOS_MASK          0x00C00000 /* Unused IO State           */
 531 #define SDRAM_MCOPT1_BCNT_MASK          0x00200000 /* Bank count                */
 532 #define SDRAM_MCOPT1_4_BANKS            0x00000000 /* 4 Banks                   */
 533 #define SDRAM_MCOPT1_8_BANKS            0x00200000 /* 8 Banks                   */
 534 #define SDRAM_MCOPT1_DDR_TYPE_MASK      0x00100000 /* DDR Memory Type mask      */
 535 #define SDRAM_MCOPT1_DDR1_TYPE          0x00000000 /* DDR1 Memory Type          */
 536 #define SDRAM_MCOPT1_DDR2_TYPE          0x00100000 /* DDR2 Memory Type          */
 537 #define SDRAM_MCOPT1_QDEP               0x00020000 /* 4 commands deep           */
 538 #define SDRAM_MCOPT1_RWOO_MASK          0x00008000 /* Out of Order Read mask    */
 539 #define SDRAM_MCOPT1_RWOO_DISABLED      0x00000000 /* disabled                  */
 540 #define SDRAM_MCOPT1_RWOO_ENABLED       0x00008000 /* enabled                   */
 541 #define SDRAM_MCOPT1_WOOO_MASK          0x00004000 /* Out of Order Write mask   */
 542 #define SDRAM_MCOPT1_WOOO_DISABLED      0x00000000 /* disabled                  */
 543 #define SDRAM_MCOPT1_WOOO_ENABLED       0x00004000 /* enabled                   */
 544 #define SDRAM_MCOPT1_DCOO_MASK          0x00002000 /* All Out of Order mask     */
 545 #define SDRAM_MCOPT1_DCOO_DISABLED      0x00002000 /* disabled                  */
 546 #define SDRAM_MCOPT1_DCOO_ENABLED       0x00000000 /* enabled                   */
 547 #define SDRAM_MCOPT1_DREF_MASK          0x00001000 /* Deferred refresh mask     */
 548 #define SDRAM_MCOPT1_DREF_NORMAL        0x00000000 /* normal refresh            */
 549 #define SDRAM_MCOPT1_DREF_DEFER_4       0x00001000 /* defer up to 4 refresh cmd */
 550
 551 /*-----------------------------------------------------------------------------+
 552 |  Memory Controller Options 2
 553 +-----------------------------------------------------------------------------*/
 554 #define SDRAM_MCOPT2_SREN_MASK          0x80000000 /* Self Test mask            */
 555 #define SDRAM_MCOPT2_SREN_EXIT          0x00000000 /* Self Test exit            */
 556 #define SDRAM_MCOPT2_SREN_ENTER         0x80000000 /* Self Test enter           */
 557 #define SDRAM_MCOPT2_PMEN_MASK          0x40000000 /* Power Management mask     */
 558 #define SDRAM_MCOPT2_PMEN_DISABLE       0x00000000 /* disable                   */
 559 #define SDRAM_MCOPT2_PMEN_ENABLE        0x40000000 /* enable                    */
 560 #define SDRAM_MCOPT2_IPTR_MASK          0x20000000 /* Init Trigger Reg mask     */
 561 #define SDRAM_MCOPT2_IPTR_IDLE          0x00000000 /* idle                      */
 562 #define SDRAM_MCOPT2_IPTR_EXECUTE       0x20000000 /* execute preloaded init    */
 563 #define SDRAM_MCOPT2_XSRP_MASK          0x10000000 /* Exit Self Refresh Prevent */
 564 #define SDRAM_MCOPT2_XSRP_ALLOW         0x00000000 /* allow self refresh exit   */
 565 #define SDRAM_MCOPT2_XSRP_PREVENT       0x10000000 /* prevent self refresh exit */
 566 #define SDRAM_MCOPT2_DCEN_MASK          0x08000000 /* SDRAM Controller Enable   */
 567 #define SDRAM_MCOPT2_DCEN_DISABLE       0x00000000 /* SDRAM Controller Enable   */
 568 #define SDRAM_MCOPT2_DCEN_ENABLE        0x08000000 /* SDRAM Controller Enable   */
 569 #define SDRAM_MCOPT2_ISIE_MASK          0x04000000 /* Init Seq Interruptable mas*/
 570 #define SDRAM_MCOPT2_ISIE_DISABLE       0x00000000 /* disable                   */
 571 #define SDRAM_MCOPT2_ISIE_ENABLE        0x04000000 /* enable                    */
 572
 573 /*-----------------------------------------------------------------------------+
 574 |  SDRAM Refresh Timer Register
 575 +-----------------------------------------------------------------------------*/
 576 #define SDRAM_RTR_RINT_MASK             0xFFF80000
 577 #define SDRAM_RTR_RINT_ENCODE(n)        ((((unsigned long)(n))&0xFFF8)<<16)
 578 #define SDRAM_RTR_RINT_DECODE(n)        ((((unsigned long)(n))>>16)&0xFFF8)
 579
 580 /*-----------------------------------------------------------------------------+
 581 |  SDRAM Read DQS Delay Control Register
 582 +-----------------------------------------------------------------------------*/
 583 #define SDRAM_RQDC_RQDE_MASK            0x80000000
 584 #define SDRAM_RQDC_RQDE_DISABLE         0x00000000
 585 #define SDRAM_RQDC_RQDE_ENABLE          0x80000000
 586 #define SDRAM_RQDC_RQFD_MASK            0x000001FF
 587 #define SDRAM_RQDC_RQFD_ENCODE(n)       ((((unsigned long)(n))&0x1FF)<<0)
 588
 589 #define SDRAM_RQDC_RQFD_MAX             0x1FF
 590
 591 /*-----------------------------------------------------------------------------+
 592 |  SDRAM Read Data Capture Control Register
 593 +-----------------------------------------------------------------------------*/
 594 #define SDRAM_RDCC_RDSS_MASK            0xC0000000
 595 #define SDRAM_RDCC_RDSS_T1              0x00000000
 596 #define SDRAM_RDCC_RDSS_T2              0x40000000
 597 #define SDRAM_RDCC_RDSS_T3              0x80000000
 598 #define SDRAM_RDCC_RDSS_T4              0xC0000000
 599 #define SDRAM_RDCC_RSAE_MASK            0x00000001
 600 #define SDRAM_RDCC_RSAE_DISABLE         0x00000001
 601 #define SDRAM_RDCC_RSAE_ENABLE          0x00000000
 602
 603 /*-----------------------------------------------------------------------------+
 604 |  SDRAM Read Feedback Delay Control Register
 605 +-----------------------------------------------------------------------------*/
 606 #define SDRAM_RFDC_ARSE_MASK            0x80000000
 607 #define SDRAM_RFDC_ARSE_DISABLE         0x80000000
 608 #define SDRAM_RFDC_ARSE_ENABLE          0x00000000
 609 #define SDRAM_RFDC_RFOS_MASK            0x007F0000
 610 #define SDRAM_RFDC_RFOS_ENCODE(n)       ((((unsigned long)(n))&0x7F)<<16)
 611 #define SDRAM_RFDC_RFFD_MASK            0x000007FF
 612 #define SDRAM_RFDC_RFFD_ENCODE(n)       ((((unsigned long)(n))&0x7FF)<<0)
 613
 614 #define SDRAM_RFDC_RFFD_MAX             0x7FF
 615
 616 /*-----------------------------------------------------------------------------+
 617 |  SDRAM Delay Line Calibration Register
 618 +-----------------------------------------------------------------------------*/
 619 #define SDRAM_DLCR_DCLM_MASK            0x80000000
 620 #define SDRAM_DLCR_DCLM_MANUEL          0x80000000
 621 #define SDRAM_DLCR_DCLM_AUTO            0x00000000
 622 #define SDRAM_DLCR_DLCR_MASK            0x08000000
 623 #define SDRAM_DLCR_DLCR_CALIBRATE       0x08000000
 624 #define SDRAM_DLCR_DLCR_IDLE            0x00000000
 625 #define SDRAM_DLCR_DLCS_MASK            0x07000000
 626 #define SDRAM_DLCR_DLCS_NOT_RUN         0x00000000
 627 #define SDRAM_DLCR_DLCS_IN_PROGRESS     0x01000000
 628 #define SDRAM_DLCR_DLCS_COMPLETE        0x02000000
 629 #define SDRAM_DLCR_DLCS_CONT_DONE       0x03000000
 630 #define SDRAM_DLCR_DLCS_ERROR           0x04000000
 631 #define SDRAM_DLCR_DLCV_MASK            0x000001FF
 632 #define SDRAM_DLCR_DLCV_ENCODE(n)       ((((unsigned long)(n))&0x1FF)<<0)
 633 #define SDRAM_DLCR_DLCV_DECODE(n)       ((((unsigned long)(n))>>0)&0x1FF)
 634
 635 /*-----------------------------------------------------------------------------+
 636 |  SDRAM Controller On Die Termination Register
 637 +-----------------------------------------------------------------------------*/
 638 #define SDRAM_CODT_ODT_ON                       0x80000000
 639 #define SDRAM_CODT_ODT_OFF                      0x00000000
 640 #define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK         0x00000020
 641 #define SDRAM_CODT_DQS_2_5_V_DDR1               0x00000000
 642 #define SDRAM_CODT_DQS_1_8_V_DDR2               0x00000020
 643 #define SDRAM_CODT_DQS_MASK                     0x00000010
 644 #define SDRAM_CODT_DQS_DIFFERENTIAL             0x00000000
 645 #define SDRAM_CODT_DQS_SINGLE_END               0x00000010
 646 #define SDRAM_CODT_CKSE_DIFFERENTIAL            0x00000000
 647 #define SDRAM_CODT_CKSE_SINGLE_END              0x00000008
 648 #define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END      0x00000004
 649 #define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END      0x00000002
 650 #define SDRAM_CODT_IO_HIZ                       0x00000000
 651 #define SDRAM_CODT_IO_NMODE                     0x00000001
 652
 653 /*-----------------------------------------------------------------------------+
 654 |  SDRAM Mode Register
 655 +-----------------------------------------------------------------------------*/
 656 #define SDRAM_MMODE_WR_MASK             0x00000E00
 657 #define SDRAM_MMODE_WR_DDR1             0x00000000
 658 #define SDRAM_MMODE_WR_DDR2_3_CYC       0x00000400
 659 #define SDRAM_MMODE_WR_DDR2_4_CYC       0x00000600
 660 #define SDRAM_MMODE_WR_DDR2_5_CYC       0x00000800
 661 #define SDRAM_MMODE_WR_DDR2_6_CYC       0x00000A00
 662 #define SDRAM_MMODE_DCL_MASK            0x00000070
 663 #define SDRAM_MMODE_DCL_DDR1_2_0_CLK    0x00000020
 664 #define SDRAM_MMODE_DCL_DDR1_2_5_CLK    0x00000060
 665 #define SDRAM_MMODE_DCL_DDR1_3_0_CLK    0x00000030
 666 #define SDRAM_MMODE_DCL_DDR2_2_0_CLK    0x00000020
 667 #define SDRAM_MMODE_DCL_DDR2_3_0_CLK    0x00000030
 668 #define SDRAM_MMODE_DCL_DDR2_4_0_CLK    0x00000040
 669 #define SDRAM_MMODE_DCL_DDR2_5_0_CLK    0x00000050
 670 #define SDRAM_MMODE_DCL_DDR2_6_0_CLK    0x00000060
 671 #define SDRAM_MMODE_DCL_DDR2_7_0_CLK    0x00000070
 672
 673 /*-----------------------------------------------------------------------------+
 674 |  SDRAM Extended Mode Register
 675 +-----------------------------------------------------------------------------*/
 676 #define SDRAM_MEMODE_DIC_MASK           0x00000002
 677 #define SDRAM_MEMODE_DIC_NORMAL         0x00000000
 678 #define SDRAM_MEMODE_DIC_WEAK           0x00000002
 679 #define SDRAM_MEMODE_DLL_MASK           0x00000001
 680 #define SDRAM_MEMODE_DLL_DISABLE        0x00000001
 681 #define SDRAM_MEMODE_DLL_ENABLE         0x00000000
 682 #define SDRAM_MEMODE_RTT_MASK           0x00000044
 683 #define SDRAM_MEMODE_RTT_DISABLED       0x00000000
 684 #define SDRAM_MEMODE_RTT_75OHM          0x00000004
 685 #define SDRAM_MEMODE_RTT_150OHM         0x00000040
 686 #define SDRAM_MEMODE_DQS_MASK           0x00000400
 687 #define SDRAM_MEMODE_DQS_DISABLE        0x00000400
 688 #define SDRAM_MEMODE_DQS_ENABLE         0x00000000
 689
 690 /*-----------------------------------------------------------------------------+
 691 |  SDRAM Clock Timing Register
 692 +-----------------------------------------------------------------------------*/
 693 #define SDRAM_CLKTR_CLKP_MASK           0xC0000000
 694 #define SDRAM_CLKTR_CLKP_0_DEG          0x00000000
 695 #define SDRAM_CLKTR_CLKP_180_DEG_ADV    0x80000000
 696 #define SDRAM_CLKTR_CLKP_90_DEG_ADV     0x40000000
 697 #define SDRAM_CLKTR_CLKP_270_DEG_ADV    0xC0000000
 698
 699 /*-----------------------------------------------------------------------------+
 700 |  SDRAM Write Timing Register
 701 +-----------------------------------------------------------------------------*/
 702 #define SDRAM_WRDTR_LLWP_MASK           0x10000000
 703 #define SDRAM_WRDTR_LLWP_DIS            0x10000000
 704 #define SDRAM_WRDTR_LLWP_1_CYC          0x00000000
 705 #define SDRAM_WRDTR_WTR_MASK            0x0E000000
 706 #define SDRAM_WRDTR_WTR_0_DEG           0x06000000
 707 #define SDRAM_WRDTR_WTR_90_DEG_ADV      0x04000000
 708 #define SDRAM_WRDTR_WTR_180_DEG_ADV     0x02000000
 709 #define SDRAM_WRDTR_WTR_270_DEG_ADV     0x00000000
 710
 711 /*-----------------------------------------------------------------------------+
 712 |  SDRAM SDTR1 Options
 713 +-----------------------------------------------------------------------------*/
 714 #define SDRAM_SDTR1_LDOF_MASK           0x80000000
 715 #define SDRAM_SDTR1_LDOF_1_CLK          0x00000000
 716 #define SDRAM_SDTR1_LDOF_2_CLK          0x80000000
 717 #define SDRAM_SDTR1_RTW_MASK            0x00F00000
 718 #define SDRAM_SDTR1_RTW_2_CLK           0x00200000
 719 #define SDRAM_SDTR1_RTW_3_CLK           0x00300000
 720 #define SDRAM_SDTR1_WTWO_MASK           0x000F0000
 721 #define SDRAM_SDTR1_WTWO_0_CLK          0x00000000
 722 #define SDRAM_SDTR1_WTWO_1_CLK          0x00010000
 723 #define SDRAM_SDTR1_RTRO_MASK           0x0000F000
 724 #define SDRAM_SDTR1_RTRO_1_CLK          0x00001000
 725 #define SDRAM_SDTR1_RTRO_2_CLK          0x00002000
 726
 727 /*-----------------------------------------------------------------------------+
 728 |  SDRAM SDTR2 Options
 729 +-----------------------------------------------------------------------------*/
 730 #define SDRAM_SDTR2_RCD_MASK            0xF0000000
 731 #define SDRAM_SDTR2_RCD_1_CLK           0x10000000
 732 #define SDRAM_SDTR2_RCD_2_CLK           0x20000000
 733 #define SDRAM_SDTR2_RCD_3_CLK           0x30000000
 734 #define SDRAM_SDTR2_RCD_4_CLK           0x40000000
 735 #define SDRAM_SDTR2_RCD_5_CLK           0x50000000
 736 #define SDRAM_SDTR2_WTR_MASK            0x0F000000
 737 #define SDRAM_SDTR2_WTR_1_CLK           0x01000000
 738 #define SDRAM_SDTR2_WTR_2_CLK           0x02000000
 739 #define SDRAM_SDTR2_WTR_3_CLK           0x03000000
 740 #define SDRAM_SDTR2_WTR_4_CLK           0x04000000
 741 #define SDRAM_SDTR3_WTR_ENCODE(n)       ((((unsigned long)(n))&0xF)<<24)
 742 #define SDRAM_SDTR2_XSNR_MASK           0x00FF0000
 743 #define SDRAM_SDTR2_XSNR_8_CLK          0x00080000
 744 #define SDRAM_SDTR2_XSNR_16_CLK         0x00100000
 745 #define SDRAM_SDTR2_XSNR_32_CLK         0x00200000
 746 #define SDRAM_SDTR2_XSNR_64_CLK         0x00400000
 747 #define SDRAM_SDTR2_WPC_MASK            0x0000F000
 748 #define SDRAM_SDTR2_WPC_2_CLK           0x00002000
 749 #define SDRAM_SDTR2_WPC_3_CLK           0x00003000
 750 #define SDRAM_SDTR2_WPC_4_CLK           0x00004000
 751 #define SDRAM_SDTR2_WPC_5_CLK           0x00005000
 752 #define SDRAM_SDTR2_WPC_6_CLK           0x00006000
 753 #define SDRAM_SDTR3_WPC_ENCODE(n)       ((((unsigned long)(n))&0xF)<<12)
 754 #define SDRAM_SDTR2_RPC_MASK            0x00000F00
 755 #define SDRAM_SDTR2_RPC_2_CLK           0x00000200
 756 #define SDRAM_SDTR2_RPC_3_CLK           0x00000300
 757 #define SDRAM_SDTR2_RPC_4_CLK           0x00000400
 758 #define SDRAM_SDTR2_RP_MASK             0x000000F0
 759 #define SDRAM_SDTR2_RP_3_CLK            0x00000030
 760 #define SDRAM_SDTR2_RP_4_CLK            0x00000040
 761 #define SDRAM_SDTR2_RP_5_CLK            0x00000050
 762 #define SDRAM_SDTR2_RP_6_CLK            0x00000060
 763 #define SDRAM_SDTR2_RP_7_CLK            0x00000070
 764 #define SDRAM_SDTR2_RRD_MASK            0x0000000F
 765 #define SDRAM_SDTR2_RRD_2_CLK           0x00000002
 766 #define SDRAM_SDTR2_RRD_3_CLK           0x00000003
 767
 768 /*-----------------------------------------------------------------------------+
 769 |  SDRAM SDTR3 Options
 770 +-----------------------------------------------------------------------------*/
 771 #define SDRAM_SDTR3_RAS_MASK            0x1F000000
 772 #define SDRAM_SDTR3_RAS_ENCODE(n)       ((((unsigned long)(n))&0x1F)<<24)
 773 #define SDRAM_SDTR3_RC_MASK             0x001F0000
 774 #define SDRAM_SDTR3_RC_ENCODE(n)        ((((unsigned long)(n))&0x1F)<<16)
 775 #define SDRAM_SDTR3_XCS_MASK            0x00001F00
 776 #define SDRAM_SDTR3_XCS                 0x00000D00
 777 #define SDRAM_SDTR3_RFC_MASK            0x0000003F
 778 #define SDRAM_SDTR3_RFC_ENCODE(n)       ((((unsigned long)(n))&0x3F)<<0)
 779
 780 /*-----------------------------------------------------------------------------+
 781 |  Memory Bank 0-1 configuration
 782 +-----------------------------------------------------------------------------*/
 783 #define SDRAM_BXCF_M_AM_MASK            0x00000F00      /* Addressing mode      */
 784 #define SDRAM_BXCF_M_AM_0               0x00000000      /*   Mode 0             */
 785 #define SDRAM_BXCF_M_AM_1               0x00000100      /*   Mode 1             */
 786 #define SDRAM_BXCF_M_AM_2               0x00000200      /*   Mode 2             */
 787 #define SDRAM_BXCF_M_AM_3               0x00000300      /*   Mode 3             */
 788 #define SDRAM_BXCF_M_AM_4               0x00000400      /*   Mode 4             */
 789 #define SDRAM_BXCF_M_AM_5               0x00000500      /*   Mode 5             */
 790 #define SDRAM_BXCF_M_AM_6               0x00000600      /*   Mode 6             */
 791 #define SDRAM_BXCF_M_AM_7               0x00000700      /*   Mode 7             */
 792 #define SDRAM_BXCF_M_AM_8               0x00000800      /*   Mode 8             */
 793 #define SDRAM_BXCF_M_AM_9               0x00000900      /*   Mode 9             */
 794 #define SDRAM_BXCF_M_BE_MASK            0x00000001      /* Memory Bank Enable   */
 795 #define SDRAM_BXCF_M_BE_DISABLE         0x00000000      /* Memory Bank Enable   */
 796 #define SDRAM_BXCF_M_BE_ENABLE          0x00000001      /* Memory Bank Enable   */
 797
 798 #define SDRAM_RTSR_TRK1SM_MASK          0xC0000000      /* Tracking State Mach 1*/
 799 #define SDRAM_RTSR_TRK1SM_ATBASE        0x00000000      /* atbase state         */
 800 #define SDRAM_RTSR_TRK1SM_MISSED        0x40000000      /* missed state         */
 801 #define SDRAM_RTSR_TRK1SM_ATPLS1        0x80000000      /* atpls1 state         */
 802 #define SDRAM_RTSR_TRK1SM_RESET         0xC0000000      /* reset  state         */
 803
 804 #define SDR0_MFR_FIXD                   0x10000000      /* Workaround for PCI/DMA */
 805 #endif /* CONFIG_440SPE */
 806
 807 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 808 /*-----------------------------------------------------------------------------
 809  | SDRAM Controller
 810  +----------------------------------------------------------------------------*/
 811 #define DDR0_00                         0x00
 812 #define DDR0_00_INT_ACK_MASK              0x7F000000    /* Write only */
 813 #define DDR0_00_INT_ACK_ALL               0x7F000000
 814 #define DDR0_00_INT_ACK_ENCODE(n)           ((((unsigned long)(n))&0x7F)<<24)
 815 #define DDR0_00_INT_ACK_DECODE(n)           ((((unsigned long)(n))>>24)&0x7F)
 816 /* Status */
 817 #define DDR0_00_INT_STATUS_MASK           0x00FF0000    /* Read only */
 818 /* Bit0. A single access outside the defined PHYSICAL memory space detected. */
 819 #define DDR0_00_INT_STATUS_BIT0           0x00010000
 820 /* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
 821 #define DDR0_00_INT_STATUS_BIT1           0x00020000
 822 /* Bit2. Single correctable ECC event detected */
 823 #define DDR0_00_INT_STATUS_BIT2           0x00040000
 824 /* Bit3. Multiple correctable ECC events detected. */
 825 #define DDR0_00_INT_STATUS_BIT3           0x00080000
 826 /* Bit4. Single uncorrectable ECC event detected. */
 827 #define DDR0_00_INT_STATUS_BIT4           0x00100000
 828 /* Bit5. Multiple uncorrectable ECC events detected. */
 829 #define DDR0_00_INT_STATUS_BIT5           0x00200000
 830 /* Bit6. DRAM initialization complete. */
 831 #define DDR0_00_INT_STATUS_BIT6           0x00400000
 832 /* Bit7. Logical OR of all lower bits. */
 833 #define DDR0_00_INT_STATUS_BIT7           0x00800000
 834
 835 #define DDR0_00_INT_STATUS_ENCODE(n)        ((((unsigned long)(n))&0xFF)<<16)
 836 #define DDR0_00_INT_STATUS_DECODE(n)        ((((unsigned long)(n))>>16)&0xFF)
 837 #define DDR0_00_DLL_INCREMENT_MASK        0x00007F00
 838 #define DDR0_00_DLL_INCREMENT_ENCODE(n)     ((((unsigned long)(n))&0x7F)<<8)
 839 #define DDR0_00_DLL_INCREMENT_DECODE(n)     ((((unsigned long)(n))>>8)&0x7F)
 840 #define DDR0_00_DLL_START_POINT_MASK      0x0000007F
 841 #define DDR0_00_DLL_START_POINT_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
 842 #define DDR0_00_DLL_START_POINT_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
 843
 844 #define DDR0_01                         0x01
 845 #define DDR0_01_PLB0_DB_CS_LOWER_MASK     0x1F000000
 846 #define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n)  ((((unsigned long)(n))&0x1F)<<24)
 847 #define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n)  ((((unsigned long)(n))>>24)&0x1F)
 848 #define DDR0_01_PLB0_DB_CS_UPPER_MASK     0x001F0000
 849 #define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n)  ((((unsigned long)(n))&0x1F)<<16)
 850 #define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n)  ((((unsigned long)(n))>>16)&0x1F)
 851 #define DDR0_01_OUT_OF_RANGE_TYPE_MASK    0x00000700    /* Read only */
 852 #define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n)               ((((unsigned long)(n))&0x7)<<8)
 853 #define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n)               ((((unsigned long)(n))>>8)&0x7)
 854 #define DDR0_01_INT_MASK_MASK             0x000000FF
 855 #define DDR0_01_INT_MASK_ENCODE(n)          ((((unsigned long)(n))&0xFF)<<0)
 856 #define DDR0_01_INT_MASK_DECODE(n)          ((((unsigned long)(n))>>0)&0xFF)
 857 #define DDR0_01_INT_MASK_ALL_ON           0x000000FF
 858 #define DDR0_01_INT_MASK_ALL_OFF          0x00000000
 859
 860 #define DDR0_02                         0x02
 861 #define DDR0_02_MAX_CS_REG_MASK           0x02000000    /* Read only */
 862 #define DDR0_02_MAX_CS_REG_ENCODE(n)        ((((unsigned long)(n))&0x2)<<24)
 863 #define DDR0_02_MAX_CS_REG_DECODE(n)        ((((unsigned long)(n))>>24)&0x2)
 864 #define DDR0_02_MAX_COL_REG_MASK          0x000F0000    /* Read only */
 865 #define DDR0_02_MAX_COL_REG_ENCODE(n)       ((((unsigned long)(n))&0xF)<<16)
 866 #define DDR0_02_MAX_COL_REG_DECODE(n)       ((((unsigned long)(n))>>16)&0xF)
 867 #define DDR0_02_MAX_ROW_REG_MASK          0x00000F00    /* Read only */
 868 #define DDR0_02_MAX_ROW_REG_ENCODE(n)       ((((unsigned long)(n))&0xF)<<8)
 869 #define DDR0_02_MAX_ROW_REG_DECODE(n)       ((((unsigned long)(n))>>8)&0xF)
 870 #define DDR0_02_START_MASK                0x00000001
 871 #define DDR0_02_START_ENCODE(n)             ((((unsigned long)(n))&0x1)<<0)
 872 #define DDR0_02_START_DECODE(n)             ((((unsigned long)(n))>>0)&0x1)
 873 #define DDR0_02_START_OFF                 0x00000000
 874 #define DDR0_02_START_ON                  0x00000001
 875
 876 #define DDR0_03                         0x03
 877 #define DDR0_03_BSTLEN_MASK               0x07000000
 878 #define DDR0_03_BSTLEN_ENCODE(n)            ((((unsigned long)(n))&0x7)<<24)
 879 #define DDR0_03_BSTLEN_DECODE(n)            ((((unsigned long)(n))>>24)&0x7)
 880 #define DDR0_03_CASLAT_MASK               0x00070000
 881 #define DDR0_03_CASLAT_ENCODE(n)            ((((unsigned long)(n))&0x7)<<16)
 882 #define DDR0_03_CASLAT_DECODE(n)            ((((unsigned long)(n))>>16)&0x7)
 883 #define DDR0_03_CASLAT_LIN_MASK           0x00000F00
 884 #define DDR0_03_CASLAT_LIN_ENCODE(n)        ((((unsigned long)(n))&0xF)<<8)
 885 #define DDR0_03_CASLAT_LIN_DECODE(n)        ((((unsigned long)(n))>>8)&0xF)
 886 #define DDR0_03_INITAREF_MASK             0x0000000F
 887 #define DDR0_03_INITAREF_ENCODE(n)          ((((unsigned long)(n))&0xF)<<0)
 888 #define DDR0_03_INITAREF_DECODE(n)          ((((unsigned long)(n))>>0)&0xF)
 889
 890 #define DDR0_04                         0x04
 891 #define DDR0_04_TRC_MASK                  0x1F000000
 892 #define DDR0_04_TRC_ENCODE(n)               ((((unsigned long)(n))&0x1F)<<24)
 893 #define DDR0_04_TRC_DECODE(n)               ((((unsigned long)(n))>>24)&0x1F)
 894 #define DDR0_04_TRRD_MASK                 0x00070000
 895 #define DDR0_04_TRRD_ENCODE(n)              ((((unsigned long)(n))&0x7)<<16)
 896 #define DDR0_04_TRRD_DECODE(n)              ((((unsigned long)(n))>>16)&0x7)
 897 #define DDR0_04_TRTP_MASK                 0x00000700
 898 #define DDR0_04_TRTP_ENCODE(n)              ((((unsigned long)(n))&0x7)<<8)
 899 #define DDR0_04_TRTP_DECODE(n)              ((((unsigned long)(n))>>8)&0x7)
 900
 901 #define DDR0_05                         0x05
 902 #define DDR0_05_TMRD_MASK                 0x1F000000
 903 #define DDR0_05_TMRD_ENCODE(n)              ((((unsigned long)(n))&0x1F)<<24)
 904 #define DDR0_05_TMRD_DECODE(n)              ((((unsigned long)(n))>>24)&0x1F)
 905 #define DDR0_05_TEMRS_MASK                0x00070000
 906 #define DDR0_05_TEMRS_ENCODE(n)             ((((unsigned long)(n))&0x7)<<16)
 907 #define DDR0_05_TEMRS_DECODE(n)             ((((unsigned long)(n))>>16)&0x7)
 908 #define DDR0_05_TRP_MASK                  0x00000F00
 909 #define DDR0_05_TRP_ENCODE(n)               ((((unsigned long)(n))&0xF)<<8)
 910 #define DDR0_05_TRP_DECODE(n)               ((((unsigned long)(n))>>8)&0xF)
 911 #define DDR0_05_TRAS_MIN_MASK             0x000000FF
 912 #define DDR0_05_TRAS_MIN_ENCODE(n)          ((((unsigned long)(n))&0xFF)<<0)
 913 #define DDR0_05_TRAS_MIN_DECODE(n)          ((((unsigned long)(n))>>0)&0xFF)
 914
 915 #define DDR0_06                         0x06
 916 #define DDR0_06_WRITEINTERP_MASK          0x01000000
 917 #define DDR0_06_WRITEINTERP_ENCODE(n)       ((((unsigned long)(n))&0x1)<<24)
 918 #define DDR0_06_WRITEINTERP_DECODE(n)       ((((unsigned long)(n))>>24)&0x1)
 919 #define DDR0_06_TWTR_MASK                 0x00070000
 920 #define DDR0_06_TWTR_ENCODE(n)              ((((unsigned long)(n))&0x7)<<16)
 921 #define DDR0_06_TWTR_DECODE(n)              ((((unsigned long)(n))>>16)&0x7)
 922 #define DDR0_06_TDLL_MASK                 0x0000FF00
 923 #define DDR0_06_TDLL_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<8)
 924 #define DDR0_06_TDLL_DECODE(n)              ((((unsigned long)(n))>>8)&0xFF)
 925 #define DDR0_06_TRFC_MASK                 0x0000007F
 926 #define DDR0_06_TRFC_ENCODE(n)              ((((unsigned long)(n))&0x7F)<<0)
 927 #define DDR0_06_TRFC_DECODE(n)              ((((unsigned long)(n))>>0)&0x7F)
 928
 929 #define DDR0_07                         0x07
 930 #define DDR0_07_NO_CMD_INIT_MASK          0x01000000
 931 #define DDR0_07_NO_CMD_INIT_ENCODE(n)       ((((unsigned long)(n))&0x1)<<24)
 932 #define DDR0_07_NO_CMD_INIT_DECODE(n)       ((((unsigned long)(n))>>24)&0x1)
 933 #define DDR0_07_TFAW_MASK                 0x001F0000
 934 #define DDR0_07_TFAW_ENCODE(n)              ((((unsigned long)(n))&0x1F)<<16)
 935 #define DDR0_07_TFAW_DECODE(n)              ((((unsigned long)(n))>>16)&0x1F)
 936 #define DDR0_07_AUTO_REFRESH_MODE_MASK    0x00000100
 937 #define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
 938 #define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
 939 #define DDR0_07_AREFRESH_MASK             0x00000001
 940 #define DDR0_07_AREFRESH_ENCODE(n)          ((((unsigned long)(n))&0x1)<<0)
 941 #define DDR0_07_AREFRESH_DECODE(n)          ((((unsigned long)(n))>>0)&0x1)
 942
 943 #define DDR0_08                         0x08
 944 #define DDR0_08_WRLAT_MASK                0x07000000
 945 #define DDR0_08_WRLAT_ENCODE(n)             ((((unsigned long)(n))&0x7)<<24)
 946 #define DDR0_08_WRLAT_DECODE(n)             ((((unsigned long)(n))>>24)&0x7)
 947 #define DDR0_08_TCPD_MASK                 0x00FF0000
 948 #define DDR0_08_TCPD_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<16)
 949 #define DDR0_08_TCPD_DECODE(n)              ((((unsigned long)(n))>>16)&0xFF)
 950 #define DDR0_08_DQS_N_EN_MASK             0x00000100
 951 #define DDR0_08_DQS_N_EN_ENCODE(n)          ((((unsigned long)(n))&0x1)<<8)
 952 #define DDR0_08_DQS_N_EN_DECODE(n)          ((((unsigned long)(n))>>8)&0x1)
 953 #define DDR0_08_DDRII_SDRAM_MODE_MASK     0x00000001
 954 #define DDR0_08_DDRII_ENCODE(n)             ((((unsigned long)(n))&0x1)<<0)
 955 #define DDR0_08_DDRII_DECODE(n)             ((((unsigned long)(n))>>0)&0x1)
 956
 957 #define DDR0_09                         0x09
 958 #define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK  0x1F000000
 959 #define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
 960 #define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
 961 #define DDR0_09_RTT_0_MASK                0x00030000
 962 #define DDR0_09_RTT_0_ENCODE(n)             ((((unsigned long)(n))&0x3)<<16)
 963 #define DDR0_09_RTT_0_DECODE(n)             ((((unsigned long)(n))>>16)&0x3)
 964 #define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK  0x00007F00
 965 #define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
 966 #define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
 967 #define DDR0_09_WR_DQS_SHIFT_MASK         0x0000007F
 968 #define DDR0_09_WR_DQS_SHIFT_ENCODE(n)      ((((unsigned long)(n))&0x7F)<<0)
 969 #define DDR0_09_WR_DQS_SHIFT_DECODE(n)      ((((unsigned long)(n))>>0)&0x7F)
 970
 971 #define DDR0_10                         0x0A
 972 #define DDR0_10_WRITE_MODEREG_MASK        0x00010000    /* Write only */
 973 #define DDR0_10_WRITE_MODEREG_ENCODE(n)     ((((unsigned long)(n))&0x1)<<16)
 974 #define DDR0_10_WRITE_MODEREG_DECODE(n)     ((((unsigned long)(n))>>16)&0x1)
 975 #define DDR0_10_CS_MAP_MASK               0x00000300
 976 #define DDR0_10_CS_MAP_NO_MEM             0x00000000
 977 #define DDR0_10_CS_MAP_RANK0_INSTALLED    0x00000100
 978 #define DDR0_10_CS_MAP_RANK1_INSTALLED    0x00000200
 979 #define DDR0_10_CS_MAP_ENCODE(n)            ((((unsigned long)(n))&0x3)<<8)
 980 #define DDR0_10_CS_MAP_DECODE(n)            ((((unsigned long)(n))>>8)&0x3)
 981 #define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK  0x0000001F
 982 #define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0)
 983 #define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F)
 984
 985 #define DDR0_11                         0x0B
 986 #define DDR0_11_SREFRESH_MASK             0x01000000
 987 #define DDR0_11_SREFRESH_ENCODE(n)          ((((unsigned long)(n))&0x1)<<24)
 988 #define DDR0_11_SREFRESH_DECODE(n)          ((((unsigned long)(n))>>24)&0x1F)
 989 #define DDR0_11_TXSNR_MASK                0x00FF0000
 990 #define DDR0_11_TXSNR_ENCODE(n)             ((((unsigned long)(n))&0xFF)<<16)
 991 #define DDR0_11_TXSNR_DECODE(n)             ((((unsigned long)(n))>>16)&0xFF)
 992 #define DDR0_11_TXSR_MASK                 0x0000FF00
 993 #define DDR0_11_TXSR_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<8)
 994 #define DDR0_11_TXSR_DECODE(n)              ((((unsigned long)(n))>>8)&0xFF)
 995
 996 #define DDR0_12                         0x0C
 997 #define DDR0_12_TCKE_MASK                 0x0000007
 998 #define DDR0_12_TCKE_ENCODE(n)              ((((unsigned long)(n))&0x7)<<0)
 999 #define DDR0_12_TCKE_DECODE(n)              ((((unsigned long)(n))>>0)&0x7)
1000
1001 #define DDR0_14                         0x0E
1002 #define DDR0_14_DLL_BYPASS_MODE_MASK      0x01000000
1003 #define DDR0_14_DLL_BYPASS_MODE_ENCODE(n)   ((((unsigned long)(n))&0x1)<<24)
1004 #define DDR0_14_DLL_BYPASS_MODE_DECODE(n)   ((((unsigned long)(n))>>24)&0x1)
1005 #define DDR0_14_REDUC_MASK                0x00010000
1006 #define DDR0_14_REDUC_64BITS              0x00000000
1007 #define DDR0_14_REDUC_32BITS              0x00010000
1008 #define DDR0_14_REDUC_ENCODE(n)             ((((unsigned long)(n))&0x1)<<16)
1009 #define DDR0_14_REDUC_DECODE(n)             ((((unsigned long)(n))>>16)&0x1)
1010 #define DDR0_14_REG_DIMM_ENABLE_MASK      0x00000100
1011 #define DDR0_14_REG_DIMM_ENABLE_ENCODE(n)   ((((unsigned long)(n))&0x1)<<8)
1012 #define DDR0_14_REG_DIMM_ENABLE_DECODE(n)   ((((unsigned long)(n))>>8)&0x1)
1013
1014 #define DDR0_17                         0x11
1015 #define DDR0_17_DLL_DQS_DELAY_0_MASK      0x7F000000
1016 #define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
1017 #define DDR0_17_DLL_DQS_DELAY_0_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
1018 #define DDR0_17_DLLLOCKREG_MASK           0x00010000    /* Read only */
1019 #define DDR0_17_DLLLOCKREG_LOCKED         0x00010000
1020 #define DDR0_17_DLLLOCKREG_UNLOCKED       0x00000000
1021 #define DDR0_17_DLLLOCKREG_ENCODE(n)        ((((unsigned long)(n))&0x1)<<16)
1022 #define DDR0_17_DLLLOCKREG_DECODE(n)        ((((unsigned long)(n))>>16)&0x1)
1023 #define DDR0_17_DLL_LOCK_MASK             0x00007F00    /* Read only */
1024 #define DDR0_17_DLL_LOCK_ENCODE(n)          ((((unsigned long)(n))&0x7F)<<8)
1025 #define DDR0_17_DLL_LOCK_DECODE(n)          ((((unsigned long)(n))>>8)&0x7F)
1026
1027 #define DDR0_18                         0x12
1028 #define DDR0_18_DLL_DQS_DELAY_X_MASK      0x7F7F7F7F
1029 #define DDR0_18_DLL_DQS_DELAY_4_MASK      0x7F000000
1030 #define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
1031 #define DDR0_18_DLL_DQS_DELAY_4_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
1032 #define DDR0_18_DLL_DQS_DELAY_3_MASK      0x007F0000
1033 #define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
1034 #define DDR0_18_DLL_DQS_DELAY_3_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
1035 #define DDR0_18_DLL_DQS_DELAY_2_MASK      0x00007F00
1036 #define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
1037 #define DDR0_18_DLL_DQS_DELAY_2_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
1038 #define DDR0_18_DLL_DQS_DELAY_1_MASK      0x0000007F
1039 #define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
1040 #define DDR0_18_DLL_DQS_DELAY_1_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
1041
1042 #define DDR0_19                         0x13
1043 #define DDR0_19_DLL_DQS_DELAY_X_MASK      0x7F7F7F7F
1044 #define DDR0_19_DLL_DQS_DELAY_8_MASK      0x7F000000
1045 #define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
1046 #define DDR0_19_DLL_DQS_DELAY_8_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
1047 #define DDR0_19_DLL_DQS_DELAY_7_MASK      0x007F0000
1048 #define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
1049 #define DDR0_19_DLL_DQS_DELAY_7_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
1050 #define DDR0_19_DLL_DQS_DELAY_6_MASK      0x00007F00
1051 #define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
1052 #define DDR0_19_DLL_DQS_DELAY_6_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
1053 #define DDR0_19_DLL_DQS_DELAY_5_MASK      0x0000007F
1054 #define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
1055 #define DDR0_19_DLL_DQS_DELAY_5_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
1056
1057 #define DDR0_20                         0x14
1058 #define DDR0_20_DLL_DQS_BYPASS_3_MASK      0x7F000000
1059 #define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
1060 #define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
1061 #define DDR0_20_DLL_DQS_BYPASS_2_MASK      0x007F0000
1062 #define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
1063 #define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
1064 #define DDR0_20_DLL_DQS_BYPASS_1_MASK      0x00007F00
1065 #define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
1066 #define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
1067 #define DDR0_20_DLL_DQS_BYPASS_0_MASK      0x0000007F
1068 #define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
1069 #define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
1070
1071 #define DDR0_21                         0x15
1072 #define DDR0_21_DLL_DQS_BYPASS_7_MASK      0x7F000000
1073 #define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
1074 #define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
1075 #define DDR0_21_DLL_DQS_BYPASS_6_MASK      0x007F0000
1076 #define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
1077 #define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
1078 #define DDR0_21_DLL_DQS_BYPASS_5_MASK      0x00007F00
1079 #define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
1080 #define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
1081 #define DDR0_21_DLL_DQS_BYPASS_4_MASK      0x0000007F
1082 #define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
1083 #define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
1084
1085 #define DDR0_22                         0x16
1086 #define DDR0_22_CTRL_RAW_MASK             0x03000000
1087 #define DDR0_22_CTRL_RAW_ECC_DISABLE      0x00000000    /* ECC not being used */
1088 #define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY   0x01000000    /* ECC checking is on, but no attempts to correct */
1089 #define DDR0_22_CTRL_RAW_NO_ECC_RAM       0x02000000    /* No ECC RAM storage available */
1090 #define DDR0_22_CTRL_RAW_ECC_ENABLE       0x03000000    /* ECC checking and correcting on */
1091 #define DDR0_22_CTRL_RAW_ENCODE(n)          ((((unsigned long)(n))&0x3)<<24)
1092 #define DDR0_22_CTRL_RAW_DECODE(n)          ((((unsigned long)(n))>>24)&0x3)
1093 #define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
1094 #define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
1095 #define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
1096 #define DDR0_22_DQS_OUT_SHIFT_MASK        0x00007F00
1097 #define DDR0_22_DQS_OUT_SHIFT_ENCODE(n)     ((((unsigned long)(n))&0x7F)<<8)
1098 #define DDR0_22_DQS_OUT_SHIFT_DECODE(n)     ((((unsigned long)(n))>>8)&0x7F)
1099 #define DDR0_22_DLL_DQS_BYPASS_8_MASK     0x0000007F
1100 #define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n)  ((((unsigned long)(n))&0x7F)<<0)
1101 #define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n)  ((((unsigned long)(n))>>0)&0x7F)
1102
1103 #define DDR0_23                         0x17
1104 #define DDR0_23_ODT_RD_MAP_CS0_MASK       0x03000000
1105 #define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n)   ((((unsigned long)(n))&0x3)<<24)
1106 #define DDR0_23_ODT_RD_MAP_CS0_DECODE(n)   ((((unsigned long)(n))>>24)&0x3)
1107 #define DDR0_23_ECC_C_SYND_MASK           0x00FF0000    /* Read only */
1108 #define DDR0_23_ECC_C_SYND_ENCODE(n)        ((((unsigned long)(n))&0xFF)<<16)
1109 #define DDR0_23_ECC_C_SYND_DECODE(n)        ((((unsigned long)(n))>>16)&0xFF)
1110 #define DDR0_23_ECC_U_SYND_MASK           0x0000FF00    /* Read only */
1111 #define DDR0_23_ECC_U_SYND_ENCODE(n)        ((((unsigned long)(n))&0xFF)<<8)
1112 #define DDR0_23_ECC_U_SYND_DECODE(n)        ((((unsigned long)(n))>>8)&0xFF)
1113 #define DDR0_23_FWC_MASK                  0x00000001    /* Write only */
1114 #define DDR0_23_FWC_ENCODE(n)               ((((unsigned long)(n))&0x1)<<0)
1115 #define DDR0_23_FWC_DECODE(n)               ((((unsigned long)(n))>>0)&0x1)
1116
1117 #define DDR0_24                         0x18
1118 #define DDR0_24_RTT_PAD_TERMINATION_MASK  0x03000000
1119 #define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
1120 #define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
1121 #define DDR0_24_ODT_WR_MAP_CS1_MASK       0x00030000
1122 #define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n)    ((((unsigned long)(n))&0x3)<<16)
1123 #define DDR0_24_ODT_WR_MAP_CS1_DECODE(n)    ((((unsigned long)(n))>>16)&0x3)
1124 #define DDR0_24_ODT_RD_MAP_CS1_MASK       0x00000300
1125 #define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n)    ((((unsigned long)(n))&0x3)<<8)
1126 #define DDR0_24_ODT_RD_MAP_CS1_DECODE(n)    ((((unsigned long)(n))>>8)&0x3)
1127 #define DDR0_24_ODT_WR_MAP_CS0_MASK       0x00000003
1128 #define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n)    ((((unsigned long)(n))&0x3)<<0)
1129 #define DDR0_24_ODT_WR_MAP_CS0_DECODE(n)    ((((unsigned long)(n))>>0)&0x3)
1130
1131 #define DDR0_25                         0x19
1132 #define DDR0_25_VERSION_MASK              0xFFFF0000    /* Read only */
1133 #define DDR0_25_VERSION_ENCODE(n)           ((((unsigned long)(n))&0xFFFF)<<16)
1134 #define DDR0_25_VERSION_DECODE(n)           ((((unsigned long)(n))>>16)&0xFFFF)
1135 #define DDR0_25_OUT_OF_RANGE_LENGTH_MASK  0x000003FF    /* Read only */
1136 #define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
1137 #define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
1138
1139 #define DDR0_26                         0x1A
1140 #define DDR0_26_TRAS_MAX_MASK             0xFFFF0000
1141 #define DDR0_26_TRAS_MAX_ENCODE(n)          ((((unsigned long)(n))&0xFFFF)<<16)
1142 #define DDR0_26_TRAS_MAX_DECODE(n)          ((((unsigned long)(n))>>16)&0xFFFF)
1143 #define DDR0_26_TREF_MASK                 0x00003FFF
1144 #define DDR0_26_TREF_ENCODE(n)              ((((unsigned long)(n))&0x3FFF)<<0)
1145 #define DDR0_26_TREF_DECODE(n)              ((((unsigned long)(n))>>0)&0x3FFF)
1146
1147 #define DDR0_27                         0x1B
1148 #define DDR0_27_EMRS_DATA_MASK            0x3FFF0000
1149 #define DDR0_27_EMRS_DATA_ENCODE(n)         ((((unsigned long)(n))&0x3FFF)<<16)
1150 #define DDR0_27_EMRS_DATA_DECODE(n)         ((((unsigned long)(n))>>16)&0x3FFF)
1151 #define DDR0_27_TINIT_MASK                0x0000FFFF
1152 #define DDR0_27_TINIT_ENCODE(n)             ((((unsigned long)(n))&0xFFFF)<<0)
1153 #define DDR0_27_TINIT_DECODE(n)             ((((unsigned long)(n))>>0)&0xFFFF)
1154
1155 #define DDR0_28                         0x1C
1156 #define DDR0_28_EMRS3_DATA_MASK           0x3FFF0000
1157 #define DDR0_28_EMRS3_DATA_ENCODE(n)        ((((unsigned long)(n))&0x3FFF)<<16)
1158 #define DDR0_28_EMRS3_DATA_DECODE(n)        ((((unsigned long)(n))>>16)&0x3FFF)
1159 #define DDR0_28_EMRS2_DATA_MASK           0x00003FFF
1160 #define DDR0_28_EMRS2_DATA_ENCODE(n)        ((((unsigned long)(n))&0x3FFF)<<0)
1161 #define DDR0_28_EMRS2_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0x3FFF)
1162
1163 #define DDR0_31                         0x1F
1164 #define DDR0_31_XOR_CHECK_BITS_MASK       0x0000FFFF
1165 #define DDR0_31_XOR_CHECK_BITS_ENCODE(n)    ((((unsigned long)(n))&0xFFFF)<<0)
1166 #define DDR0_31_XOR_CHECK_BITS_DECODE(n)    ((((unsigned long)(n))>>0)&0xFFFF)
1167
1168 #define DDR0_32                         0x20
1169 #define DDR0_32_OUT_OF_RANGE_ADDR_MASK    0xFFFFFFFF    /* Read only */
1170 #define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
1171 #define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
1172
1173 #define DDR0_33                         0x21
1174 #define DDR0_33_OUT_OF_RANGE_ADDR_MASK    0x00000001    /* Read only */
1175 #define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
1176 #define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n)               ((((unsigned long)(n))>>0)&0x1)
1177
1178 #define DDR0_34                         0x22
1179 #define DDR0_34_ECC_U_ADDR_MASK           0xFFFFFFFF    /* Read only */
1180 #define DDR0_34_ECC_U_ADDR_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
1181 #define DDR0_34_ECC_U_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
1182
1183 #define DDR0_35                         0x23
1184 #define DDR0_35_ECC_U_ADDR_MASK           0x00000001    /* Read only */
1185 #define DDR0_35_ECC_U_ADDR_ENCODE(n)        ((((unsigned long)(n))&0x1)<<0)
1186 #define DDR0_35_ECC_U_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0x1)
1187
1188 #define DDR0_36                         0x24
1189 #define DDR0_36_ECC_U_DATA_MASK           0xFFFFFFFF    /* Read only */
1190 #define DDR0_36_ECC_U_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
1191 #define DDR0_36_ECC_U_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
1192
1193 #define DDR0_37                         0x25
1194 #define DDR0_37_ECC_U_DATA_MASK           0xFFFFFFFF    /* Read only */
1195 #define DDR0_37_ECC_U_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
1196 #define DDR0_37_ECC_U_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
1197
1198 #define DDR0_38                         0x26
1199 #define DDR0_38_ECC_C_ADDR_MASK           0xFFFFFFFF    /* Read only */
1200 #define DDR0_38_ECC_C_ADDR_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
1201 #define DDR0_38_ECC_C_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
1202
1203 #define DDR0_39                         0x27
1204 #define DDR0_39_ECC_C_ADDR_MASK           0x00000001    /* Read only */
1205 #define DDR0_39_ECC_C_ADDR_ENCODE(n)        ((((unsigned long)(n))&0x1)<<0)
1206 #define DDR0_39_ECC_C_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0x1)
1207
1208 #define DDR0_40                         0x28
1209 #define DDR0_40_ECC_C_DATA_MASK           0xFFFFFFFF    /* Read only */
1210 #define DDR0_40_ECC_C_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
1211 #define DDR0_40_ECC_C_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
1212
1213 #define DDR0_41                         0x29
1214 #define DDR0_41_ECC_C_DATA_MASK           0xFFFFFFFF    /* Read only */
1215 #define DDR0_41_ECC_C_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
1216 #define DDR0_41_ECC_C_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
1217
1218 #define DDR0_42                         0x2A
1219 #define DDR0_42_ADDR_PINS_MASK            0x07000000
1220 #define DDR0_42_ADDR_PINS_ENCODE(n)         ((((unsigned long)(n))&0x7)<<24)
1221 #define DDR0_42_ADDR_PINS_DECODE(n)         ((((unsigned long)(n))>>24)&0x7)
1222 #define DDR0_42_CASLAT_LIN_GATE_MASK      0x0000000F
1223 #define DDR0_42_CASLAT_LIN_GATE_ENCODE(n)   ((((unsigned long)(n))&0xF)<<0)
1224 #define DDR0_42_CASLAT_LIN_GATE_DECODE(n)   ((((unsigned long)(n))>>0)&0xF)
1225
1226 #define DDR0_43                         0x2B
1227 #define DDR0_43_TWR_MASK                  0x07000000
1228 #define DDR0_43_TWR_ENCODE(n)               ((((unsigned long)(n))&0x7)<<24)
1229 #define DDR0_43_TWR_DECODE(n)               ((((unsigned long)(n))>>24)&0x7)
1230 #define DDR0_43_APREBIT_MASK              0x000F0000
1231 #define DDR0_43_APREBIT_ENCODE(n)           ((((unsigned long)(n))&0xF)<<16)
1232 #define DDR0_43_APREBIT_DECODE(n)           ((((unsigned long)(n))>>16)&0xF)
1233 #define DDR0_43_COLUMN_SIZE_MASK          0x00000700
1234 #define DDR0_43_COLUMN_SIZE_ENCODE(n)       ((((unsigned long)(n))&0x7)<<8)
1235 #define DDR0_43_COLUMN_SIZE_DECODE(n)       ((((unsigned long)(n))>>8)&0x7)
1236 #define DDR0_43_EIGHT_BANK_MODE_MASK      0x00000001
1237 #define DDR0_43_EIGHT_BANK_MODE_8_BANKS     0x00000001
1238 #define DDR0_43_EIGHT_BANK_MODE_4_BANKS     0x00000000
1239 #define DDR0_43_EIGHT_BANK_MODE_ENCODE(n)   ((((unsigned long)(n))&0x1)<<0)
1240 #define DDR0_43_EIGHT_BANK_MODE_DECODE(n)   ((((unsigned long)(n))>>0)&0x1)
1241
1242 #define DDR0_44                         0x2C
1243 #define DDR0_44_TRCD_MASK                 0x000000FF
1244 #define DDR0_44_TRCD_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<0)
1245 #define DDR0_44_TRCD_DECODE(n)              ((((unsigned long)(n))>>0)&0xFF)
1246
1247 #endif /* CONFIG_440EPX */
1248
1249 /*-----------------------------------------------------------------------------
1250  | External Bus Controller
1251  +----------------------------------------------------------------------------*/
1252 /* values for ebccfga register - indirect addressing of these regs */
1253 #define pb0cr           0x00    /* periph bank 0 config reg             */
1254 #define pb1cr           0x01    /* periph bank 1 config reg             */
1255 #define pb2cr           0x02    /* periph bank 2 config reg             */
1256 #define pb3cr           0x03    /* periph bank 3 config reg             */
1257 #define pb4cr           0x04    /* periph bank 4 config reg             */
1258 #define pb5cr           0x05    /* periph bank 5 config reg             */
1259 #define pb6cr           0x06    /* periph bank 6 config reg             */
1260 #define pb7cr           0x07    /* periph bank 7 config reg             */
1261 #define pb0ap           0x10    /* periph bank 0 access parameters      */
1262 #define pb1ap           0x11    /* periph bank 1 access parameters      */
1263 #define pb2ap           0x12    /* periph bank 2 access parameters      */
1264 #define pb3ap           0x13    /* periph bank 3 access parameters      */
1265 #define pb4ap           0x14    /* periph bank 4 access parameters      */
1266 #define pb5ap           0x15    /* periph bank 5 access parameters      */
1267 #define pb6ap           0x16    /* periph bank 6 access parameters      */
1268 #define pb7ap           0x17    /* periph bank 7 access parameters      */
1269 #define pbear           0x20    /* periph bus error addr reg            */
1270 #define pbesr           0x21    /* periph bus error status reg          */
1271 #define xbcfg           0x23    /* external bus configuration reg       */
1272 #define EBC0_CFG        0x23    /* external bus configuration reg       */
1273 #define xbcid           0x24    /* external bus core id reg             */
1274
1275 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1276     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1277
1278 /* PLB4 to PLB3 Bridge OUT */
1279 #define P4P3_DCR_BASE           0x020
1280 #define p4p3_esr0_read          (P4P3_DCR_BASE+0x0)
1281 #define p4p3_esr0_write         (P4P3_DCR_BASE+0x1)
1282 #define p4p3_eadr               (P4P3_DCR_BASE+0x2)
1283 #define p4p3_euadr              (P4P3_DCR_BASE+0x3)
1284 #define p4p3_esr1_read          (P4P3_DCR_BASE+0x4)
1285 #define p4p3_esr1_write         (P4P3_DCR_BASE+0x5)
1286 #define p4p3_confg              (P4P3_DCR_BASE+0x6)
1287 #define p4p3_pic                (P4P3_DCR_BASE+0x7)
1288 #define p4p3_peir               (P4P3_DCR_BASE+0x8)
1289 #define p4p3_rev                (P4P3_DCR_BASE+0xA)
1290
1291 /* PLB3 to PLB4 Bridge IN */
1292 #define P3P4_DCR_BASE           0x030
1293 #define p3p4_esr0_read          (P3P4_DCR_BASE+0x0)
1294 #define p3p4_esr0_write         (P3P4_DCR_BASE+0x1)
1295 #define p3p4_eadr               (P3P4_DCR_BASE+0x2)
1296 #define p3p4_euadr              (P3P4_DCR_BASE+0x3)
1297 #define p3p4_esr1_read          (P3P4_DCR_BASE+0x4)
1298 #define p3p4_esr1_write         (P3P4_DCR_BASE+0x5)
1299 #define p3p4_confg              (P3P4_DCR_BASE+0x6)
1300 #define p3p4_pic                (P3P4_DCR_BASE+0x7)
1301 #define p3p4_peir               (P3P4_DCR_BASE+0x8)
1302 #define p3p4_rev                (P3P4_DCR_BASE+0xA)
1303
1304 /* PLB3 Arbiter */
1305 #define PLB3_DCR_BASE           0x070
1306 #define plb3_revid              (PLB3_DCR_BASE+0x2)
1307 #define plb3_besr               (PLB3_DCR_BASE+0x3)
1308 #define plb3_bear               (PLB3_DCR_BASE+0x6)
1309 #define plb3_acr                (PLB3_DCR_BASE+0x7)
1310
1311 /* PLB4 Arbiter - PowerPC440EP Pass1 */
1312 #define PLB4_DCR_BASE           0x080
1313 #define plb4_acr                (PLB4_DCR_BASE+0x1)
1314 #define plb4_revid              (PLB4_DCR_BASE+0x2)
1315 #define plb4_besr               (PLB4_DCR_BASE+0x4)
1316 #define plb4_bearl              (PLB4_DCR_BASE+0x6)
1317 #define plb4_bearh              (PLB4_DCR_BASE+0x7)
1318
1319 #define PLB4_ACR_WRP            (0x80000000 >> 7)
1320
1321 /* Nebula PLB4 Arbiter - PowerPC440EP */
1322 #define PLB_ARBITER_BASE   0x80
1323
1324 #define plb0_revid                (PLB_ARBITER_BASE+ 0x00)
1325 #define plb0_acr                  (PLB_ARBITER_BASE+ 0x01)
1326 #define   plb0_acr_ppm_mask             0xF0000000
1327 #define   plb0_acr_ppm_fixed            0x00000000
1328 #define   plb0_acr_ppm_fair             0xD0000000
1329 #define   plb0_acr_hbu_mask             0x08000000
1330 #define   plb0_acr_hbu_disabled         0x00000000
1331 #define   plb0_acr_hbu_enabled          0x08000000
1332 #define   plb0_acr_rdp_mask             0x06000000
1333 #define   plb0_acr_rdp_disabled         0x00000000
1334 #define   plb0_acr_rdp_2deep            0x02000000
1335 #define   plb0_acr_rdp_3deep            0x04000000
1336 #define   plb0_acr_rdp_4deep            0x06000000
1337 #define   plb0_acr_wrp_mask             0x01000000
1338 #define   plb0_acr_wrp_disabled         0x00000000
1339 #define   plb0_acr_wrp_2deep            0x01000000
1340
1341 #define plb0_besrl                (PLB_ARBITER_BASE+ 0x02)
1342 #define plb0_besrh                (PLB_ARBITER_BASE+ 0x03)
1343 #define plb0_bearl                (PLB_ARBITER_BASE+ 0x04)
1344 #define plb0_bearh                (PLB_ARBITER_BASE+ 0x05)
1345 #define plb0_ccr                  (PLB_ARBITER_BASE+ 0x08)
1346
1347 #define plb1_acr                  (PLB_ARBITER_BASE+ 0x09)
1348 #define   plb1_acr_ppm_mask             0xF0000000
1349 #define   plb1_acr_ppm_fixed            0x00000000
1350 #define   plb1_acr_ppm_fair             0xD0000000
1351 #define   plb1_acr_hbu_mask             0x08000000
1352 #define   plb1_acr_hbu_disabled         0x00000000
1353 #define   plb1_acr_hbu_enabled          0x08000000
1354 #define   plb1_acr_rdp_mask             0x06000000
1355 #define   plb1_acr_rdp_disabled         0x00000000
1356 #define   plb1_acr_rdp_2deep            0x02000000
1357 #define   plb1_acr_rdp_3deep            0x04000000
1358 #define   plb1_acr_rdp_4deep            0x06000000
1359 #define   plb1_acr_wrp_mask             0x01000000
1360 #define   plb1_acr_wrp_disabled         0x00000000
1361 #define   plb1_acr_wrp_2deep            0x01000000
1362
1363 #define plb1_besrl                (PLB_ARBITER_BASE+ 0x0A)
1364 #define plb1_besrh                (PLB_ARBITER_BASE+ 0x0B)
1365 #define plb1_bearl                (PLB_ARBITER_BASE+ 0x0C)
1366 #define plb1_bearh                (PLB_ARBITER_BASE+ 0x0D)
1367
1368 /* Pin Function Control Register 1 */
1369 #define SDR0_PFC1                    0x4101
1370 #define   SDR0_PFC1_U1ME_MASK         0x02000000    /* UART1 Mode Enable */
1371 #define   SDR0_PFC1_U1ME_DSR_DTR      0x00000000      /* UART1 in DSR/DTR Mode */
1372 #define   SDR0_PFC1_U1ME_CTS_RTS      0x02000000      /* UART1 in CTS/RTS Mode */
1373 #define   SDR0_PFC1_U0ME_MASK         0x00080000    /* UART0 Mode Enable */
1374 #define   SDR0_PFC1_U0ME_DSR_DTR      0x00000000      /* UART0 in DSR/DTR Mode */
1375 #define   SDR0_PFC1_U0ME_CTS_RTS      0x00080000      /* UART0 in CTS/RTS Mode */
1376 #define   SDR0_PFC1_U0IM_MASK         0x00040000    /* UART0 Interface Mode */
1377 #define   SDR0_PFC1_U0IM_8PINS        0x00000000      /* UART0 Interface Mode 8 pins */
1378 #define   SDR0_PFC1_U0IM_4PINS        0x00040000      /* UART0 Interface Mode 4 pins */
1379 #define   SDR0_PFC1_SIS_MASK          0x00020000    /* SCP or IIC1 Selection */
1380 #define   SDR0_PFC1_SIS_SCP_SEL       0x00000000      /* SCP Selected */
1381 #define   SDR0_PFC1_SIS_IIC1_SEL      0x00020000      /* IIC1 Selected */
1382 #define   SDR0_PFC1_UES_MASK          0x00010000    /* USB2D_RX_Active / EBC_Hold Req Selection */
1383 #define   SDR0_PFC1_UES_USB2D_SEL     0x00000000      /* USB2D_RX_Active Selected */
1384 #define   SDR0_PFC1_UES_EBCHR_SEL     0x00010000      /* EBC_Hold Req Selected */
1385 #define   SDR0_PFC1_DIS_MASK          0x00008000    /* DMA_Req(1) / UIC_IRQ(5) Selection */
1386 #define   SDR0_PFC1_DIS_DMAR_SEL      0x00000000      /* DMA_Req(1) Selected */
1387 #define   SDR0_PFC1_DIS_UICIRQ5_SEL   0x00008000      /* UIC_IRQ(5) Selected */
1388 #define   SDR0_PFC1_ERE_MASK          0x00004000    /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
1389 #define   SDR0_PFC1_ERE_EXTR_SEL      0x00000000      /* EBC Mast.Ext.Req.En. Selected */
1390 #define   SDR0_PFC1_ERE_GPIO0_27_SEL  0x00004000      /* GPIO0(27) Selected */
1391 #define   SDR0_PFC1_UPR_MASK          0x00002000    /* USB2 Device Packet Reject Selection */
1392 #define   SDR0_PFC1_UPR_DISABLE       0x00000000      /* USB2 Device Packet Reject Disable */
1393 #define   SDR0_PFC1_UPR_ENABLE        0x00002000      /* USB2 Device Packet Reject Enable */
1394
1395 #define   SDR0_PFC1_PLB_PME_MASK      0x00001000    /* PLB3/PLB4 Perf. Monitor En. Selection */
1396 #define   SDR0_PFC1_PLB_PME_PLB3_SEL  0x00000000      /* PLB3 Performance Monitor Enable */
1397 #define   SDR0_PFC1_PLB_PME_PLB4_SEL  0x00001000      /* PLB3 Performance Monitor Enable */
1398 #define   SDR0_PFC1_GFGGI_MASK        0x0000000F    /* GPT Frequency Generation Gated In */
1399
1400 /* USB Control Register */
1401 #define SDR0_USB0                    0x0320
1402 #define   SDR0_USB0_USB_DEVSEL_MASK   0x00000002    /* USB Device Selection */
1403 #define   SDR0_USB0_USB20D_DEVSEL     0x00000000      /* USB2.0 Device Selected */
1404 #define   SDR0_USB0_USB11D_DEVSEL     0x00000002      /* USB1.1 Device Selected */
1405 #define   SDR0_USB0_LEEN_MASK         0x00000001    /* Little Endian selection */
1406 #define   SDR0_USB0_LEEN_DISABLE      0x00000000      /* Little Endian Disable */
1407 #define   SDR0_USB0_LEEN_ENABLE       0x00000001      /* Little Endian Enable */
1408
1409 /* Miscealleneaous Function Reg. */
1410 #define SDR0_MFR                     0x4300
1411 #define   SDR0_MFR_ETH0_CLK_SEL_MASK   0x08000000   /* Ethernet0 Clock Select */
1412 #define   SDR0_MFR_ETH0_CLK_SEL_EXT    0x00000000
1413 #define   SDR0_MFR_ETH1_CLK_SEL_MASK   0x04000000   /* Ethernet1 Clock Select */
1414 #define   SDR0_MFR_ETH1_CLK_SEL_EXT    0x00000000
1415 #define   SDR0_MFR_ZMII_MODE_MASK      0x03000000   /* ZMII Mode Mask */
1416 #define   SDR0_MFR_ZMII_MODE_MII       0x00000000     /* ZMII Mode MII */
1417 #define   SDR0_MFR_ZMII_MODE_SMII      0x01000000     /* ZMII Mode SMII */
1418 #define   SDR0_MFR_ZMII_MODE_RMII_10M  0x02000000     /* ZMII Mode RMII - 10 Mbs */
1419 #define   SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000     /* ZMII Mode RMII - 100 Mbs */
1420 #define   SDR0_MFR_ZMII_MODE_BIT0      0x02000000     /* ZMII Mode Bit0 */
1421 #define   SDR0_MFR_ZMII_MODE_BIT1      0x01000000     /* ZMII Mode Bit1 */
1422 #define   SDR0_MFR_ZM_ENCODE(n)        ((((unsigned long)(n))&0x3)<<24)
1423 #define   SDR0_MFR_ZM_DECODE(n)        ((((unsigned long)(n))<<24)&0x3)
1424
1425 #define   SDR0_MFR_ERRATA3_EN0         0x00800000
1426 #define   SDR0_MFR_ERRATA3_EN1         0x00400000
1427 #define   SDR0_MFR_PKT_REJ_MASK        0x00180000   /* Pkt Rej. Enable Mask */
1428 #define   SDR0_MFR_PKT_REJ_EN          0x00180000   /* Pkt Rej. Enable on both EMAC3 0-1 */
1429 #define   SDR0_MFR_PKT_REJ_EN0         0x00100000   /* Pkt Rej. Enable on EMAC3(0) */
1430 #define   SDR0_MFR_PKT_REJ_EN1         0x00080000   /* Pkt Rej. Enable on EMAC3(1) */
1431 #define   SDR0_MFR_PKT_REJ_POL         0x00200000   /* Packet Reject Polarity */
1432
1433 #define GPT0_COMP6                      0x00000098
1434 #define GPT0_COMP5                      0x00000094
1435 #define GPT0_COMP4                      0x00000090
1436 #define GPT0_COMP3                      0x0000008C
1437 #define GPT0_COMP2                      0x00000088
1438 #define GPT0_COMP1                      0x00000084
1439
1440 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1441 #define SDR0_USB2D0CR                 0x0320
1442 #define   SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK   0x00000004    /* USB 2.0 Device/EBC Master Selection */
1443 #define   SDR0_USB2D0CR_USB2DEV_SELECTION      0x00000004    /* USB 2.0 Device Selection */
1444 #define   SDR0_USB2D0CR_EBC_SELECTION          0x00000000    /* EBC Selection */
1445
1446 #define   SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK   0x00000002    /* USB Device Interface Selection */
1447 #define   SDR0_USB2D0CR_USB20D_DEVSEL          0x00000000      /* USB2.0 Device Selected */
1448 #define   SDR0_USB2D0CR_USB11D_DEVSEL          0x00000002      /* USB1.1 Device Selected */
1449
1450 #define   SDR0_USB2D0CR_LEEN_MASK              0x00000001    /* Little Endian selection */
1451 #define   SDR0_USB2D0CR_LEEN_DISABLE           0x00000000      /* Little Endian Disable */
1452 #define   SDR0_USB2D0CR_LEEN_ENABLE            0x00000001      /* Little Endian Enable */
1453
1454 /* USB2 Host Control Register */
1455 #define SDR0_USB2H0CR                0x0340
1456 #define   SDR0_USB2H0CR_WDINT_MASK             0x00000001 /* Host UTMI Word Interface */
1457 #define   SDR0_USB2H0CR_WDINT_8BIT_60MHZ       0x00000000  /* 8-bit/60MHz */
1458 #define   SDR0_USB2H0CR_WDINT_16BIT_30MHZ      0x00000001  /* 16-bit/30MHz */
1459 #define   SDR0_USB2H0CR_EFLADJ_MASK            0x0000007e /* EHCI Frame Length Adjustment */
1460
1461 /* Pin Function Control Register 1 */
1462 #define SDR0_PFC1                    0x4101
1463 #define   SDR0_PFC1_U1ME_MASK                  0x02000000    /* UART1 Mode Enable */
1464 #define   SDR0_PFC1_U1ME_DSR_DTR               0x00000000      /* UART1 in DSR/DTR Mode */
1465 #define   SDR0_PFC1_U1ME_CTS_RTS               0x02000000      /* UART1 in CTS/RTS Mode */
1466
1467 #define   SDR0_PFC1_SELECT_MASK                0x01C00000 /* Ethernet Pin Select EMAC 0 */
1468 #define   SDR0_PFC1_SELECT_CONFIG_1_1          0x00C00000   /* 1xMII   using RGMII bridge */
1469 #define   SDR0_PFC1_SELECT_CONFIG_1_2          0x00000000   /* 1xMII   using  ZMII bridge */
1470 #define   SDR0_PFC1_SELECT_CONFIG_2            0x00C00000   /* 1xGMII  using RGMII bridge */
1471 #define   SDR0_PFC1_SELECT_CONFIG_3            0x01000000   /* 1xTBI   using RGMII bridge */
1472 #define   SDR0_PFC1_SELECT_CONFIG_4            0x01400000   /* 2xRGMII using RGMII bridge */
1473 #define   SDR0_PFC1_SELECT_CONFIG_5            0x01800000   /* 2xRTBI  using RGMII bridge */
1474 #define   SDR0_PFC1_SELECT_CONFIG_6            0x00800000   /* 2xSMII  using  ZMII bridge */
1475
1476 #define   SDR0_PFC1_U0ME_MASK                  0x00080000    /* UART0 Mode Enable */
1477 #define   SDR0_PFC1_U0ME_DSR_DTR               0x00000000      /* UART0 in DSR/DTR Mode */
1478 #define   SDR0_PFC1_U0ME_CTS_RTS               0x00080000      /* UART0 in CTS/RTS Mode */
1479 #define   SDR0_PFC1_U0IM_MASK                  0x00040000    /* UART0 Interface Mode */
1480 #define   SDR0_PFC1_U0IM_8PINS                 0x00000000      /* UART0 Interface Mode 8 pins */
1481 #define   SDR0_PFC1_U0IM_4PINS                 0x00040000      /* UART0 Interface Mode 4 pins */
1482 #define   SDR0_PFC1_SIS_MASK                   0x00020000    /* SCP or IIC1 Selection */
1483 #define   SDR0_PFC1_SIS_SCP_SEL                0x00000000      /* SCP Selected */
1484 #define   SDR0_PFC1_SIS_IIC1_SEL               0x00020000      /* IIC1 Selected */
1485 #define   SDR0_PFC1_UES_MASK                   0x00010000    /* USB2D_RX_Active / EBC_Hold Req Selection */
1486 #define   SDR0_PFC1_UES_USB2D_SEL              0x00000000      /* USB2D_RX_Active Selected */
1487 #define   SDR0_PFC1_UES_EBCHR_SEL              0x00010000      /* EBC_Hold Req Selected */
1488 #define   SDR0_PFC1_DIS_MASK                   0x00008000    /* DMA_Req(1) / UIC_IRQ(5) Selection */
1489 #define   SDR0_PFC1_DIS_DMAR_SEL               0x00000000      /* DMA_Req(1) Selected */
1490 #define   SDR0_PFC1_DIS_UICIRQ5_SEL            0x00008000      /* UIC_IRQ(5) Selected */
1491 #define   SDR0_PFC1_ERE_MASK                   0x00004000    /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
1492 #define   SDR0_PFC1_ERE_EXTR_SEL               0x00000000      /* EBC Mast.Ext.Req.En. Selected */
1493 #define   SDR0_PFC1_ERE_GPIO0_27_SEL           0x00004000      /* GPIO0(27) Selected */
1494 #define   SDR0_PFC1_UPR_MASK                   0x00002000    /* USB2 Device Packet Reject Selection */
1495 #define   SDR0_PFC1_UPR_DISABLE                0x00000000      /* USB2 Device Packet Reject Disable */
1496 #define   SDR0_PFC1_UPR_ENABLE                 0x00002000      /* USB2 Device Packet Reject Enable */
1497
1498 #define   SDR0_PFC1_PLB_PME_MASK               0x00001000    /* PLB3/PLB4 Perf. Monitor En. Selection */
1499 #define   SDR0_PFC1_PLB_PME_PLB3_SEL           0x00000000      /* PLB3 Performance Monitor Enable */
1500 #define   SDR0_PFC1_PLB_PME_PLB4_SEL           0x00001000      /* PLB3 Performance Monitor Enable */
1501 #define   SDR0_PFC1_GFGGI_MASK                 0x0000000F    /* GPT Frequency Generation Gated In */
1502
1503 /* Ethernet PLL Configuration Register */
1504 #define SDR0_PFC2                    0x4102
1505 #define   SDR0_PFC2_TUNE_MASK                  0x01FF8000  /* Loop stability tuning bits */
1506 #define   SDR0_PFC2_MULTI_MASK                 0x00007C00  /* Frequency multiplication selector */
1507 #define   SDR0_PFC2_RANGEB_MASK                0x00000380  /* PLLOUTB/C frequency selector */
1508 #define   SDR0_PFC2_RANGEA_MASK                0x00000071  /* PLLOUTA frequency selector */
1509
1510 #define   SDR0_PFC2_SELECT_MASK                0xE0000000  /* Ethernet Pin select EMAC1 */
1511 #define   SDR0_PFC2_SELECT_CONFIG_1_1          0x60000000   /* 1xMII   using RGMII bridge */
1512 #define   SDR0_PFC2_SELECT_CONFIG_1_2          0x00000000   /* 1xMII   using  ZMII bridge */
1513 #define   SDR0_PFC2_SELECT_CONFIG_2            0x60000000   /* 1xGMII  using RGMII bridge */
1514 #define   SDR0_PFC2_SELECT_CONFIG_3            0x80000000   /* 1xTBI   using RGMII bridge */
1515 #define   SDR0_PFC2_SELECT_CONFIG_4            0xA0000000   /* 2xRGMII using RGMII bridge */
1516 #define   SDR0_PFC2_SELECT_CONFIG_5            0xC0000000   /* 2xRTBI  using RGMII bridge */
1517 #define   SDR0_PFC2_SELECT_CONFIG_6            0x40000000   /* 2xSMII  using  ZMII bridge */
1518
1519 #define SDR0_PFC4               0x4104
1520
1521 /* USB2PHY0 Control Register */
1522 #define SDR0_USB2PHY0CR               0x4103
1523 #define   SDR0_USB2PHY0CR_UTMICN_MASK          0x00100000 /*  PHY UTMI interface connection */
1524 #define   SDR0_USB2PHY0CR_UTMICN_DEV           0x00000000  /* Device support */
1525 #define   SDR0_USB2PHY0CR_UTMICN_HOST          0x00100000  /* Host support */
1526
1527 #define   SDR0_USB2PHY0CR_DWNSTR_MASK          0x00400000 /* Select downstream port mode */
1528 #define   SDR0_USB2PHY0CR_DWNSTR_DEV           0x00000000  /* Device */
1529 #define   SDR0_USB2PHY0CR_DWNSTR_HOST          0x00400000  /* Host   */
1530
1531 #define   SDR0_USB2PHY0CR_DVBUS_MASK           0x00800000 /* VBus detect (Device mode only)  */
1532 #define   SDR0_USB2PHY0CR_DVBUS_PURDIS         0x00000000  /* Pull-up resistance on D+ is disabled */
1533 #define   SDR0_USB2PHY0CR_DVBUS_PUREN          0x00800000  /* Pull-up resistance on D+ is enabled */
1534
1535 #define   SDR0_USB2PHY0CR_WDINT_MASK           0x01000000 /* PHY UTMI data width and clock select  */
1536 #define   SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ     0x00000000  /* 8-bit data/60MHz */
1537 #define   SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ    0x01000000  /* 16-bit data/30MHz */
1538
1539 #define   SDR0_USB2PHY0CR_LOOPEN_MASK          0x02000000 /* Loop back test enable  */
1540 #define   SDR0_USB2PHY0CR_LOOP_ENABLE          0x00000000  /* Loop back disabled */
1541 #define   SDR0_USB2PHY0CR_LOOP_DISABLE         0x02000000  /* Loop back enabled (only test purposes) */
1542
1543 #define   SDR0_USB2PHY0CR_XOON_MASK            0x04000000 /* Force XO block on during a suspend  */
1544 #define   SDR0_USB2PHY0CR_XO_ON                0x00000000  /* PHY XO block is powered-on */
1545 #define   SDR0_USB2PHY0CR_XO_OFF               0x04000000  /* PHY XO block is powered-off when all ports are suspended */
1546
1547 #define   SDR0_USB2PHY0CR_PWRSAV_MASK          0x08000000 /* Select PHY power-save mode  */
1548 #define   SDR0_USB2PHY0CR_PWRSAV_OFF           0x00000000  /* Non-power-save mode */
1549 #define   SDR0_USB2PHY0CR_PWRSAV_ON            0x08000000  /* Power-save mode. Valid only for full-speed operation */
1550
1551 #define   SDR0_USB2PHY0CR_XOREF_MASK           0x10000000 /* Select reference clock source  */
1552 #define   SDR0_USB2PHY0CR_XOREF_INTERNAL       0x00000000  /* PHY PLL uses chip internal 48M clock as a reference */
1553 #define   SDR0_USB2PHY0CR_XOREF_XO             0x10000000  /* PHY PLL uses internal XO block output as a reference */
1554
1555 #define   SDR0_USB2PHY0CR_XOCLK_MASK           0x20000000 /* Select clock for XO block  */
1556 #define   SDR0_USB2PHY0CR_XOCLK_EXTERNAL       0x00000000  /* PHY macro used an external clock */
1557 #define   SDR0_USB2PHY0CR_XOCLK_CRYSTAL        0x20000000  /* PHY macro uses the clock from a crystal */
1558
1559 #define   SDR0_USB2PHY0CR_CLKSEL_MASK          0xc0000000 /* Select ref clk freq */
1560 #define   SDR0_USB2PHY0CR_CLKSEL_12MHZ         0x00000000 /* Select ref clk freq = 12 MHz*/
1561 #define   SDR0_USB2PHY0CR_CLKSEL_48MHZ         0x40000000 /* Select ref clk freq = 48 MHz*/
1562 #define   SDR0_USB2PHY0CR_CLKSEL_24MHZ         0x80000000 /* Select ref clk freq = 24 MHz*/
1563
1564 /* Miscealleneaous Function Reg. */
1565 #define SDR0_MFR                     0x4300
1566 #define   SDR0_MFR_ETH0_CLK_SEL_MASK   0x08000000   /* Ethernet0 Clock Select */
1567 #define   SDR0_MFR_ETH0_CLK_SEL_EXT    0x00000000
1568 #define   SDR0_MFR_ETH1_CLK_SEL_MASK   0x04000000   /* Ethernet1 Clock Select */
1569 #define   SDR0_MFR_ETH1_CLK_SEL_EXT    0x00000000
1570 #define   SDR0_MFR_ZMII_MODE_MASK      0x03000000   /* ZMII Mode Mask */
1571 #define   SDR0_MFR_ZMII_MODE_MII       0x00000000     /* ZMII Mode MII */
1572 #define   SDR0_MFR_ZMII_MODE_SMII      0x01000000     /* ZMII Mode SMII */
1573 #define   SDR0_MFR_ZMII_MODE_BIT0      0x02000000     /* ZMII Mode Bit0 */
1574 #define   SDR0_MFR_ZMII_MODE_BIT1      0x01000000     /* ZMII Mode Bit1 */
1575 #define   SDR0_MFR_ZM_ENCODE(n)        ((((unsigned long)(n))&0x3)<<24)
1576 #define   SDR0_MFR_ZM_DECODE(n)        ((((unsigned long)(n))<<24)&0x3)
1577
1578 #define   SDR0_MFR_ERRATA3_EN0         0x00800000
1579 #define   SDR0_MFR_ERRATA3_EN1         0x00400000
1580 #define   SDR0_MFR_PKT_REJ_MASK        0x00180000   /* Pkt Rej. Enable Mask */
1581 #define   SDR0_MFR_PKT_REJ_EN          0x00180000   /* Pkt Rej. Enable on both EMAC3 0-1 */
1582 #define   SDR0_MFR_PKT_REJ_EN0         0x00100000   /* Pkt Rej. Enable on EMAC3(0) */
1583 #define   SDR0_MFR_PKT_REJ_EN1         0x00080000   /* Pkt Rej. Enable on EMAC3(1) */
1584 #define   SDR0_MFR_PKT_REJ_POL         0x00200000   /* Packet Reject Polarity */
1585
1586 #endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
1587
1588 /* CUST1 Customer Configuration Register1 */
1589 #define   SDR0_CUST1                 0x4002
1590 #define   SDR0_CUST1_NDRSC_MASK       0xFFFF0000     /* NDRSC Device Read Count */
1591 #define   SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
1592 #define   SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
1593
1594 /* Pin Function Control Register 0 */
1595 #define SDR0_PFC0                    0x4100
1596 #define   SDR0_PFC0_CPU_TR_EN_MASK    0x00000100    /* CPU Trace Enable Mask */
1597 #define   SDR0_PFC0_CPU_TRACE_EN      0x00000100      /* CPU Trace Enable */
1598 #define   SDR0_PFC0_CPU_TRACE_DIS     0x00000100      /* CPU Trace Disable */
1599 #define   SDR0_PFC0_CTE_ENCODE(n)    ((((unsigned long)(n))&0x01)<<8)
1600 #define   SDR0_PFC0_CTE_DECODE(n)    ((((unsigned long)(n))>>8)&0x01)
1601
1602 /* Pin Function Control Register 1 */
1603 #define SDR0_PFC1                    0x4101
1604 #define   SDR0_PFC1_U1ME_MASK         0x02000000    /* UART1 Mode Enable */
1605 #define   SDR0_PFC1_U1ME_DSR_DTR      0x00000000      /* UART1 in DSR/DTR Mode */
1606 #define   SDR0_PFC1_U1ME_CTS_RTS      0x02000000      /* UART1 in CTS/RTS Mode */
1607 #define   SDR0_PFC1_U0ME_MASK         0x00080000    /* UART0 Mode Enable */
1608 #define   SDR0_PFC1_U0ME_DSR_DTR      0x00000000      /* UART0 in DSR/DTR Mode */
1609 #define   SDR0_PFC1_U0ME_CTS_RTS      0x00080000      /* UART0 in CTS/RTS Mode */
1610 #define   SDR0_PFC1_U0IM_MASK         0x00040000    /* UART0 Interface Mode */
1611 #define   SDR0_PFC1_U0IM_8PINS        0x00000000      /* UART0 Interface Mode 8 pins */
1612 #define   SDR0_PFC1_U0IM_4PINS        0x00040000      /* UART0 Interface Mode 4 pins */
1613 #define   SDR0_PFC1_SIS_MASK          0x00020000    /* SCP or IIC1 Selection */
1614 #define   SDR0_PFC1_SIS_SCP_SEL       0x00000000      /* SCP Selected */
1615 #define   SDR0_PFC1_SIS_IIC1_SEL      0x00020000      /* IIC1 Selected */
1616 #define   SDR0_PFC1_UES_MASK          0x00010000    /* USB2D_RX_Active / EBC_Hold Req Selection */
1617 #define   SDR0_PFC1_UES_USB2D_SEL     0x00000000      /* USB2D_RX_Active Selected */
1618 #define   SDR0_PFC1_UES_EBCHR_SEL     0x00010000      /* EBC_Hold Req Selected */
1619 #define   SDR0_PFC1_DIS_MASK          0x00008000    /* DMA_Req(1) / UIC_IRQ(5) Selection */
1620 #define   SDR0_PFC1_DIS_DMAR_SEL      0x00000000      /* DMA_Req(1) Selected */
1621 #define   SDR0_PFC1_DIS_UICIRQ5_SEL   0x00008000      /* UIC_IRQ(5) Selected */
1622 #define   SDR0_PFC1_ERE_MASK          0x00004000    /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
1623 #define   SDR0_PFC1_ERE_EXTR_SEL      0x00000000      /* EBC Mast.Ext.Req.En. Selected */
1624 #define   SDR0_PFC1_ERE_GPIO0_27_SEL  0x00004000      /* GPIO0(27) Selected */
1625 #define   SDR0_PFC1_UPR_MASK          0x00002000    /* USB2 Device Packet Reject Selection */
1626 #define   SDR0_PFC1_UPR_DISABLE       0x00000000      /* USB2 Device Packet Reject Disable */
1627 #define   SDR0_PFC1_UPR_ENABLE        0x00002000      /* USB2 Device Packet Reject Enable */
1628
1629 #define   SDR0_PFC1_PLB_PME_MASK      0x00001000    /* PLB3/PLB4 Perf. Monitor En. Selection */
1630 #define   SDR0_PFC1_PLB_PME_PLB3_SEL  0x00000000      /* PLB3 Performance Monitor Enable */
1631 #define   SDR0_PFC1_PLB_PME_PLB4_SEL  0x00001000      /* PLB3 Performance Monitor Enable */
1632 #define   SDR0_PFC1_GFGGI_MASK        0x0000000F    /* GPT Frequency Generation Gated In */
1633
1634 #endif /* 440EP || 440GR || 440EPX || 440GRX */
1635
1636 /*-----------------------------------------------------------------------------
1637  | L2 Cache
1638  +----------------------------------------------------------------------------*/
1639 #if defined (CONFIG_440GX) || \
1640     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
1641     defined(CONFIG_460EX) || defined(CONFIG_460GT)
1642 #define L2_CACHE_BASE   0x030
1643 #define l2_cache_cfg    (L2_CACHE_BASE+0x00)    /* L2 Cache Config      */
1644 #define l2_cache_cmd    (L2_CACHE_BASE+0x01)    /* L2 Cache Command     */
1645 #define l2_cache_addr   (L2_CACHE_BASE+0x02)    /* L2 Cache Address     */
1646 #define l2_cache_data   (L2_CACHE_BASE+0x03)    /* L2 Cache Data        */
1647 #define l2_cache_stat   (L2_CACHE_BASE+0x04)    /* L2 Cache Status      */
1648 #define l2_cache_cver   (L2_CACHE_BASE+0x05)    /* L2 Cache Revision ID */
1649 #define l2_cache_snp0   (L2_CACHE_BASE+0x06)    /* L2 Cache Snoop reg 0 */
1650 #define l2_cache_snp1   (L2_CACHE_BASE+0x07)    /* L2 Cache Snoop reg 1 */
1651
1652 #endif /* CONFIG_440GX */
1653
1654 /*-----------------------------------------------------------------------------
1655  | Internal SRAM
1656  +----------------------------------------------------------------------------*/
1657 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1658 #define ISRAM0_DCR_BASE 0x380
1659 #else
1660 #define ISRAM0_DCR_BASE 0x020
1661 #endif
1662 #define isram0_sb0cr    (ISRAM0_DCR_BASE+0x00)  /* SRAM bank config 0*/
1663 #define isram0_sb1cr    (ISRAM0_DCR_BASE+0x01)  /* SRAM bank config 1*/
1664 #define isram0_sb2cr    (ISRAM0_DCR_BASE+0x02)  /* SRAM bank config 2*/
1665 #define isram0_sb3cr    (ISRAM0_DCR_BASE+0x03)  /* SRAM bank config 3*/
1666 #define isram0_bear     (ISRAM0_DCR_BASE+0x04)  /* SRAM bus error addr reg */
1667 #define isram0_besr0    (ISRAM0_DCR_BASE+0x05)  /* SRAM bus error status reg 0 */
1668 #define isram0_besr1    (ISRAM0_DCR_BASE+0x06)  /* SRAM bus error status reg 1 */
1669 #define isram0_pmeg     (ISRAM0_DCR_BASE+0x07)  /* SRAM power management */
1670 #define isram0_cid      (ISRAM0_DCR_BASE+0x08)  /* SRAM bus core id reg */
1671 #define isram0_revid    (ISRAM0_DCR_BASE+0x09)  /* SRAM bus revision id reg */
1672 #define isram0_dpc      (ISRAM0_DCR_BASE+0x0a)  /* SRAM data parity check reg */
1673
1674 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1675     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1676     defined(CONFIG_460EX) || defined(CONFIG_460GT)
1677 /* CUST0 Customer Configuration Register0 */
1678 #define SDR0_CUST0                   0x4000
1679 #define   SDR0_CUST0_MUX_E_N_G_MASK   0xC0000000     /* Mux_Emac_NDFC_GPIO */
1680 #define   SDR0_CUST0_MUX_EMAC_SEL     0x40000000       /* Emac Selection */
1681 #define   SDR0_CUST0_MUX_NDFC_SEL     0x80000000       /* NDFC Selection */
1682 #define   SDR0_CUST0_MUX_GPIO_SEL     0xC0000000       /* GPIO Selection */
1683
1684 #define   SDR0_CUST0_NDFC_EN_MASK     0x20000000     /* NDFC Enable Mask */
1685 #define   SDR0_CUST0_NDFC_ENABLE      0x20000000       /* NDFC Enable */
1686 #define   SDR0_CUST0_NDFC_DISABLE     0x00000000       /* NDFC Disable */
1687
1688 #define   SDR0_CUST0_NDFC_BW_MASK     0x10000000     /* NDFC Boot Width */
1689 #define   SDR0_CUST0_NDFC_BW_16_BIT   0x10000000       /* NDFC Boot Width = 16 Bit */
1690 #define   SDR0_CUST0_NDFC_BW_8_BIT    0x00000000       /* NDFC Boot Width =  8 Bit */
1691
1692 #define   SDR0_CUST0_NDFC_BP_MASK     0x0F000000     /* NDFC Boot Page */
1693 #define   SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
1694 #define   SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
1695
1696 #define   SDR0_CUST0_NDFC_BAC_MASK    0x00C00000     /* NDFC Boot Address Cycle */
1697 #define   SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
1698 #define   SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
1699
1700 #define   SDR0_CUST0_NDFC_ARE_MASK    0x00200000     /* NDFC Auto Read Enable */
1701 #define   SDR0_CUST0_NDFC_ARE_ENABLE  0x00200000       /* NDFC Auto Read Enable */
1702 #define   SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000       /* NDFC Auto Read Disable */
1703
1704 #define   SDR0_CUST0_NRB_MASK         0x00100000     /* NDFC Ready / Busy */
1705 #define   SDR0_CUST0_NRB_BUSY         0x00100000       /* Busy */
1706 #define   SDR0_CUST0_NRB_READY        0x00000000       /* Ready */
1707
1708 #define   SDR0_CUST0_NDRSC_MASK       0x0000FFF0     /* NDFC Device Reset Count Mask */
1709 #define   SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
1710 #define   SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
1711
1712 #define   SDR0_CUST0_CHIPSELGAT_MASK  0x0000000F     /* Chip Select Gating Mask */
1713 #define   SDR0_CUST0_CHIPSELGAT_DIS   0x00000000       /* Chip Select Gating Disable */
1714 #define   SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F       /* All Chip Select Gating Enable */
1715 #define   SDR0_CUST0_CHIPSELGAT_EN0   0x00000008       /* Chip Select0 Gating Enable */
1716 #define   SDR0_CUST0_CHIPSELGAT_EN1   0x00000004       /* Chip Select1 Gating Enable */
1717 #define   SDR0_CUST0_CHIPSELGAT_EN2   0x00000002       /* Chip Select2 Gating Enable */
1718 #define   SDR0_CUST0_CHIPSELGAT_EN3   0x00000001       /* Chip Select3 Gating Enable */
1719 #endif
1720
1721 /*-----------------------------------------------------------------------------
1722  | On-Chip Buses
1723  +----------------------------------------------------------------------------*/
1724 /* TODO: as needed */
1725
1726 /*-----------------------------------------------------------------------------
1727  | Clocking, Power Management and Chip Control
1728  +----------------------------------------------------------------------------*/
1729 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
1730 #define CNTRL_DCR_BASE 0x160
1731 #else
1732 #define CNTRL_DCR_BASE 0x0b0
1733 #endif
1734 #if defined(CONFIG_440GX) || \
1735     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
1736     defined(CONFIG_460EX) || defined(CONFIG_460GT)
1737 #define cpc0_er         (CNTRL_DCR_BASE+0x00)   /* CPM enable register          */
1738 #define cpc0_fr         (CNTRL_DCR_BASE+0x01)   /* CPM force register           */
1739 #define cpc0_sr         (CNTRL_DCR_BASE+0x02)   /* CPM status register          */
1740 #else
1741 #define cpc0_sr         (CNTRL_DCR_BASE+0x00)   /* CPM status register          */
1742 #define cpc0_er         (CNTRL_DCR_BASE+0x01)   /* CPM enable register          */
1743 #define cpc0_fr         (CNTRL_DCR_BASE+0x02)   /* CPM force register           */
1744 #endif
1745
1746 #define cpc0_sys0       (CNTRL_DCR_BASE+0x30)   /* System configuration reg 0   */
1747 #define cpc0_sys1       (CNTRL_DCR_BASE+0x31)   /* System configuration reg 1   */
1748 #define cpc0_cust0      (CNTRL_DCR_BASE+0x32)   /* Customer configuration reg 0 */
1749 #define cpc0_cust1      (CNTRL_DCR_BASE+0x33)   /* Customer configuration reg 1 */
1750
1751 #define cpc0_strp0      (CNTRL_DCR_BASE+0x34)   /* Power-on config reg 0 (RO)   */
1752 #define cpc0_strp1      (CNTRL_DCR_BASE+0x35)   /* Power-on config reg 1 (RO)   */
1753 #define cpc0_strp2      (CNTRL_DCR_BASE+0x36)   /* Power-on config reg 2 (RO)   */
1754 #define cpc0_strp3      (CNTRL_DCR_BASE+0x37)   /* Power-on config reg 3 (RO)   */
1755
1756 #define cpc0_gpio       (CNTRL_DCR_BASE+0x38)   /* GPIO config reg (440GP)      */
1757
1758 #define cntrl0          (CNTRL_DCR_BASE+0x3b)   /* Control 0 register           */
1759 #define cntrl1          (CNTRL_DCR_BASE+0x3a)   /* Control 1 register           */
1760
1761 /*-----------------------------------------------------------------------------
1762  | Universal interrupt controller
1763  +----------------------------------------------------------------------------*/
1764 #define UIC_SR  0x0                     /* UIC status                      */
1765 #define UIC_ER  0x2                     /* UIC enable                      */
1766 #define UIC_CR  0x3                     /* UIC critical                    */
1767 #define UIC_PR  0x4                     /* UIC polarity                    */
1768 #define UIC_TR  0x5                     /* UIC triggering                  */
1769 #define UIC_MSR 0x6                     /* UIC masked status               */
1770 #define UIC_VR  0x7                     /* UIC vector                      */
1771 #define UIC_VCR 0x8                     /* UIC vector configuration        */
1772
1773 #define UIC0_DCR_BASE 0xc0
1774 #define uic0sr  (UIC0_DCR_BASE+0x0)   /* UIC0 status                       */
1775 #define uic0er  (UIC0_DCR_BASE+0x2)   /* UIC0 enable                       */
1776 #define uic0cr  (UIC0_DCR_BASE+0x3)   /* UIC0 critical                     */
1777 #define uic0pr  (UIC0_DCR_BASE+0x4)   /* UIC0 polarity                     */
1778 #define uic0tr  (UIC0_DCR_BASE+0x5)   /* UIC0 triggering                   */
1779 #define uic0msr (UIC0_DCR_BASE+0x6)   /* UIC0 masked status                */
1780 #define uic0vr  (UIC0_DCR_BASE+0x7)   /* UIC0 vector                       */
1781 #define uic0vcr (UIC0_DCR_BASE+0x8)   /* UIC0 vector configuration         */
1782
1783 #define UIC1_DCR_BASE 0xd0
1784 #define uic1sr  (UIC1_DCR_BASE+0x0)   /* UIC1 status                       */
1785 #define uic1er  (UIC1_DCR_BASE+0x2)   /* UIC1 enable                       */
1786 #define uic1cr  (UIC1_DCR_BASE+0x3)   /* UIC1 critical                     */
1787 #define uic1pr  (UIC1_DCR_BASE+0x4)   /* UIC1 polarity                     */
1788 #define uic1tr  (UIC1_DCR_BASE+0x5)   /* UIC1 triggering                   */
1789 #define uic1msr (UIC1_DCR_BASE+0x6)   /* UIC1 masked status                */
1790 #define uic1vr  (UIC1_DCR_BASE+0x7)   /* UIC1 vector                       */
1791 #define uic1vcr (UIC1_DCR_BASE+0x8)   /* UIC1 vector configuration         */
1792
1793 #if defined(CONFIG_440SPE) || \
1794     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1795     defined(CONFIG_460EX) || defined(CONFIG_460GT)
1796 #define UIC2_DCR_BASE 0xe0
1797 #define uic2sr  (UIC2_DCR_BASE+0x0)   /* UIC2 status-Read Clear         */
1798 #define uic2srs (UIC2_DCR_BASE+0x1)   /* UIC2 status-Read Set */
1799 #define uic2er  (UIC2_DCR_BASE+0x2)   /* UIC2 enable                    */
1800 #define uic2cr  (UIC2_DCR_BASE+0x3)   /* UIC2 critical                  */
1801 #define uic2pr  (UIC2_DCR_BASE+0x4)   /* UIC2 polarity                  */
1802 #define uic2tr  (UIC2_DCR_BASE+0x5)   /* UIC2 triggering                */
1803 #define uic2msr (UIC2_DCR_BASE+0x6)   /* UIC2 masked status             */
1804 #define uic2vr  (UIC2_DCR_BASE+0x7)   /* UIC2 vector                    */
1805 #define uic2vcr (UIC2_DCR_BASE+0x8)   /* UIC2 vector configuration      */
1806
1807 #define UIC3_DCR_BASE 0xf0
1808 #define uic3sr  (UIC3_DCR_BASE+0x0)   /* UIC3 status-Read Clear         */
1809 #define uic3srs (UIC3_DCR_BASE+0x1)   /* UIC3 status-Read Set */
1810 #define uic3er  (UIC3_DCR_BASE+0x2)   /* UIC3 enable                    */
1811 #define uic3cr  (UIC3_DCR_BASE+0x3)   /* UIC3 critical                  */
1812 #define uic3pr  (UIC3_DCR_BASE+0x4)   /* UIC3 polarity                  */
1813 #define uic3tr  (UIC3_DCR_BASE+0x5)   /* UIC3 triggering                */
1814 #define uic3msr (UIC3_DCR_BASE+0x6)   /* UIC3 masked status             */
1815 #define uic3vr  (UIC3_DCR_BASE+0x7)   /* UIC3 vector                    */
1816 #define uic3vcr (UIC3_DCR_BASE+0x8)   /* UIC3 vector configuration      */
1817 #endif /* CONFIG_440SPE */
1818
1819 #if defined(CONFIG_440GX)
1820 #define UIC2_DCR_BASE 0x210
1821 #define uic2sr  (UIC2_DCR_BASE+0x0)   /* UIC2 status                       */
1822 #define uic2er  (UIC2_DCR_BASE+0x2)   /* UIC2 enable                       */
1823 #define uic2cr  (UIC2_DCR_BASE+0x3)   /* UIC2 critical                     */
1824 #define uic2pr  (UIC2_DCR_BASE+0x4)   /* UIC2 polarity                     */
1825 #define uic2tr  (UIC2_DCR_BASE+0x5)   /* UIC2 triggering                   */
1826 #define uic2msr (UIC2_DCR_BASE+0x6)   /* UIC2 masked status                */
1827 #define uic2vr  (UIC2_DCR_BASE+0x7)   /* UIC2 vector                       */
1828 #define uic2vcr (UIC2_DCR_BASE+0x8)   /* UIC2 vector configuration         */
1829
1830
1831 #define UIC_DCR_BASE 0x200
1832 #define uicb0sr  (UIC_DCR_BASE+0x0)   /* UIC Base Status Register          */
1833 #define uicb0er  (UIC_DCR_BASE+0x2)   /* UIC Base enable                   */
1834 #define uicb0cr  (UIC_DCR_BASE+0x3)   /* UIC Base critical                 */
1835 #define uicb0pr  (UIC_DCR_BASE+0x4)   /* UIC Base polarity                 */
1836 #define uicb0tr  (UIC_DCR_BASE+0x5)   /* UIC Base triggering               */
1837 #define uicb0msr (UIC_DCR_BASE+0x6)   /* UIC Base masked status            */
1838 #define uicb0vr  (UIC_DCR_BASE+0x7)   /* UIC Base vector                   */
1839 #define uicb0vcr (UIC_DCR_BASE+0x8)   /* UIC Base vector configuration     */
1840 #endif /* CONFIG_440GX */
1841
1842 /* The following is for compatibility with 405 code */
1843 #define uicsr  uic0sr
1844 #define uicer  uic0er
1845 #define uiccr  uic0cr
1846 #define uicpr  uic0pr
1847 #define uictr  uic0tr
1848 #define uicmsr uic0msr
1849 #define uicvr  uic0vr
1850 #define uicvcr uic0vcr
1851
1852 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX)
1853 /*----------------------------------------------------------------------------+
1854 | Clock / Power-on-reset DCR's.
1855 +----------------------------------------------------------------------------*/
1856 #define CPR0_CLKUPD                     0x20
1857 #define CPR0_CLKUPD_BSY_MASK            0x80000000
1858 #define CPR0_CLKUPD_BSY_COMPLETED       0x00000000
1859 #define CPR0_CLKUPD_BSY_BUSY            0x80000000
1860 #define CPR0_CLKUPD_CUI_MASK            0x80000000
1861 #define CPR0_CLKUPD_CUI_DISABLE         0x00000000
1862 #define CPR0_CLKUPD_CUI_ENABLE          0x80000000
1863 #define CPR0_CLKUPD_CUD_MASK            0x40000000
1864 #define CPR0_CLKUPD_CUD_DISABLE         0x00000000
1865 #define CPR0_CLKUPD_CUD_ENABLE          0x40000000
1866
1867 #define CPR0_PLLC                       0x40
1868 #define CPR0_PLLC_RST_MASK              0x80000000
1869 #define CPR0_PLLC_RST_PLLLOCKED         0x00000000
1870 #define CPR0_PLLC_RST_PLLRESET          0x80000000
1871 #define CPR0_PLLC_ENG_MASK              0x40000000
1872 #define CPR0_PLLC_ENG_DISABLE           0x00000000
1873 #define CPR0_PLLC_ENG_ENABLE            0x40000000
1874 #define CPR0_PLLC_ENG_ENCODE(n)         ((((unsigned long)(n))&0x01)<<30)
1875 #define CPR0_PLLC_ENG_DECODE(n)         ((((unsigned long)(n))>>30)&0x01)
1876 #define CPR0_PLLC_SRC_MASK              0x20000000
1877 #define CPR0_PLLC_SRC_PLLOUTA           0x00000000
1878 #define CPR0_PLLC_SRC_PLLOUTB           0x20000000
1879 #define CPR0_PLLC_SRC_ENCODE(n)         ((((unsigned long)(n))&0x01)<<29)
1880 #define CPR0_PLLC_SRC_DECODE(n)         ((((unsigned long)(n))>>29)&0x01)
1881 #define CPR0_PLLC_SEL_MASK              0x07000000
1882 #define CPR0_PLLC_SEL_PLLOUT            0x00000000
1883 #define CPR0_PLLC_SEL_CPU               0x01000000
1884 #define CPR0_PLLC_SEL_EBC               0x05000000
1885 #define CPR0_PLLC_SEL_ENCODE(n)         ((((unsigned long)(n))&0x07)<<24)
1886 #define CPR0_PLLC_SEL_DECODE(n)         ((((unsigned long)(n))>>24)&0x07)
1887 #define CPR0_PLLC_TUNE_MASK             0x000003FF
1888 #define CPR0_PLLC_TUNE_ENCODE(n)        ((((unsigned long)(n))&0x3FF)<<0)
1889 #define CPR0_PLLC_TUNE_DECODE(n)        ((((unsigned long)(n))>>0)&0x3FF)
1890
1891 #define CPR0_PLLD                       0x60
1892 #define CPR0_PLLD_FBDV_MASK             0x1F000000
1893 #define CPR0_PLLD_FBDV_ENCODE(n)        ((((unsigned long)(n))&0x1F)<<24)
1894 #define CPR0_PLLD_FBDV_DECODE(n)        ((((((unsigned long)(n))>>24)-1)&0x1F)+1)
1895 #define CPR0_PLLD_FWDVA_MASK            0x000F0000
1896 #define CPR0_PLLD_FWDVA_ENCODE(n)       ((((unsigned long)(n))&0x0F)<<16)
1897 #define CPR0_PLLD_FWDVA_DECODE(n)       ((((((unsigned long)(n))>>16)-1)&0x0F)+1)
1898 #define CPR0_PLLD_FWDVB_MASK            0x00000700
1899 #define CPR0_PLLD_FWDVB_ENCODE(n)       ((((unsigned long)(n))&0x07)<<8)
1900 #define CPR0_PLLD_FWDVB_DECODE(n)       ((((((unsigned long)(n))>>8)-1)&0x07)+1)
1901 #define CPR0_PLLD_LFBDV_MASK            0x0000003F
1902 #define CPR0_PLLD_LFBDV_ENCODE(n)       ((((unsigned long)(n))&0x3F)<<0)
1903 #define CPR0_PLLD_LFBDV_DECODE(n)       ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
1904
1905 #define CPR0_PRIMAD                     0x80
1906 #define CPR0_PRIMAD_PRADV0_MASK         0x07000000
1907 #define CPR0_PRIMAD_PRADV0_ENCODE(n)    ((((unsigned long)(n))&0x07)<<24)
1908 #define CPR0_PRIMAD_PRADV0_DECODE(n)    ((((((unsigned long)(n))>>24)-1)&0x07)+1)
1909
1910 #define CPR0_PRIMBD                     0xA0
1911 #define CPR0_PRIMBD_PRBDV0_MASK         0x07000000
1912 #define CPR0_PRIMBD_PRBDV0_ENCODE(n)    ((((unsigned long)(n))&0x07)<<24)
1913 #define CPR0_PRIMBD_PRBDV0_DECODE(n)    ((((((unsigned long)(n))>>24)-1)&0x07)+1)
1914
1915 #define CPR0_OPBD                       0xC0
1916 #define CPR0_OPBD_OPBDV0_MASK           0x03000000
1917 #define CPR0_OPBD_OPBDV0_ENCODE(n)      ((((unsigned long)(n))&0x03)<<24)
1918 #define CPR0_OPBD_OPBDV0_DECODE(n)      ((((((unsigned long)(n))>>24)-1)&0x03)+1)
1919
1920 #define CPR0_PERD                       0xE0
1921 #if !defined(CONFIG_440EPX)
1922 #define CPR0_PERD_PERDV0_MASK           0x03000000
1923 #define CPR0_PERD_PERDV0_ENCODE(n)      ((((unsigned long)(n))&0x03)<<24)
1924 #define CPR0_PERD_PERDV0_DECODE(n)      ((((((unsigned long)(n))>>24)-1)&0x03)+1)
1925 #endif
1926
1927 #define CPR0_MALD                       0x100
1928 #define CPR0_MALD_MALDV0_MASK           0x03000000
1929 #define CPR0_MALD_MALDV0_ENCODE(n)      ((((unsigned long)(n))&0x03)<<24)
1930 #define CPR0_MALD_MALDV0_DECODE(n)      ((((((unsigned long)(n))>>24)-1)&0x03)+1)
1931
1932 #define CPR0_ICFG                       0x140
1933 #define CPR0_ICFG_RLI_MASK              0x80000000
1934 #define CPR0_ICFG_RLI_RESETCPR          0x00000000
1935 #define CPR0_ICFG_RLI_PRESERVECPR       0x80000000
1936 #define CPR0_ICFG_ICS_MASK              0x00000007
1937 #define CPR0_ICFG_ICS_ENCODE(n)         ((((unsigned long)(n))&0x3F)<<0)
1938 #define CPR0_ICFG_ICS_DECODE(n)         ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
1939
1940 /************************/
1941 /* IIC defines          */
1942 /************************/
1943 #define IIC0_MMIO_BASE 0xA0000400
1944 #define IIC1_MMIO_BASE 0xA0000500
1945
1946 #endif /* CONFIG_440SP */
1947
1948 /*-----------------------------------------------------------------------------
1949  | DMA
1950  +----------------------------------------------------------------------------*/
1951 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
1952 #define DMA_DCR_BASE 0x200
1953 #else
1954 #define DMA_DCR_BASE 0x100
1955 #endif
1956 #define dmacr0  (DMA_DCR_BASE+0x00)  /* DMA channel control register 0       */
1957 #define dmact0  (DMA_DCR_BASE+0x01)  /* DMA count register 0                 */
1958 #define dmasah0 (DMA_DCR_BASE+0x02)  /* DMA source address high 0            */
1959 #define dmasal0 (DMA_DCR_BASE+0x03)  /* DMA source address low 0             */
1960 #define dmadah0 (DMA_DCR_BASE+0x04)  /* DMA destination address high 0       */
1961 #define dmadal0 (DMA_DCR_BASE+0x05)  /* DMA destination address low 0        */
1962 #define dmasgh0 (DMA_DCR_BASE+0x06)  /* DMA scatter/gather desc addr high 0  */
1963 #define dmasgl0 (DMA_DCR_BASE+0x07)  /* DMA scatter/gather desc addr low 0   */
1964 #define dmacr1  (DMA_DCR_BASE+0x08)  /* DMA channel control register 1       */
1965 #define dmact1  (DMA_DCR_BASE+0x09)  /* DMA count register 1                 */
1966 #define dmasah1 (DMA_DCR_BASE+0x0a)  /* DMA source address high 1            */
1967 #define dmasal1 (DMA_DCR_BASE+0x0b)  /* DMA source address low 1             */
1968 #define dmadah1 (DMA_DCR_BASE+0x0c)  /* DMA destination address high 1       */
1969 #define dmadal1 (DMA_DCR_BASE+0x0d)  /* DMA destination address low 1        */
1970 #define dmasgh1 (DMA_DCR_BASE+0x0e)  /* DMA scatter/gather desc addr high 1  */
1971 #define dmasgl1 (DMA_DCR_BASE+0x0f)  /* DMA scatter/gather desc addr low 1   */
1972 #define dmacr2  (DMA_DCR_BASE+0x10)  /* DMA channel control register 2       */
1973 #define dmact2  (DMA_DCR_BASE+0x11)  /* DMA count register 2                 */
1974 #define dmasah2 (DMA_DCR_BASE+0x12)  /* DMA source address high 2            */
1975 #define dmasal2 (DMA_DCR_BASE+0x13)  /* DMA source address low 2             */
1976 #define dmadah2 (DMA_DCR_BASE+0x14)  /* DMA destination address high 2       */
1977 #define dmadal2 (DMA_DCR_BASE+0x15)  /* DMA destination address low 2        */
1978 #define dmasgh2 (DMA_DCR_BASE+0x16)  /* DMA scatter/gather desc addr high 2  */
1979 #define dmasgl2 (DMA_DCR_BASE+0x17)  /* DMA scatter/gather desc addr low 2   */
1980 #define dmacr3  (DMA_DCR_BASE+0x18)  /* DMA channel control register 2       */
1981 #define dmact3  (DMA_DCR_BASE+0x19)  /* DMA count register 2                 */
1982 #define dmasah3 (DMA_DCR_BASE+0x1a)  /* DMA source address high 2            */
1983 #define dmasal3 (DMA_DCR_BASE+0x1b)  /* DMA source address low 2             */
1984 #define dmadah3 (DMA_DCR_BASE+0x1c)  /* DMA destination address high 2       */
1985 #define dmadal3 (DMA_DCR_BASE+0x1d)  /* DMA destination address low 2        */
1986 #define dmasgh3 (DMA_DCR_BASE+0x1e)  /* DMA scatter/gather desc addr high 2  */
1987 #define dmasgl3 (DMA_DCR_BASE+0x1f)  /* DMA scatter/gather desc addr low 2   */
1988 #define dmasr   (DMA_DCR_BASE+0x20)  /* DMA status register                  */
1989 #define dmasgc  (DMA_DCR_BASE+0x23)  /* DMA scatter/gather command register  */
1990 #define dmaslp  (DMA_DCR_BASE+0x25)  /* DMA sleep mode register              */
1991 #define dmapol  (DMA_DCR_BASE+0x26)  /* DMA polarity configuration register  */
1992
1993 /*-----------------------------------------------------------------------------
1994  | Memory Access Layer
1995  +----------------------------------------------------------------------------*/
1996 #define MAL_DCR_BASE 0x180
1997 #define malmcr      (MAL_DCR_BASE+0x00) /* MAL Config reg                   */
1998 #define malesr      (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear)    */
1999 #define malier      (MAL_DCR_BASE+0x02) /* Interrupt enable reg             */
2000 #define maldbr      (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only)        */
2001 #define maltxcasr   (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)      */
2002 #define maltxcarr   (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset)    */
2003 #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg  */
2004 #define maltxdeir   (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg          */
2005 #define maltxtattrr (MAL_DCR_BASE+0x08) /* TX PLB attribute reg             */
2006 #define maltxbattr  (MAL_DCR_BASE+0x09) /* TX descriptor base addr reg      */
2007 #define malrxcasr   (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)      */
2008 #define malrxcarr   (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset)    */
2009 #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg  */
2010 #define malrxdeir   (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg          */
2011 #define malrxtattrr (MAL_DCR_BASE+0x14) /* RX PLB attribute reg             */
2012 #define malrxbattr  (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg      */
2013 #define maltxctp0r  (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg   */
2014 #define maltxctp1r  (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg   */
2015 #define maltxctp2r  (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg   */
2016 #define maltxctp3r  (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg   */
2017 #define malrxctp0r  (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg   */
2018 #define malrxctp1r  (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg   */
2019 #define malrcbs0    (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg     */
2020 #define malrcbs1    (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg     */
2021 #if defined(CONFIG_440GX) || \
2022     defined(CONFIG_460EX) || defined(CONFIG_460GT)
2023 #define malrxctp2r  (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg   */
2024 #define malrxctp3r  (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg   */
2025 #define malrxctp8r  (MAL_DCR_BASE+0x48) /* RX 8 Channel table pointer reg   */
2026 #define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table pointer reg  */
2027 #define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table pointer reg  */
2028 #define malrcbs2    (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg     */
2029 #define malrcbs3    (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg     */
2030 #define malrcbs8    (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg     */
2031 #define malrcbs16   (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg    */
2032 #define malrcbs24   (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg    */
2033 #endif /* CONFIG_440GX */
2034
2035
2036 /*---------------------------------------------------------------------------+
2037 |  Universal interrupt controller 0 interrupts (UIC0)
2038 +---------------------------------------------------------------------------*/
2039 #if defined(CONFIG_440SP)
2040 #define UIC_U0          0x80000000      /* UART 0                           */
2041 #define UIC_U1          0x40000000      /* UART 1                           */
2042 #define UIC_IIC0        0x20000000      /* IIC                              */
2043 #define UIC_IIC1        0x10000000      /* IIC                              */
2044 #define UIC_PIM         0x08000000      /* PCI0 inbound message             */
2045 #define UIC_PCRW        0x04000000      /* PCI0 command write register      */
2046 #define UIC_PPM         0x02000000      /* PCI0 power management            */
2047 #define UIC_PVPD        0x01000000      /* PCI0 VPD Access                  */
2048 #define UIC_MSI0        0x00800000      /* PCI0 MSI level 0                 */
2049 #define UIC_P1IM        0x00400000      /* PCI1 Inbound Message             */
2050 #define UIC_P1CRW       0x00200000      /* PCI1 command write register      */
2051 #define UIC_P1PM        0x00100000      /* PCI1 power management            */
2052 #define UIC_P1VPD       0x00080000      /* PCI1 VPD Access                  */
2053 #define UIC_P1MSI0      0x00040000      /* PCI1 MSI level 0                 */
2054 #define UIC_P2IM        0x00020000      /* PCI2 inbound message             */
2055 #define UIC_P2CRW       0x00010000      /* PCI2 command register write      */
2056 #define UIC_P2PM        0x00008000      /* PCI2 power management            */
2057 #define UIC_P2VPD       0x00004000      /* PCI2 VPD access                  */
2058 #define UIC_P2MSI0      0x00002000      /* PCI2 MSI level 0                 */
2059 #define UIC_D0CPF       0x00001000      /* DMA0 command pointer             */
2060 #define UIC_D0CSF       0x00000800      /* DMA0 command status              */
2061 #define UIC_D1CPF       0x00000400      /* DMA1 command pointer             */
2062 #define UIC_D1CSF       0x00000200      /* DMA1 command status              */
2063 #define UIC_I2OID       0x00000100      /* I2O inbound doorbell             */
2064 #define UIC_I2OPLF      0x00000080      /* I2O inbound post list            */
2065 #define UIC_I2O0LL      0x00000040      /* I2O0 low latency PLB write       */
2066 #define UIC_I2O1LL      0x00000020      /* I2O1 low latency PLB write       */
2067 #define UIC_I2O0HB      0x00000010      /* I2O0 high bandwidth PLB write    */
2068 #define UIC_I2O1HB      0x00000008      /* I2O1 high bandwidth PLB write    */
2069 #define UIC_GPTCT       0x00000004      /* GPT count timer                  */
2070 #define UIC_UIC1NC      0x00000002      /* UIC1 non-critical interrupt      */
2071 #define UIC_UIC1C       0x00000001      /* UIC1 critical interrupt          */
2072 #elif defined(CONFIG_440GX) || defined(CONFIG_440EP)
2073 #define UIC_U0          0x80000000      /* UART 0                           */
2074 #define UIC_U1          0x40000000      /* UART 1                           */
2075 #define UIC_IIC0        0x20000000      /* IIC                              */
2076 #define UIC_IIC1        0x10000000      /* IIC                              */
2077 #define UIC_PIM         0x08000000      /* PCI inbound message              */
2078 #define UIC_PCRW        0x04000000      /* PCI command register write       */
2079 #define UIC_PPM         0x02000000      /* PCI power management             */
2080 #define UIC_MSI0        0x01000000      /* PCI MSI level 0                  */
2081 #define UIC_MSI1        0x00800000      /* PCI MSI level 1                  */
2082 #define UIC_MSI2        0x00400000      /* PCI MSI level 2                  */
2083 #define UIC_MTE         0x00200000      /* MAL TXEOB                        */
2084 #define UIC_MRE         0x00100000      /* MAL RXEOB                        */
2085 #define UIC_D0          0x00080000      /* DMA channel 0                    */
2086 #define UIC_D1          0x00040000      /* DMA channel 1                    */
2087 #define UIC_D2          0x00020000      /* DMA channel 2                    */
2088 #define UIC_D3          0x00010000      /* DMA channel 3                    */
2089 #define UIC_RSVD0       0x00008000      /* Reserved                         */
2090 #define UIC_RSVD1       0x00004000      /* Reserved                         */
2091 #define UIC_CT0         0x00002000      /* GPT compare timer 0              */
2092 #define UIC_CT1         0x00001000      /* GPT compare timer 1              */
2093 #define UIC_CT2         0x00000800      /* GPT compare timer 2              */
2094 #define UIC_CT3         0x00000400      /* GPT compare timer 3              */
2095 #define UIC_CT4         0x00000200      /* GPT compare timer 4              */
2096 #define UIC_EIR0        0x00000100      /* External interrupt 0             */
2097 #define UIC_EIR1        0x00000080      /* External interrupt 1             */
2098 #define UIC_EIR2        0x00000040      /* External interrupt 2             */
2099 #define UIC_EIR3        0x00000020      /* External interrupt 3             */
2100 #define UIC_EIR4        0x00000010      /* External interrupt 4             */
2101 #define UIC_EIR5        0x00000008      /* External interrupt 5             */
2102 #define UIC_EIR6        0x00000004      /* External interrupt 6             */
2103 #define UIC_UIC1NC      0x00000002      /* UIC1 non-critical interrupt      */
2104 #define UIC_UIC1C       0x00000001      /* UIC1 critical interrupt          */
2105
2106 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
2107
2108 #define UIC_U0        0x80000000  /* UART 0                             */
2109 #define UIC_U1        0x40000000  /* UART 1                             */
2110 #define UIC_IIC0      0x20000000  /* IIC                                */
2111 #define UIC_KRD       0x10000000  /* Kasumi Ready for data              */
2112 #define UIC_KDA       0x08000000  /* Kasumi Data Available              */
2113 #define UIC_PCRW      0x04000000  /* PCI command register write         */
2114 #define UIC_PPM       0x02000000  /* PCI power management               */
2115 #define UIC_IIC1      0x01000000  /* IIC                                */
2116 #define UIC_SPI       0x00800000  /* SPI                                */
2117 #define UIC_EPCISER   0x00400000  /* External PCI SERR                  */
2118 #define UIC_MTE       0x00200000  /* MAL TXEOB                          */
2119 #define UIC_MRE       0x00100000  /* MAL RXEOB                          */
2120 #define UIC_D0        0x00080000  /* DMA channel 0                      */
2121 #define UIC_D1        0x00040000  /* DMA channel 1                      */
2122 #define UIC_D2        0x00020000  /* DMA channel 2                      */
2123 #define UIC_D3        0x00010000  /* DMA channel 3                      */
2124 #define UIC_UD0       0x00008000  /* UDMA irq 0                         */
2125 #define UIC_UD1       0x00004000  /* UDMA irq 1                         */
2126 #define UIC_UD2       0x00002000  /* UDMA irq 2                         */
2127 #define UIC_UD3       0x00001000  /* UDMA irq 3                         */
2128 #define UIC_HSB2D     0x00000800  /* USB2.0 Device                      */
2129 #define UIC_OHCI1     0x00000400  /* USB2.0 Host OHCI irq 1             */
2130 #define UIC_OHCI2     0x00000200  /* USB2.0 Host OHCI irq 2             */
2131 #define UIC_EIP94     0x00000100  /* Security EIP94                     */
2132 #define UIC_ETH0      0x00000080  /* Emac 0                             */
2133 #define UIC_ETH1      0x00000040  /* Emac 1                             */
2134 #define UIC_EHCI      0x00000020  /* USB2.0 Host EHCI                   */
2135 #define UIC_EIR4      0x00000010  /* External interrupt 4               */
2136 #define UIC_UIC2NC    0x00000008  /* UIC2 non-critical interrupt        */
2137 #define UIC_UIC2C     0x00000004  /* UIC2 critical interrupt            */
2138 #define UIC_UIC1NC    0x00000002  /* UIC1 non-critical interrupt        */
2139 #define UIC_UIC1C     0x00000001  /* UIC1 critical interrupt            */
2140
2141 /* For compatibility with 405 code */
2142 #define UIC_MAL_TXEOB   UIC_MTE
2143 #define UIC_MAL_RXEOB   UIC_MRE
2144
2145 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
2146
2147 #define UIC_RSVD0       0x80000000      /* N/A - unused                     */
2148 #define UIC_U1          0x40000000      /* UART 1                           */
2149 #define UIC_IIC0        0x20000000      /* IIC                              */
2150 #define UIC_IIC1        0x10000000      /* IIC                              */
2151 #define UIC_PIM         0x08000000      /* PCI inbound message              */
2152 #define UIC_PCRW        0x04000000      /* PCI command register write       */
2153 #define UIC_PPM         0x02000000      /* PCI power management             */
2154 #define UIC_PCIVPD      0x01000000      /* PCI VPD                          */
2155 #define UIC_MSI0        0x00800000      /* PCI MSI level 0                  */
2156 #define UIC_EIR0        0x00400000      /* External interrupt 0             */
2157 #define UIC_UIC2NC      0x00200000      /* UIC2 non-critical interrupt      */
2158 #define UIC_UIC2C       0x00100000      /* UIC2 critical interrupt          */
2159 #define UIC_D0          0x00080000      /* DMA channel 0                    */
2160 #define UIC_D1          0x00040000      /* DMA channel 1                    */
2161 #define UIC_D2          0x00020000      /* DMA channel 2                    */
2162 #define UIC_D3          0x00010000      /* DMA channel 3                    */
2163 #define UIC_UIC3NC      0x00008000      /* UIC3 non-critical interrupt      */
2164 #define UIC_UIC3C       0x00004000      /* UIC3 critical interrupt          */
2165 #define UIC_EIR1        0x00002000      /* External interrupt 1             */
2166 #define UIC_TRNGDA      0x00001000      /* TRNG data available              */
2167 #define UIC_PKAR1       0x00000800      /* PKA ready (PKA[1])               */
2168 #define UIC_D1CPFF      0x00000400      /* DMA1 cp fifo full                */
2169 #define UIC_D1CSNS      0x00000200      /* DMA1 cs fifo needs service       */
2170 #define UIC_I2OID       0x00000100      /* I2O inbound door bell            */
2171 #define UIC_I2OLNE      0x00000080      /* I2O Inbound Post List FIFO Not Empty */
2172 #define UIC_I20R0LL     0x00000040      /* I2O Region 0 Low Latency PLB Write */
2173 #define UIC_I2OR1LL     0x00000020      /* I2O Region 1 Low Latency PLB Write */
2174 #define UIC_I20R0HB     0x00000010      /* I2O Region 0 High Bandwidth PLB Write */
2175 #define UIC_I2OR1HB     0x00000008      /* I2O Region 1 High Bandwidth PLB Write */
2176 #define UIC_EIP94       0x00000004      /* Security EIP94                   */
2177 #define UIC_UIC1NC      0x00000002      /* UIC1 non-critical interrupt      */
2178 #define UIC_UIC1C       0x00000001      /* UIC1 critical interrupt          */
2179
2180 #elif !defined(CONFIG_440SPE)
2181 #define UIC_U0          0x80000000      /* UART 0                           */
2182 #define UIC_U1          0x40000000      /* UART 1                           */
2183 #define UIC_IIC0        0x20000000      /* IIC                              */
2184 #define UIC_IIC1        0x10000000      /* IIC                              */
2185 #define UIC_PIM         0x08000000      /* PCI inbound message              */
2186 #define UIC_PCRW        0x04000000      /* PCI command register write       */
2187 #define UIC_PPM         0x02000000      /* PCI power management             */
2188 #define UIC_MSI0        0x01000000      /* PCI MSI level 0                  */
2189 #define UIC_MSI1        0x00800000      /* PCI MSI level 1                  */
2190 #define UIC_MSI2        0x00400000      /* PCI MSI level 2                  */
2191 #define UIC_MTE         0x00200000      /* MAL TXEOB                        */
2192 #define UIC_MRE         0x00100000      /* MAL RXEOB                        */
2193 #define UIC_D0          0x00080000      /* DMA channel 0                    */
2194 #define UIC_D1          0x00040000      /* DMA channel 1                    */
2195 #define UIC_D2          0x00020000      /* DMA channel 2                    */
2196 #define UIC_D3          0x00010000      /* DMA channel 3                    */
2197 #define UIC_RSVD0       0x00008000      /* Reserved                         */
2198 #define UIC_RSVD1       0x00004000      /* Reserved                         */
2199 #define UIC_CT0         0x00002000      /* GPT compare timer 0              */
2200 #define UIC_CT1         0x00001000      /* GPT compare timer 1              */
2201 #define UIC_CT2         0x00000800      /* GPT compare timer 2              */
2202 #define UIC_CT3         0x00000400      /* GPT compare timer 3              */
2203 #define UIC_CT4         0x00000200      /* GPT compare timer 4              */
2204 #define UIC_EIR0        0x00000100      /* External interrupt 0             */
2205 #define UIC_EIR1        0x00000080      /* External interrupt 1             */
2206 #define UIC_EIR2        0x00000040      /* External interrupt 2             */
2207 #define UIC_EIR3        0x00000020      /* External interrupt 3             */
2208 #define UIC_EIR4        0x00000010      /* External interrupt 4             */
2209 #define UIC_EIR5        0x00000008      /* External interrupt 5             */
2210 #define UIC_EIR6        0x00000004      /* External interrupt 6             */
2211 #define UIC_UIC1NC      0x00000002      /* UIC1 non-critical interrupt      */
2212 #define UIC_UIC1C       0x00000001      /* UIC1 critical interrupt          */
2213 #endif /* CONFIG_440GX */
2214
2215 /* For compatibility with 405 code */
2216 #define UIC_MAL_TXEOB   UIC_MTE
2217 #define UIC_MAL_RXEOB   UIC_MRE
2218
2219 /*---------------------------------------------------------------------------+
2220 |  Universal interrupt controller 1 interrupts (UIC1)
2221 +---------------------------------------------------------------------------*/
2222 #if defined(CONFIG_440SP)
2223 #define UIC_EIR0        0x80000000      /* External interrupt 0             */
2224 #define UIC_MS          0x40000000      /* MAL SERR                         */
2225 #define UIC_MTDE        0x20000000      /* MAL TXDE                         */
2226 #define UIC_MRDE        0x10000000      /* MAL RXDE                         */
2227 #define UIC_DECE        0x08000000      /* DDR SDRAM correctible error      */
2228 #define UIC_EBCO        0x04000000      /* EBCO interrupt status            */
2229 #define UIC_MTE         0x02000000      /* MAL TXEOB                        */
2230 #define UIC_MRE         0x01000000      /* MAL RXEOB                        */
2231 #define UIC_P0MSI1      0x00800000      /* PCI0 MSI level 1                 */
2232 #define UIC_P1MSI1      0x00400000      /* PCI1 MSI level 1                 */
2233 #define UIC_P2MSI1      0x00200000      /* PCI2 MSI level 1                 */
2234 #define UIC_L2C         0x00100000      /* L2 cache                         */
2235 #define UIC_CT0         0x00080000      /* GPT compare timer 0              */
2236 #define UIC_CT1         0x00040000      /* GPT compare timer 1              */
2237 #define UIC_CT2         0x00020000      /* GPT compare timer 2              */
2238 #define UIC_CT3         0x00010000      /* GPT compare timer 3              */
2239 #define UIC_CT4         0x00008000      /* GPT compare timer 4              */
2240 #define UIC_EIR1        0x00004000      /* External interrupt 1             */
2241 #define UIC_EIR2        0x00002000      /* External interrupt 2             */
2242 #define UIC_EIR3        0x00001000      /* External interrupt 3             */
2243 #define UIC_EIR4        0x00000800      /* External interrupt 4             */
2244 #define UIC_EIR5        0x00000400      /* External interrupt 5             */
2245 #define UIC_DMAE        0x00000200      /* DMA error                        */
2246 #define UIC_I2OE        0x00000100      /* I2O error                        */
2247 #define UIC_SRE         0x00000080      /* Serial ROM error                 */
2248 #define UIC_P0AE        0x00000040      /* PCI0 asynchronous error          */
2249 #define UIC_P1AE        0x00000020      /* PCI1 asynchronous error          */
2250 #define UIC_P2AE        0x00000010      /* PCI2 asynchronous error          */
2251 #define UIC_ETH0        0x00000008      /* Ethernet 0                       */
2252 #define UIC_EWU0        0x00000004      /* Ethernet 0 wakeup                */
2253 #define UIC_ETH1        0x00000002      /* Reserved                         */
2254 #define UIC_XOR         0x00000001      /* XOR                              */
2255 #elif defined(CONFIG_440GX) || defined(CONFIG_440EP)
2256 #define UIC_MS          0x80000000      /* MAL SERR                         */
2257 #define UIC_MTDE        0x40000000      /* MAL TXDE                         */
2258 #define UIC_MRDE        0x20000000      /* MAL RXDE                         */
2259 #define UIC_DEUE        0x10000000      /* DDR SDRAM ECC uncorrectible error*/
2260 #define UIC_DECE        0x08000000      /* DDR SDRAM correctible error      */
2261 #define UIC_EBCO        0x04000000      /* EBCO interrupt status            */
2262 #define UIC_EBMI        0x02000000      /* EBMI interrupt status            */
2263 #define UIC_OPB         0x01000000      /* OPB to PLB bridge interrupt stat */
2264 #define UIC_MSI3        0x00800000      /* PCI MSI level 3                  */
2265 #define UIC_MSI4        0x00400000      /* PCI MSI level 4                  */
2266 #define UIC_MSI5        0x00200000      /* PCI MSI level 5                  */
2267 #define UIC_MSI6        0x00100000      /* PCI MSI level 6                  */
2268 #define UIC_MSI7        0x00080000      /* PCI MSI level 7                  */
2269 #define UIC_MSI8        0x00040000      /* PCI MSI level 8                  */
2270 #define UIC_MSI9        0x00020000      /* PCI MSI level 9                  */
2271 #define UIC_MSI10       0x00010000      /* PCI MSI level 10                 */
2272 #define UIC_MSI11       0x00008000      /* PCI MSI level 11                 */
2273 #define UIC_PPMI        0x00004000      /* PPM interrupt status             */
2274 #define UIC_EIR7        0x00002000      /* External interrupt 7             */
2275 #define UIC_EIR8        0x00001000      /* External interrupt 8             */
2276 #define UIC_EIR9        0x00000800      /* External interrupt 9             */
2277 #define UIC_EIR10       0x00000400      /* External interrupt 10            */
2278 #define UIC_EIR11       0x00000200      /* External interrupt 11            */
2279 #define UIC_EIR12       0x00000100      /* External interrupt 12            */
2280 #define UIC_SRE         0x00000080      /* Serial ROM error                 */
2281 #define UIC_RSVD2       0x00000040      /* Reserved                         */
2282 #define UIC_RSVD3       0x00000020      /* Reserved                         */
2283 #define UIC_PAE         0x00000010      /* PCI asynchronous error           */
2284 #define UIC_ETH0        0x00000008      /* Ethernet 0                       */
2285 #define UIC_EWU0        0x00000004      /* Ethernet 0 wakeup                */
2286 #define UIC_ETH1        0x00000002      /* Ethernet 1                       */
2287 #define UIC_EWU1        0x00000001      /* Ethernet 1 wakeup                */
2288
2289 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
2290
2291 #define UIC_EIR2        0x80000000      /* External interrupt 2             */
2292 #define UIC_U0          0x40000000      /* UART 0                           */
2293 #define UIC_SPI         0x20000000      /* SPI                              */
2294 #define UIC_TRNGAL      0x10000000      /* TRNG alarm                       */
2295 #define UIC_DEUE        0x08000000      /* DDR SDRAM ECC correct/uncorrectable error */
2296 #define UIC_EBCO        0x04000000      /* EBCO interrupt status            */
2297 #define UIC_NDFC        0x02000000      /* NDFC                             */
2298 #define UIC_EIPPKPSE    0x01000000      /* EIPPKP slave error               */
2299 #define UIC_P0MSI1      0x00800000      /* PCI0 MSI level 1                 */
2300 #define UIC_P0MSI2      0x00400000      /* PCI0 MSI level 2                 */
2301 #define UIC_P0MSI3      0x00200000      /* PCI0 MSI level 3                 */
2302 #define UIC_L2C         0x00100000      /* L2 cache                         */
2303 #define UIC_CT0         0x00080000      /* GPT compare timer 0              */
2304 #define UIC_CT1         0x00040000      /* GPT compare timer 1              */
2305 #define UIC_CT2         0x00020000      /* GPT compare timer 2              */
2306 #define UIC_CT3         0x00010000      /* GPT compare timer 3              */
2307 #define UIC_CT4         0x00008000      /* GPT compare timer 4              */
2308 #define UIC_CT5         0x00004000      /* GPT compare timer 5              */
2309 #define UIC_CT6         0x00002000      /* GPT compare timer 6              */
2310 #define UIC_GPTDC       0x00001000      /* GPT decrementer pulse            */
2311 #define UIC_EIR3        0x00000800      /* External interrupt 3             */
2312 #define UIC_EIR4        0x00000400      /* External interrupt 4             */
2313 #define UIC_DMAE        0x00000200      /* DMA error                        */
2314 #define UIC_I2OE        0x00000100      /* I2O error                        */
2315 #define UIC_SRE         0x00000080      /* Serial ROM error                 */
2316 #define UIC_P0AE        0x00000040      /* PCI0 asynchronous error          */
2317 #define UIC_EIR5        0x00000020      /* External interrupt 5             */
2318 #define UIC_EIR6        0x00000010      /* External interrupt 6             */
2319 #define UIC_U2          0x00000008      /* UART 2                           */
2320 #define UIC_U3          0x00000004      /* UART 3                           */
2321 #define UIC_EIR7        0x00000002      /* External interrupt 7             */
2322 #define UIC_EIR8        0x00000001      /* External interrupt 8             */
2323
2324 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
2325
2326 #define UIC_MS        0x80000000  /* MAL SERR                           */
2327 #define UIC_MTDE      0x40000000  /* MAL TXDE                           */
2328 #define UIC_MRDE      0x20000000  /* MAL RXDE                           */
2329 #define UIC_U2        0x10000000  /* UART 2                             */
2330 #define UIC_U3        0x08000000  /* UART 3                             */
2331 #define UIC_EBCO      0x04000000  /* EBCO interrupt status              */
2332 #define UIC_NDFC      0x02000000  /* NDFC                               */
2333 #define UIC_KSLE      0x01000000  /* KASUMI slave error                 */
2334 #define UIC_CT5       0x00800000  /* GPT compare timer 5                */
2335 #define UIC_CT6       0x00400000  /* GPT compare timer 6                */
2336 #define UIC_PLB34I0   0x00200000  /* PLB3X4X MIRQ0                      */
2337 #define UIC_PLB34I1   0x00100000  /* PLB3X4X MIRQ1                      */
2338 #define UIC_PLB34I2   0x00080000  /* PLB3X4X MIRQ2                      */
2339 #define UIC_PLB34I3   0x00040000  /* PLB3X4X MIRQ3                      */
2340 #define UIC_PLB34I4   0x00020000  /* PLB3X4X MIRQ4                      */
2341 #define UIC_PLB34I5   0x00010000  /* PLB3X4X MIRQ5                      */
2342 #define UIC_CT0       0x00008000  /* GPT compare timer 0                */
2343 #define UIC_CT1       0x00004000  /* GPT compare timer 1                */
2344 #define UIC_EIR7      0x00002000  /* External interrupt 7               */
2345 #define UIC_EIR8      0x00001000  /* External interrupt 8               */
2346 #define UIC_EIR9      0x00000800  /* External interrupt 9               */
2347 #define UIC_CT2       0x00000400  /* GPT compare timer 2                */
2348 #define UIC_CT3       0x00000200  /* GPT compare timer 3                */
2349 #define UIC_CT4       0x00000100  /* GPT compare timer 4                */
2350 #define UIC_SRE       0x00000080  /* Serial ROM error                   */
2351 #define UIC_GPTDC     0x00000040  /* GPT decrementer pulse              */
2352 #define UIC_RSVD0     0x00000020  /* Reserved                           */
2353 #define UIC_EPCIPER   0x00000010  /* External PCI PERR                  */
2354 #define UIC_EIR0      0x00000008  /* External interrupt 0               */
2355 #define UIC_EWU0      0x00000004  /* Ethernet 0 wakeup                  */
2356 #define UIC_EIR1      0x00000002  /* External interrupt 1               */
2357 #define UIC_EWU1      0x00000001  /* Ethernet 1 wakeup                  */
2358
2359 /* For compatibility with 405 code */
2360 #define UIC_MAL_SERR    UIC_MS
2361 #define UIC_MAL_TXDE    UIC_MTDE
2362 #define UIC_MAL_RXDE    UIC_MRDE
2363 #define UIC_ENET        UIC_ETH0
2364
2365 #elif !defined(CONFIG_440SPE)
2366 #define UIC_MS          0x80000000      /* MAL SERR                         */
2367 #define UIC_MTDE        0x40000000      /* MAL TXDE                         */
2368 #define UIC_MRDE        0x20000000      /* MAL RXDE                         */
2369 #define UIC_DEUE        0x10000000      /* DDR SDRAM ECC uncorrectible error*/
2370 #define UIC_DECE        0x08000000      /* DDR SDRAM correctible error      */
2371 #define UIC_EBCO        0x04000000      /* EBCO interrupt status            */
2372 #define UIC_EBMI        0x02000000      /* EBMI interrupt status            */
2373 #define UIC_OPB         0x01000000      /* OPB to PLB bridge interrupt stat */
2374 #define UIC_MSI3        0x00800000      /* PCI MSI level 3                  */
2375 #define UIC_MSI4        0x00400000      /* PCI MSI level 4                  */
2376 #define UIC_MSI5        0x00200000      /* PCI MSI level 5                  */
2377 #define UIC_MSI6        0x00100000      /* PCI MSI level 6                  */
2378 #define UIC_MSI7        0x00080000      /* PCI MSI level 7                  */
2379 #define UIC_MSI8        0x00040000      /* PCI MSI level 8                  */
2380 #define UIC_MSI9        0x00020000      /* PCI MSI level 9                  */
2381 #define UIC_MSI10       0x00010000      /* PCI MSI level 10                 */
2382 #define UIC_MSI11       0x00008000      /* PCI MSI level 11                 */
2383 #define UIC_PPMI        0x00004000      /* PPM interrupt status             */
2384 #define UIC_EIR7        0x00002000      /* External interrupt 7             */
2385 #define UIC_EIR8        0x00001000      /* External interrupt 8             */
2386 #define UIC_EIR9        0x00000800      /* External interrupt 9             */
2387 #define UIC_EIR10       0x00000400      /* External interrupt 10            */
2388 #define UIC_EIR11       0x00000200      /* External interrupt 11            */
2389 #define UIC_EIR12       0x00000100      /* External interrupt 12            */
2390 #define UIC_SRE         0x00000080      /* Serial ROM error                 */
2391 #define UIC_RSVD2       0x00000040      /* Reserved                         */
2392 #define UIC_RSVD3       0x00000020      /* Reserved                         */
2393 #define UIC_PAE         0x00000010      /* PCI asynchronous error           */
2394 #define UIC_ETH0        0x00000008      /* Ethernet 0                       */
2395 #define UIC_EWU0        0x00000004      /* Ethernet 0 wakeup                */
2396 #define UIC_ETH1        0x00000002      /* Ethernet 1                       */
2397 #define UIC_EWU1        0x00000001      /* Ethernet 1 wakeup                */
2398 #endif /* CONFIG_440SP */
2399
2400 /* For compatibility with 405 code */
2401 #define UIC_MAL_SERR    UIC_MS
2402 #define UIC_MAL_TXDE    UIC_MTDE
2403 #define UIC_MAL_RXDE    UIC_MRDE
2404 #define UIC_ENET        UIC_ETH0
2405
2406 /*---------------------------------------------------------------------------+
2407 |  Universal interrupt controller 2 interrupts (UIC2)
2408 +---------------------------------------------------------------------------*/
2409 #if defined(CONFIG_440GX)
2410 #define UIC_ETH2        0x80000000      /* Ethernet 2                       */
2411 #define UIC_EWU2        0x40000000      /* Ethernet 2 wakeup                */
2412 #define UIC_ETH3        0x20000000      /* Ethernet 3                       */
2413 #define UIC_EWU3        0x10000000      /* Ethernet 3 wakeup                */
2414 #define UIC_TAH0        0x08000000      /* TAH 0                            */
2415 #define UIC_TAH1        0x04000000      /* TAH 1                            */
2416 #define UIC_IMUOBFQ     0x02000000      /* IMU outbound free queue          */
2417 #define UIC_IMUIBPQ     0x01000000      /* IMU inbound post queue           */
2418 #define UIC_IMUIRQDB    0x00800000      /* IMU irq doorbell                 */
2419 #define UIC_IMUIBDB     0x00400000      /* IMU inbound doorbell             */
2420 #define UIC_IMUMSG0     0x00200000      /* IMU inbound message 0            */
2421 #define UIC_IMUMSG1     0x00100000      /* IMU inbound message 1            */
2422 #define UIC_IMUTO       0x00080000      /* IMU timeout                      */
2423 #define UIC_MSI12       0x00040000      /* PCI MSI level 12                 */
2424 #define UIC_MSI13       0x00020000      /* PCI MSI level 13                 */
2425 #define UIC_MSI14       0x00010000      /* PCI MSI level 14                 */
2426 #define UIC_MSI15       0x00008000      /* PCI MSI level 15                 */
2427 #define UIC_EIR13       0x00004000      /* External interrupt 13            */
2428 #define UIC_EIR14       0x00002000      /* External interrupt 14            */
2429 #define UIC_EIR15       0x00001000      /* External interrupt 15            */
2430 #define UIC_EIR16       0x00000800      /* External interrupt 16            */
2431 #define UIC_EIR17       0x00000400      /* External interrupt 17            */
2432 #define UIC_PCIVPD      0x00000200      /* PCI VPD                          */
2433 #define UIC_L2C         0x00000100      /* L2 Cache                         */
2434 #define UIC_ETH2PCS     0x00000080      /* Ethernet 2 PCS                   */
2435 #define UIC_ETH3PCS     0x00000040      /* Ethernet 3 PCS                   */
2436 #define UIC_RSVD26      0x00000020      /* Reserved                         */
2437 #define UIC_RSVD27      0x00000010      /* Reserved                         */
2438 #define UIC_RSVD28      0x00000008      /* Reserved                         */
2439 #define UIC_RSVD29      0x00000004      /* Reserved                         */
2440 #define UIC_RSVD30      0x00000002      /* Reserved                         */
2441 #define UIC_RSVD31      0x00000001      /* Reserved                         */
2442
2443 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
2444
2445 #define UIC_TAH0        0x80000000      /* TAHOE 0                          */
2446 #define UIC_TAH1        0x40000000      /* TAHOE 1                          */
2447 #define UIC_EIR9        0x20000000      /* External interrupt 9             */
2448 #define UIC_MS          0x10000000      /* MAL SERR                         */
2449 #define UIC_MTDE        0x08000000      /* MAL TXDE                         */
2450 #define UIC_MRDE        0x04000000      /* MAL RXDE                         */
2451 #define UIC_MTE         0x02000000      /* MAL TXEOB                        */
2452 #define UIC_MRE         0x01000000      /* MAL RXEOB                        */
2453 #define UIC_MCTX0       0x00800000      /* MAL interrupt coalescence TX0    */
2454 #define UIC_MCTX1       0x00400000      /* MAL interrupt coalescence TX1    */
2455 #define UIC_MCTX2       0x00200000      /* MAL interrupt coalescence TX2    */
2456 #define UIC_MCTX3       0x00100000      /* MAL interrupt coalescence TX3    */
2457 #define UIC_MCTR0       0x00080000      /* MAL interrupt coalescence TR0    */
2458 #define UIC_MCTR1       0x00040000      /* MAL interrupt coalescence TR1    */
2459 #define UIC_MCTR2       0x00020000      /* MAL interrupt coalescence TR2    */
2460 #define UIC_MCTR3       0x00010000      /* MAL interrupt coalescence TR3    */
2461 #define UIC_ETH0        0x00008000      /* Ethernet 0                       */
2462 #define UIC_ETH1        0x00004000      /* Ethernet 1                       */
2463 #define UIC_ETH2        0x00002000      /* Ethernet 2                       */
2464 #define UIC_ETH3        0x00001000      /* Ethernet 3                       */
2465 #define UIC_EWU0        0x00000800      /* Ethernet 0 wakeup                */
2466 #define UIC_EWU1        0x00000400      /* Ethernet 1 wakeup                */
2467 #define UIC_EWU2        0x00000200      /* Ethernet 2 wakeup                */
2468 #define UIC_EWU3        0x00000100      /* Ethernet 3 wakeup                */
2469 #define UIC_EIR10       0x00000080      /* External interrupt 10            */
2470 #define UIC_EIR11       0x00000040      /* External interrupt 11            */
2471 #define UIC_RSVD2       0x00000020      /* Reserved                         */
2472 #define UIC_PLB4XAHB    0x00000010      /* PLB4XAHB / AHBARB error          */
2473 #define UIC_OTG         0x00000008      /* USB2.0 OTG                       */
2474 #define UIC_EHCI        0x00000004      /* USB2.0 Host EHCI                 */
2475 #define UIC_OHCI        0x00000002      /* USB2.0 Host OHCI                 */
2476 #define UIC_OHCISMI     0x00000001      /* USB2.0 Host OHCI SMI             */
2477
2478 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* UIC2 */
2479
2480 #define UIC_EIR5    0x80000000  /* External interrupt 5                 */
2481 #define UIC_EIR6    0x40000000  /* External interrupt 6                 */
2482 #define UIC_OPB     0x20000000  /* OPB to PLB bridge interrupt stat     */
2483 #define UIC_EIR2    0x10000000  /* External interrupt 2                 */
2484 #define UIC_EIR3    0x08000000  /* External interrupt 3                 */
2485 #define UIC_DDR2    0x04000000  /* DDR2 sdram                           */
2486 #define UIC_MCTX0   0x02000000  /* MAl intp coalescence TX0             */
2487 #define UIC_MCTX1   0x01000000  /* MAl intp coalescence TX1             */
2488 #define UIC_MCTR0   0x00800000  /* MAl intp coalescence TR0             */
2489 #define UIC_MCTR1   0x00400000  /* MAl intp coalescence TR1             */
2490
2491 #endif  /* CONFIG_440GX */
2492
2493 /*---------------------------------------------------------------------------+
2494 |  Universal interrupt controller Base 0 interrupts (UICB0)
2495 +---------------------------------------------------------------------------*/
2496 #if defined(CONFIG_440GX)
2497 #define UICB0_UIC0CI    0x80000000      /* UIC0 Critical Interrupt          */
2498 #define UICB0_UIC0NCI   0x40000000      /* UIC0 Noncritical Interrupt       */
2499 #define UICB0_UIC1CI    0x20000000      /* UIC1 Critical Interrupt          */
2500 #define UICB0_UIC1NCI   0x10000000      /* UIC1 Noncritical Interrupt       */
2501 #define UICB0_UIC2CI    0x08000000      /* UIC2 Critical Interrupt          */
2502 #define UICB0_UIC2NCI   0x04000000      /* UIC2 Noncritical Interrupt       */
2503
2504 #define UICB0_ALL       (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
2505                          UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
2506
2507 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
2508
2509 #define UICB0_UIC1NCI   0x00000002      /* UIC1 Noncritical Interrupt       */
2510 #define UICB0_UIC1CI    0x00000001      /* UIC1 Critical Interrupt          */
2511 #define UICB0_UIC2NCI   0x00200000      /* UIC2 Noncritical Interrupt       */
2512 #define UICB0_UIC2CI    0x00100000      /* UIC2 Critical Interrupt          */
2513 #define UICB0_UIC3NCI   0x00008000      /* UIC3 Noncritical Interrupt       */
2514 #define UICB0_UIC3CI    0x00004000      /* UIC3 Critical Interrupt          */
2515
2516 #define UICB0_ALL       (UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \
2517                          UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI)
2518
2519 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
2520
2521 #define UICB0_UIC1CI    0x00000001      /* UIC1 Critical Interrupt          */
2522 #define UICB0_UIC1NCI   0x00000002      /* UIC1 Noncritical Interrupt       */
2523 #define UICB0_UIC2CI    0x00000004      /* UIC2 Critical Interrupt          */
2524 #define UICB0_UIC2NCI   0x00000008      /* UIC2 Noncritical Interrupt       */
2525
2526 #define UICB0_ALL       (UICB0_UIC1CI | UICB0_UIC1NCI | \
2527                          UICB0_UIC1CI | UICB0_UIC2NCI)
2528
2529 #elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
2530     defined(CONFIG_440EP) || defined(CONFIG_440GR)
2531
2532 #define UICB0_UIC1CI    0x00000001      /* UIC1 Critical Interrupt          */
2533 #define UICB0_UIC1NCI   0x00000002      /* UIC1 Noncritical Interrupt       */
2534
2535 #define UICB0_ALL       (UICB0_UIC1CI | UICB0_UIC1NCI)
2536
2537 #endif /* CONFIG_440GX */
2538 /*---------------------------------------------------------------------------+
2539 |  Universal interrupt controller interrupts
2540 +---------------------------------------------------------------------------*/
2541 #if defined(CONFIG_440SPE)
2542 /*#define UICB0_UIC0CI  0x80000000*/    /* UIC0 Critical Interrupt          */
2543 /*#define UICB0_UIC0NCI 0x40000000*/    /* UIC0 Noncritical Interrupt       */
2544 #define UICB0_UIC1CI    0x00000002      /* UIC1 Critical Interrupt          */
2545 #define UICB0_UIC1NCI   0x00000001      /* UIC1 Noncritical Interrupt       */
2546 #define UICB0_UIC2CI    0x00200000      /* UIC2 Critical Interrupt          */
2547 #define UICB0_UIC2NCI   0x00100000      /* UIC2 Noncritical Interrupt       */
2548 #define UICB0_UIC3CI    0x00008000      /* UIC3 Critical Interrupt          */
2549 #define UICB0_UIC3NCI   0x00004000      /* UIC3 Noncritical Interrupt       */
2550
2551 #define UICB0_ALL               (UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \
2552                                                  UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI)
2553 /*---------------------------------------------------------------------------+
2554 |  Universal interrupt controller 0 interrupts (UIC0)
2555 +---------------------------------------------------------------------------*/
2556 #define UIC_U0          0x80000000      /* UART 0                           */
2557 #define UIC_U1          0x40000000      /* UART 1                           */
2558 #define UIC_IIC0        0x20000000      /* IIC                              */
2559 #define UIC_IIC1        0x10000000      /* IIC                              */
2560 #define UIC_PIM         0x08000000      /* PCI inbound message              */
2561 #define UIC_PCRW        0x04000000      /* PCI command register write       */
2562 #define UIC_PPM         0x02000000      /* PCI power management             */
2563 #define UIC_PVPDA       0x01000000      /* PCIx 0 vpd access                */
2564 #define UIC_MSI0        0x00800000      /* PCIx MSI level 0                 */
2565 #define UIC_EIR15       0x00400000      /* External intp 15                 */
2566 #define UIC_PEMSI0      0x00080000      /* PCIe MSI level 0                 */
2567 #define UIC_PEMSI1      0x00040000      /* PCIe MSI level 1                 */
2568 #define UIC_PEMSI2      0x00020000      /* PCIe MSI level 2                 */
2569 #define UIC_PEMSI3      0x00010000      /* PCIe MSI level 3                 */
2570 #define UIC_EIR14       0x00002000      /* External interrupt 14            */
2571 #define UIC_D0CPFF      0x00001000      /* DMA0 cp fifo full                */
2572 #define UIC_D0CSNS      0x00000800      /* DMA0 cs fifo needs service       */
2573 #define UIC_D1CPFF      0x00000400      /* DMA1 cp fifo full                */
2574 #define UIC_D1CSNS      0x00000200      /* DMA1 cs fifo needs service       */
2575 #define UIC_I2OID       0x00000100      /* I2O inbound door bell            */
2576 #define UIC_I2OLNE      0x00000080      /* I2O Inbound Post List FIFO Not Empty */
2577 #define UIC_I20R0LL     0x00000040      /* I2O Region 0 Low Latency PLB Write */
2578 #define UIC_I2OR1LL     0x00000020      /* I2O Region 1 Low Latency PLB Write */
2579 #define UIC_I20R0HB     0x00000010      /* I2O Region 0 High Bandwidth PLB Write */
2580 #define UIC_I2OR1HB     0x00000008      /* I2O Region 1 High Bandwidth PLB Write */
2581 #define UIC_CPTCNT      0x00000004      /* GPT Count Timer                  */
2582 /*---------------------------------------------------------------------------+
2583 |  Universal interrupt controller 1 interrupts (UIC1)
2584 +---------------------------------------------------------------------------*/
2585 #define UIC_EIR13       0x80000000      /* externei intp 13                 */
2586 #define UIC_MS          0x40000000      /* MAL SERR                         */
2587 #define UIC_MTDE        0x20000000      /* MAL TXDE                         */
2588 #define UIC_MRDE        0x10000000      /* MAL RXDE                         */
2589 #define UIC_DEUE        0x08000000      /* DDR SDRAM ECC correct/uncorrectable error */
2590 #define UIC_EBCO        0x04000000      /* EBCO interrupt status            */
2591 #define UIC_MTE         0x02000000      /* MAL TXEOB                        */
2592 #define UIC_MRE         0x01000000      /* MAL RXEOB                        */
2593 #define UIC_MSI1        0x00800000      /* PCI MSI level 1                  */
2594 #define UIC_MSI2        0x00400000      /* PCI MSI level 2                  */
2595 #define UIC_MSI3        0x00200000      /* PCI MSI level 3                  */
2596 #define UIC_L2C         0x00100000      /* L2 cache                         */
2597 #define UIC_CT0         0x00080000      /* GPT compare timer 0              */
2598 #define UIC_CT1         0x00040000      /* GPT compare timer 1              */
2599 #define UIC_CT2         0x00020000      /* GPT compare timer 2              */
2600 #define UIC_CT3         0x00010000      /* GPT compare timer 3              */
2601 #define UIC_CT4         0x00008000      /* GPT compare timer 4              */
2602 #define UIC_EIR12       0x00004000      /* External interrupt 12            */
2603 #define UIC_EIR11       0x00002000      /* External interrupt 11            */
2604 #define UIC_EIR10       0x00001000      /* External interrupt 10            */
2605 #define UIC_EIR9        0x00000800      /* External interrupt 9             */
2606 #define UIC_EIR8        0x00000400      /* External interrupt 8             */
2607 #define UIC_DMAE        0x00000200      /* dma error                        */
2608 #define UIC_I2OE        0x00000100      /* i2o error                        */
2609 #define UIC_SRE         0x00000080      /* Serial ROM error                 */
2610 #define UIC_PCIXAE      0x00000040      /* Pcix0 async error                */
2611 #define UIC_EIR7        0x00000020      /* External interrupt 7             */
2612 #define UIC_EIR6        0x00000010      /* External interrupt 6             */
2613 #define UIC_ETH0        0x00000008      /* Ethernet 0                       */
2614 #define UIC_EWU0        0x00000004      /* Ethernet 0 wakeup                */
2615 #define UIC_ETH1        0x00000002      /* reserved                         */
2616 #define UIC_XOR         0x00000001      /* xor                              */
2617
2618 /*---------------------------------------------------------------------------+
2619 |  Universal interrupt controller 2 interrupts (UIC2)
2620 +---------------------------------------------------------------------------*/
2621 #define UIC_PEOAL       0x80000000      /* PE0  AL                          */
2622 #define UIC_PEOVA       0x40000000      /* PE0  VPD access                  */
2623 #define UIC_PEOHRR      0x20000000      /* PE0 Host reset request rising    */
2624 #define UIC_PE0HRF      0x10000000      /* PE0 Host reset request falling   */
2625 #define UIC_PE0TCR      0x08000000      /* PE0 TCR                          */
2626 #define UIC_PE0BVCO     0x04000000      /* PE0 Busmaster VCO                */
2627 #define UIC_PE0DCRE     0x02000000      /* PE0 DCR error                    */
2628 #define UIC_PE1AL       0x00800000      /* PE1  AL                          */
2629 #define UIC_PE1VA       0x00400000      /* PE1  VPD access                  */
2630 #define UIC_PE1HRR      0x00200000      /* PE1 Host reset request rising    */
2631 #define UIC_PE1HRF      0x00100000      /* PE1 Host reset request falling   */
2632 #define UIC_PE1TCR      0x00080000      /* PE1 TCR                          */
2633 #define UIC_PE1BVCO     0x00040000      /* PE1 Busmaster VCO                */
2634 #define UIC_PE1DCRE     0x00020000      /* PE1 DCR error                    */
2635 #define UIC_PE2AL       0x00008000      /* PE2  AL                          */
2636 #define UIC_PE2VA       0x00004000      /* PE2  VPD access                  */
2637 #define UIC_PE2HRR      0x00002000      /* PE2 Host reset request rising    */
2638 #define UIC_PE2HRF      0x00001000      /* PE2 Host reset request falling   */
2639 #define UIC_PE2TCR      0x00000800      /* PE2 TCR                          */
2640 #define UIC_PE2BVCO     0x00000400      /* PE2 Busmaster VCO                */
2641 #define UIC_PE2DCRE     0x00000200      /* PE2 DCR error                    */
2642 #define UIC_EIR5        0x00000080      /* External interrupt 5             */
2643 #define UIC_EIR4        0x00000040      /* External interrupt 4             */
2644 #define UIC_EIR3        0x00000020      /* External interrupt 3             */
2645 #define UIC_EIR2        0x00000010      /* External interrupt 2             */
2646 #define UIC_EIR1        0x00000008      /* External interrupt 1             */
2647 #define UIC_EIR0        0x00000004      /* External interrupt 0             */
2648 #endif /* CONFIG_440SPE */
2649
2650 /*-----------------------------------------------------------------------------+
2651 |  External Bus Controller Bit Settings
2652 +-----------------------------------------------------------------------------*/
2653 #define EBC_CFGADDR_MASK                0x0000003F
2654
2655 #define EBC_BXCR_BAS_ENCODE(n)  ((((unsigned long)(n))&0xFFF00000)<<0)
2656 #define EBC_BXCR_BS_MASK                0x000E0000
2657 #define EBC_BXCR_BS_1MB                 0x00000000
2658 #define EBC_BXCR_BS_2MB                 0x00020000
2659 #define EBC_BXCR_BS_4MB                 0x00040000
2660 #define EBC_BXCR_BS_8MB                 0x00060000
2661 #define EBC_BXCR_BS_16MB                0x00080000
2662 #define EBC_BXCR_BS_32MB                0x000A0000
2663 #define EBC_BXCR_BS_64MB                0x000C0000
2664 #define EBC_BXCR_BS_128MB               0x000E0000
2665 #define EBC_BXCR_BU_MASK                0x00018000
2666 #define EBC_BXCR_BU_R                   0x00008000
2667 #define EBC_BXCR_BU_W                   0x00010000
2668 #define EBC_BXCR_BU_RW                  0x00018000
2669 #define EBC_BXCR_BW_MASK                0x00006000
2670 #define EBC_BXCR_BW_8BIT                0x00000000
2671 #define EBC_BXCR_BW_16BIT               0x00002000
2672 #define EBC_BXCR_BW_32BIT               0x00006000
2673 #define EBC_BXAP_BME_ENABLED            0x80000000
2674 #define EBC_BXAP_BME_DISABLED           0x00000000
2675 #define EBC_BXAP_TWT_ENCODE(n)          ((((unsigned long)(n))&0xFF)<<23)
2676 #define EBC_BXAP_BCE_DISABLE            0x00000000
2677 #define EBC_BXAP_BCE_ENABLE             0x00400000
2678 #define EBC_BXAP_BCT_MASK               0x00300000
2679 #define EBC_BXAP_BCT_2TRANS             0x00000000
2680 #define EBC_BXAP_BCT_4TRANS             0x00100000
2681 #define EBC_BXAP_BCT_8TRANS             0x00200000
2682 #define EBC_BXAP_BCT_16TRANS            0x00300000
2683 #define EBC_BXAP_CSN_ENCODE(n)          ((((unsigned long)(n))&0x3)<<18)
2684 #define EBC_BXAP_OEN_ENCODE(n)          ((((unsigned long)(n))&0x3)<<16)
2685 #define EBC_BXAP_WBN_ENCODE(n)          ((((unsigned long)(n))&0x3)<<14)
2686 #define EBC_BXAP_WBF_ENCODE(n)          ((((unsigned long)(n))&0x3)<<12)
2687 #define EBC_BXAP_TH_ENCODE(n)           ((((unsigned long)(n))&0x7)<<9)
2688 #define EBC_BXAP_RE_ENABLED             0x00000100
2689 #define EBC_BXAP_RE_DISABLED            0x00000000
2690 #define EBC_BXAP_SOR_DELAYED            0x00000000
2691 #define EBC_BXAP_SOR_NONDELAYED         0x00000080
2692 #define EBC_BXAP_BEM_WRITEONLY          0x00000000
2693 #define EBC_BXAP_BEM_RW                 0x00000040
2694 #define EBC_BXAP_PEN_DISABLED           0x00000000
2695
2696 #define EBC_CFG_LE_MASK                 0x80000000
2697 #define EBC_CFG_LE_UNLOCK               0x00000000
2698 #define EBC_CFG_LE_LOCK                 0x80000000
2699 #define EBC_CFG_PTD_MASK                0x40000000
2700 #define EBC_CFG_PTD_ENABLE              0x00000000
2701 #define EBC_CFG_PTD_DISABLE             0x40000000
2702 #define EBC_CFG_RTC_MASK                0x38000000
2703 #define EBC_CFG_RTC_16PERCLK            0x00000000
2704 #define EBC_CFG_RTC_32PERCLK            0x08000000
2705 #define EBC_CFG_RTC_64PERCLK            0x10000000
2706 #define EBC_CFG_RTC_128PERCLK           0x18000000
2707 #define EBC_CFG_RTC_256PERCLK           0x20000000
2708 #define EBC_CFG_RTC_512PERCLK           0x28000000
2709 #define EBC_CFG_RTC_1024PERCLK          0x30000000
2710 #define EBC_CFG_RTC_2048PERCLK          0x38000000
2711 #define EBC_CFG_ATC_MASK                0x04000000
2712 #define EBC_CFG_ATC_HI                  0x00000000
2713 #define EBC_CFG_ATC_PREVIOUS            0x04000000
2714 #define EBC_CFG_DTC_MASK                0x02000000
2715 #define EBC_CFG_DTC_HI                  0x00000000
2716 #define EBC_CFG_DTC_PREVIOUS            0x02000000
2717 #define EBC_CFG_CTC_MASK                0x01000000
2718 #define EBC_CFG_CTC_HI                  0x00000000
2719 #define EBC_CFG_CTC_PREVIOUS            0x01000000
2720 #define EBC_CFG_OEO_MASK                0x00800000
2721 #define EBC_CFG_OEO_HI                  0x00000000
2722 #define EBC_CFG_OEO_PREVIOUS            0x00800000
2723 #define EBC_CFG_EMC_MASK                0x00400000
2724 #define EBC_CFG_EMC_NONDEFAULT          0x00000000
2725 #define EBC_CFG_EMC_DEFAULT             0x00400000
2726 #define EBC_CFG_PME_MASK                0x00200000
2727 #define EBC_CFG_PME_DISABLE             0x00000000
2728 #define EBC_CFG_PME_ENABLE              0x00200000
2729 #define EBC_CFG_PMT_MASK                0x001F0000
2730 #define EBC_CFG_PMT_ENCODE(n)           ((((unsigned long)(n))&0x1F)<<12)
2731 #define EBC_CFG_PR_MASK                 0x0000C000
2732 #define EBC_CFG_PR_16                   0x00000000
2733 #define EBC_CFG_PR_32                   0x00004000
2734 #define EBC_CFG_PR_64                   0x00008000
2735 #define EBC_CFG_PR_128                  0x0000C000
2736
2737 /*-----------------------------------------------------------------------------+
2738 |  SDR0 Bit Settings
2739 +-----------------------------------------------------------------------------*/
2740 #if defined(CONFIG_440SP)
2741 #define SDR0_SRST                       0x0200
2742
2743 #define SDR0_DDR0                       0x00E1
2744 #define SDR0_DDR0_DPLLRST               0x80000000
2745 #define SDR0_DDR0_DDRM_MASK             0x60000000
2746 #define SDR0_DDR0_DDRM_DDR1             0x20000000
2747 #define SDR0_DDR0_DDRM_DDR2             0x40000000
2748 #define SDR0_DDR0_DDRM_ENCODE(n)        ((((unsigned long)(n))&0x03)<<29)
2749 #define SDR0_DDR0_DDRM_DECODE(n)        ((((unsigned long)(n))>>29)&0x03)
2750 #define SDR0_DDR0_TUNE_ENCODE(n)        ((((unsigned long)(n))&0x2FF)<<0)
2751 #define SDR0_DDR0_TUNE_DECODE(n)        ((((unsigned long)(n))>>0)&0x2FF)
2752 #endif
2753
2754 #if defined(CONFIG_440SPE)
2755 #define SDR0_CP440                      0x0180
2756 #define SDR0_CP440_ERPN_MASK            0x30000000
2757 #define SDR0_CP440_ERPN_MASK_HI         0x3000
2758 #define SDR0_CP440_ERPN_MASK_LO         0x0000
2759 #define SDR0_CP440_ERPN_EBC             0x10000000
2760 #define SDR0_CP440_ERPN_EBC_HI          0x1000
2761 #define SDR0_CP440_ERPN_EBC_LO          0x0000
2762 #define SDR0_CP440_ERPN_PCI             0x20000000
2763 #define SDR0_CP440_ERPN_PCI_HI          0x2000
2764 #define SDR0_CP440_ERPN_PCI_LO          0x0000
2765 #define SDR0_CP440_ERPN_ENCODE(n)       ((((unsigned long)(n))&0x03)<<28)
2766 #define SDR0_CP440_ERPN_DECODE(n)       ((((unsigned long)(n))>>28)&0x03)
2767 #define SDR0_CP440_NTO1_MASK            0x00000002
2768 #define SDR0_CP440_NTO1_NTOP            0x00000000
2769 #define SDR0_CP440_NTO1_NTO1            0x00000002
2770 #define SDR0_CP440_NTO1_ENCODE(n)       ((((unsigned long)(n))&0x01)<<1)
2771 #define SDR0_CP440_NTO1_DECODE(n)       ((((unsigned long)(n))>>1)&0x01)
2772
2773 #define SDR0_SDSTP0                     0x0020
2774 #define SDR0_SDSTP0_ENG_MASK            0x80000000
2775 #define SDR0_SDSTP0_ENG_PLLDIS          0x00000000
2776 #define SDR0_SDSTP0_ENG_PLLENAB         0x80000000
2777 #define SDR0_SDSTP0_ENG_ENCODE(n)       ((((unsigned long)(n))&0x01)<<31)
2778 #define SDR0_SDSTP0_ENG_DECODE(n)       ((((unsigned long)(n))>>31)&0x01)
2779 #define SDR0_SDSTP0_SRC_MASK            0x40000000
2780 #define SDR0_SDSTP0_SRC_PLLOUTA         0x00000000
2781 #define SDR0_SDSTP0_SRC_PLLOUTB         0x40000000
2782 #define SDR0_SDSTP0_SRC_ENCODE(n)       ((((unsigned long)(n))&0x01)<<30)
2783 #define SDR0_SDSTP0_SRC_DECODE(n)       ((((unsigned long)(n))>>30)&0x01)
2784 #define SDR0_SDSTP0_SEL_MASK            0x38000000
2785 #define SDR0_SDSTP0_SEL_PLLOUT          0x00000000
2786 #define SDR0_SDSTP0_SEL_CPU             0x08000000
2787 #define SDR0_SDSTP0_SEL_EBC             0x28000000
2788 #define SDR0_SDSTP0_SEL_ENCODE(n)       ((((unsigned long)(n))&0x07)<<27)
2789 #define SDR0_SDSTP0_SEL_DECODE(n)       ((((unsigned long)(n))>>27)&0x07)
2790 #define SDR0_SDSTP0_TUNE_MASK           0x07FE0000
2791 #define SDR0_SDSTP0_TUNE_ENCODE(n)      ((((unsigned long)(n))&0x3FF)<<17)
2792 #define SDR0_SDSTP0_TUNE_DECODE(n)      ((((unsigned long)(n))>>17)&0x3FF)
2793 #define SDR0_SDSTP0_FBDV_MASK           0x0001F000
2794 #define SDR0_SDSTP0_FBDV_ENCODE(n)      ((((unsigned long)(n))&0x1F)<<12)
2795 #define SDR0_SDSTP0_FBDV_DECODE(n)      ((((((unsigned long)(n))>>12)-1)&0x1F)+1)
2796 #define SDR0_SDSTP0_FWDVA_MASK          0x00000F00
2797 #define SDR0_SDSTP0_FWDVA_ENCODE(n)     ((((unsigned long)(n))&0x0F)<<8)
2798 #define SDR0_SDSTP0_FWDVA_DECODE(n)     ((((((unsigned long)(n))>>8)-1)&0x0F)+1)
2799 #define SDR0_SDSTP0_FWDVB_MASK          0x000000E0
2800 #define SDR0_SDSTP0_FWDVB_ENCODE(n)     ((((unsigned long)(n))&0x07)<<5)
2801 #define SDR0_SDSTP0_FWDVB_DECODE(n)     ((((((unsigned long)(n))>>5)-1)&0x07)+1)
2802 #define SDR0_SDSTP0_PRBDV0_MASK         0x0000001C
2803 #define SDR0_SDSTP0_PRBDV0_ENCODE(n)    ((((unsigned long)(n))&0x07)<<2)
2804 #define SDR0_SDSTP0_PRBDV0_DECODE(n)    ((((((unsigned long)(n))>>2)-1)&0x07)+1)
2805 #define SDR0_SDSTP0_OPBDV0_MASK         0x00000003
2806 #define SDR0_SDSTP0_OPBDV0_ENCODE(n)    ((((unsigned long)(n))&0x03)<<0)
2807 #define SDR0_SDSTP0_OPBDV0_DECODE(n)    ((((((unsigned long)(n))>>0)-1)&0x03)+1)
2808
2809
2810 #define SDR0_SDSTP1                     0x0021
2811 #define SDR0_SDSTP1_LFBDV_MASK          0xFC000000
2812 #define SDR0_SDSTP1_LFBDV_ENCODE(n)     ((((unsigned long)(n))&0x3F)<<26)
2813 #define SDR0_SDSTP1_LFBDV_DECODE(n)     ((((unsigned long)(n))>>26)&0x3F)
2814 #define SDR0_SDSTP1_PERDV0_MASK         0x03000000
2815 #define SDR0_SDSTP1_PERDV0_ENCODE(n)    ((((unsigned long)(n))&0x03)<<24)
2816 #define SDR0_SDSTP1_PERDV0_DECODE(n)    ((((unsigned long)(n))>>24)&0x03)
2817 #define SDR0_SDSTP1_MALDV0_MASK         0x00C00000
2818 #define SDR0_SDSTP1_MALDV0_ENCODE(n)    ((((unsigned long)(n))&0x03)<<22)
2819 #define SDR0_SDSTP1_MALDV0_DECODE(n)    ((((unsigned long)(n))>>22)&0x03)
2820 #define SDR0_SDSTP1_DDR_MODE_MASK       0x00300000
2821 #define SDR0_SDSTP1_DDR1_MODE           0x00100000
2822 #define SDR0_SDSTP1_DDR2_MODE           0x00200000
2823 #define SDR0_SDSTP1_DDR_ENCODE(n)       ((((unsigned long)(n))&0x03)<<20)
2824 #define SDR0_SDSTP1_DDR_DECODE(n)       ((((unsigned long)(n))>>20)&0x03)
2825 #define SDR0_SDSTP1_ERPN_MASK           0x00080000
2826 #define SDR0_SDSTP1_ERPN_EBC            0x00000000
2827 #define SDR0_SDSTP1_ERPN_PCI            0x00080000
2828 #define SDR0_SDSTP1_PAE_MASK            0x00040000
2829 #define SDR0_SDSTP1_PAE_DISABLE         0x00000000
2830 #define SDR0_SDSTP1_PAE_ENABLE          0x00040000
2831 #define SDR0_SDSTP1_PAE_ENCODE(n)       ((((unsigned long)(n))&0x01)<<18)
2832 #define SDR0_SDSTP1_PAE_DECODE(n)       ((((unsigned long)(n))>>18)&0x01)
2833 #define SDR0_SDSTP1_PHCE_MASK           0x00020000
2834 #define SDR0_SDSTP1_PHCE_DISABLE        0x00000000
2835 #define SDR0_SDSTP1_PHCE_ENABLE         0x00020000
2836 #define SDR0_SDSTP1_PHCE_ENCODE(n)      ((((unsigned long)(n))&0x01)<<17)
2837 #define SDR0_SDSTP1_PHCE_DECODE(n)      ((((unsigned long)(n))>>17)&0x01)
2838 #define SDR0_SDSTP1_PISE_MASK           0x00010000
2839 #define SDR0_SDSTP1_PISE_DISABLE        0x00000000
2840 #define SDR0_SDSTP1_PISE_ENABLE         0x00001000
2841 #define SDR0_SDSTP1_PISE_ENCODE(n)      ((((unsigned long)(n))&0x01)<<16)
2842 #define SDR0_SDSTP1_PISE_DECODE(n)      ((((unsigned long)(n))>>16)&0x01)
2843 #define SDR0_SDSTP1_PCWE_MASK           0x00008000
2844 #define SDR0_SDSTP1_PCWE_DISABLE        0x00000000
2845 #define SDR0_SDSTP1_PCWE_ENABLE         0x00008000
2846 #define SDR0_SDSTP1_PCWE_ENCODE(n)      ((((unsigned long)(n))&0x01)<<15)
2847 #define SDR0_SDSTP1_PCWE_DECODE(n)      ((((unsigned long)(n))>>15)&0x01)
2848 #define SDR0_SDSTP1_PPIM_MASK           0x00007800
2849 #define SDR0_SDSTP1_PPIM_ENCODE(n)      ((((unsigned long)(n))&0x0F)<<11)
2850 #define SDR0_SDSTP1_PPIM_DECODE(n)      ((((unsigned long)(n))>>11)&0x0F)
2851 #define SDR0_SDSTP1_PR64E_MASK          0x00000400
2852 #define SDR0_SDSTP1_PR64E_DISABLE       0x00000000
2853 #define SDR0_SDSTP1_PR64E_ENABLE        0x00000400
2854 #define SDR0_SDSTP1_PR64E_ENCODE(n)     ((((unsigned long)(n))&0x01)<<10)
2855 #define SDR0_SDSTP1_PR64E_DECODE(n)     ((((unsigned long)(n))>>10)&0x01)
2856 #define SDR0_SDSTP1_PXFS_MASK           0x00000300
2857 #define SDR0_SDSTP1_PXFS_100_133        0x00000000
2858 #define SDR0_SDSTP1_PXFS_66_100         0x00000100
2859 #define SDR0_SDSTP1_PXFS_50_66          0x00000200
2860 #define SDR0_SDSTP1_PXFS_0_50           0x00000300
2861 #define SDR0_SDSTP1_PXFS_ENCODE(n)      ((((unsigned long)(n))&0x03)<<8)
2862 #define SDR0_SDSTP1_PXFS_DECODE(n)      ((((unsigned long)(n))>>8)&0x03)
2863 #define SDR0_SDSTP1_EBCW_MASK           0x00000080 /* SOP */
2864 #define SDR0_SDSTP1_EBCW_8_BITS         0x00000000 /* SOP */
2865 #define SDR0_SDSTP1_EBCW_16_BITS        0x00000080 /* SOP */
2866 #define SDR0_SDSTP1_DBGEN_MASK          0x00000030 /* $218C */
2867 #define SDR0_SDSTP1_DBGEN_FUNC          0x00000000
2868 #define SDR0_SDSTP1_DBGEN_TRACE         0x00000010
2869 #define SDR0_SDSTP1_DBGEN_ENCODE(n)     ((((unsigned long)(n))&0x03)<<4) /* $218C */
2870 #define SDR0_SDSTP1_DBGEN_DECODE(n)     ((((unsigned long)(n))>>4)&0x03) /* $218C */
2871 #define SDR0_SDSTP1_ETH_MASK            0x00000004
2872 #define SDR0_SDSTP1_ETH_10_100          0x00000000
2873 #define SDR0_SDSTP1_ETH_GIGA            0x00000004
2874 #define SDR0_SDSTP1_ETH_ENCODE(n)       ((((unsigned long)(n))&0x01)<<2)
2875 #define SDR0_SDSTP1_ETH_DECODE(n)       ((((unsigned long)(n))>>2)&0x01)
2876 #define SDR0_SDSTP1_NTO1_MASK           0x00000001
2877 #define SDR0_SDSTP1_NTO1_DISABLE        0x00000000
2878 #define SDR0_SDSTP1_NTO1_ENABLE         0x00000001
2879 #define SDR0_SDSTP1_NTO1_ENCODE(n)      ((((unsigned long)(n))&0x01)<<0)
2880 #define SDR0_SDSTP1_NTO1_DECODE(n)      ((((unsigned long)(n))>>0)&0x01)
2881
2882 #define SDR0_SDSTP2                     0x0022
2883 #define SDR0_SDSTP2_P1AE_MASK           0x80000000
2884 #define SDR0_SDSTP2_P1AE_DISABLE        0x00000000
2885 #define SDR0_SDSTP2_P1AE_ENABLE         0x80000000
2886 #define SDR0_SDSTP2_P1AE_ENCODE(n)      ((((unsigned long)(n))&0x01)<<31)
2887 #define SDR0_SDSTP2_P1AE_DECODE(n)      ((((unsigned long)(n))>>31)&0x01)
2888 #define SDR0_SDSTP2_P1HCE_MASK          0x40000000
2889 #define SDR0_SDSTP2_P1HCE_DISABLE       0x00000000
2890 #define SDR0_SDSTP2_P1HCE_ENABLE        0x40000000
2891 #define SDR0_SDSTP2_P1HCE_ENCODE(n)     ((((unsigned long)(n))&0x01)<<30)
2892 #define SDR0_SDSTP2_P1HCE_DECODE(n)     ((((unsigned long)(n))>>30)&0x01)
2893 #define SDR0_SDSTP2_P1ISE_MASK          0x20000000
2894 #define SDR0_SDSTP2_P1ISE_DISABLE       0x00000000
2895 #define SDR0_SDSTP2_P1ISE_ENABLE        0x20000000
2896 #define SDR0_SDSTP2_P1ISE_ENCODE(n)     ((((unsigned long)(n))&0x01)<<29)
2897 #define SDR0_SDSTP2_P1ISE_DECODE(n)     ((((unsigned long)(n))>>29)&0x01)
2898 #define SDR0_SDSTP2_P1CWE_MASK          0x10000000
2899 #define SDR0_SDSTP2_P1CWE_DISABLE       0x00000000
2900 #define SDR0_SDSTP2_P1CWE_ENABLE        0x10000000
2901 #define SDR0_SDSTP2_P1CWE_ENCODE(n)     ((((unsigned long)(n))&0x01)<<28)
2902 #define SDR0_SDSTP2_P1CWE_DECODE(n)     ((((unsigned long)(n))>>28)&0x01)
2903 #define SDR0_SDSTP2_P1PIM_MASK          0x0F000000
2904 #define SDR0_SDSTP2_P1PIM_ENCODE(n)     ((((unsigned long)(n))&0x0F)<<24)
2905 #define SDR0_SDSTP2_P1PIM_DECODE(n)     ((((unsigned long)(n))>>24)&0x0F)
2906 #define SDR0_SDSTP2_P1R64E_MASK         0x00800000
2907 #define SDR0_SDSTP2_P1R64E_DISABLE      0x00000000
2908 #define SDR0_SDSTP2_P1R64E_ENABLE       0x00800000
2909 #define SDR0_SDSTP2_P1R64E_ENCODE(n)    ((((unsigned long)(n))&0x01)<<23)
2910 #define SDR0_SDSTP2_P1R64E_DECODE(n)    ((((unsigned long)(n))>>23)&0x01)
2911 #define SDR0_SDSTP2_P1XFS_MASK          0x00600000
2912 #define SDR0_SDSTP2_P1XFS_100_133       0x00000000
2913 #define SDR0_SDSTP2_P1XFS_66_100        0x00200000
2914 #define SDR0_SDSTP2_P1XFS_50_66         0x00400000
2915 #define SDR0_SDSTP2_P1XFS_0_50          0x00600000
2916 #define SDR0_SDSTP2_P1XFS_ENCODE(n)     ((((unsigned long)(n))&0x03)<<21)
2917 #define SDR0_SDSTP2_P1XFS_DECODE(n)     ((((unsigned long)(n))>>21)&0x03)
2918 #define SDR0_SDSTP2_P2AE_MASK           0x00040000
2919 #define SDR0_SDSTP2_P2AE_DISABLE        0x00000000
2920 #define SDR0_SDSTP2_P2AE_ENABLE         0x00040000
2921 #define SDR0_SDSTP2_P2AE_ENCODE(n)      ((((unsigned long)(n))&0x01)<<18)
2922 #define SDR0_SDSTP2_P2AE_DECODE(n)      ((((unsigned long)(n))>>18)&0x01)
2923 #define SDR0_SDSTP2_P2HCE_MASK          0x00020000
2924 #define SDR0_SDSTP2_P2HCE_DISABLE       0x00000000
2925 #define SDR0_SDSTP2_P2HCE_ENABLE        0x00020000
2926 #define SDR0_SDSTP2_P2HCE_ENCODE(n)     ((((unsigned long)(n))&0x01)<<17)
2927 #define SDR0_SDSTP2_P2HCE_DECODE(n)     ((((unsigned long)(n))>>17)&0x01)
2928 #define SDR0_SDSTP2_P2ISE_MASK          0x00010000
2929 #define SDR0_SDSTP2_P2ISE_DISABLE       0x00000000
2930 #define SDR0_SDSTP2_P2ISE_ENABLE        0x00010000
2931 #define SDR0_SDSTP2_P2ISE_ENCODE(n)     ((((unsigned long)(n))&0x01)<<16)
2932 #define SDR0_SDSTP2_P2ISE_DECODE(n)     ((((unsigned long)(n))>>16)&0x01)
2933 #define SDR0_SDSTP2_P2CWE_MASK          0x00008000
2934 #define SDR0_SDSTP2_P2CWE_DISABLE       0x00000000
2935 #define SDR0_SDSTP2_P2CWE_ENABLE        0x00008000
2936 #define SDR0_SDSTP2_P2CWE_ENCODE(n)     ((((unsigned long)(n))&0x01)<<15)
2937 #define SDR0_SDSTP2_P2CWE_DECODE(n)     ((((unsigned long)(n))>>15)&0x01)
2938 #define SDR0_SDSTP2_P2PIM_MASK          0x00007800
2939 #define SDR0_SDSTP2_P2PIM_ENCODE(n)     ((((unsigned long)(n))&0x0F)<<11)
2940 #define SDR0_SDSTP2_P2PIM_DECODE(n)     ((((unsigned long)(n))>>11)&0x0F)
2941 #define SDR0_SDSTP2_P2XFS_MASK          0x00000300
2942 #define SDR0_SDSTP2_P2XFS_100_133       0x00000000
2943 #define SDR0_SDSTP2_P2XFS_66_100        0x00000100
2944 #define SDR0_SDSTP2_P2XFS_50_66         0x00000200
2945 #define SDR0_SDSTP2_P2XFS_0_50          0x00000100
2946 #define SDR0_SDSTP2_P2XFS_ENCODE(n)     ((((unsigned long)(n))&0x03)<<8)
2947 #define SDR0_SDSTP2_P2XFS_DECODE(n)     ((((unsigned long)(n))>>8)&0x03)
2948
2949 #define SDR0_SDSTP3                     0x0023
2950
2951 #define SDR0_PINSTP                     0x0040
2952 #define SDR0_PINSTP_BOOTSTRAP_MASK      0xC0000000  /* Strap Bits */
2953 #define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000  /* Default strap settings 0 (EBC boot) */
2954 #define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000  /* Default strap settings 1 (PCI boot) */
2955 #define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000  /* Serial Device Enabled - Addr = 0x54 */
2956 #define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000  /* Serial Device Enabled - Addr = 0x50 */
2957 #define SDR0_SDCS                       0x0060
2958 #define SDR0_ECID0                      0x0080
2959 #define SDR0_ECID1                      0x0081
2960 #define SDR0_ECID2                      0x0082
2961 #define SDR0_JTAG                       0x00C0
2962
2963 #define SDR0_DDR0                       0x00E1
2964 #define SDR0_DDR0_DPLLRST               0x80000000
2965 #define SDR0_DDR0_DDRM_MASK             0x60000000
2966 #define SDR0_DDR0_DDRM_DDR1             0x20000000
2967 #define SDR0_DDR0_DDRM_DDR2             0x40000000
2968 #define SDR0_DDR0_DDRM_ENCODE(n)        ((((unsigned long)(n))&0x03)<<29)
2969 #define SDR0_DDR0_DDRM_DECODE(n)        ((((unsigned long)(n))>>29)&0x03)
2970 #define SDR0_DDR0_TUNE_ENCODE(n)        ((((unsigned long)(n))&0x2FF)<<0)
2971 #define SDR0_DDR0_TUNE_DECODE(n)        ((((unsigned long)(n))>>0)&0x2FF)
2972
2973 #define SDR0_UART0                      0x0120
2974 #define SDR0_UART1                      0x0121
2975 #define SDR0_UART2                      0x0122
2976 #define SDR0_UARTX_UXICS_MASK           0xF0000000
2977 #define SDR0_UARTX_UXICS_PLB            0x20000000
2978 #define SDR0_UARTX_UXEC_MASK            0x00800000
2979 #define SDR0_UARTX_UXEC_INT             0x00000000
2980 #define SDR0_UARTX_UXEC_EXT             0x00800000
2981 #define SDR0_UARTX_UXDIV_MASK           0x000000FF
2982 #define SDR0_UARTX_UXDIV_ENCODE(n)      ((((unsigned long)(n))&0xFF)<<0)
2983 #define SDR0_UARTX_UXDIV_DECODE(n)      ((((((unsigned long)(n))>>0)-1)&0xFF)+1)
2984
2985 #define SDR0_CP440                      0x0180
2986 #define SDR0_CP440_ERPN_MASK            0x30000000
2987 #define SDR0_CP440_ERPN_MASK_HI         0x3000
2988 #define SDR0_CP440_ERPN_MASK_LO         0x0000
2989 #define SDR0_CP440_ERPN_EBC             0x10000000
2990 #define SDR0_CP440_ERPN_EBC_HI          0x1000
2991 #define SDR0_CP440_ERPN_EBC_LO          0x0000
2992 #define SDR0_CP440_ERPN_PCI             0x20000000
2993 #define SDR0_CP440_ERPN_PCI_HI          0x2000
2994 #define SDR0_CP440_ERPN_PCI_LO          0x0000
2995 #define SDR0_CP440_ERPN_ENCODE(n)       ((((unsigned long)(n))&0x03)<<28)
2996 #define SDR0_CP440_ERPN_DECODE(n)       ((((unsigned long)(n))>>28)&0x03)
2997 #define SDR0_CP440_NTO1_MASK            0x00000002
2998 #define SDR0_CP440_NTO1_NTOP            0x00000000
2999 #define SDR0_CP440_NTO1_NTO1            0x00000002
3000 #define SDR0_CP440_NTO1_ENCODE(n)       ((((unsigned long)(n))&0x01)<<1)
3001 #define SDR0_CP440_NTO1_DECODE(n)       ((((unsigned long)(n))>>1)&0x01)
3002
3003 #define SDR0_XCR0                       0x01C0
3004 #define SDR0_XCR1                       0x01C3
3005 #define SDR0_XCR2                       0x01C6
3006 #define SDR0_XCRn_PAE_MASK              0x80000000
3007 #define SDR0_XCRn_PAE_DISABLE           0x00000000
3008 #define SDR0_XCRn_PAE_ENABLE            0x80000000
3009 #define SDR0_XCRn_PAE_ENCODE(n)         ((((unsigned long)(n))&0x01)<<31)
3010 #define SDR0_XCRn_PAE_DECODE(n)         ((((unsigned long)(n))>>31)&0x01)
3011 #define SDR0_XCRn_PHCE_MASK             0x40000000
3012 #define SDR0_XCRn_PHCE_DISABLE          0x00000000
3013 #define SDR0_XCRn_PHCE_ENABLE           0x40000000
3014 #define SDR0_XCRn_PHCE_ENCODE(n)        ((((unsigned long)(n))&0x01)<<30)
3015 #define SDR0_XCRn_PHCE_DECODE(n)        ((((unsigned long)(n))>>30)&0x01)
3016 #define SDR0_XCRn_PISE_MASK             0x20000000
3017 #define SDR0_XCRn_PISE_DISABLE          0x00000000
3018 #define SDR0_XCRn_PISE_ENABLE           0x20000000
3019 #define SDR0_XCRn_PISE_ENCODE(n)        ((((unsigned long)(n))&0x01)<<29)
3020 #define SDR0_XCRn_PISE_DECODE(n)        ((((unsigned long)(n))>>29)&0x01)
3021 #define SDR0_XCRn_PCWE_MASK             0x10000000
3022 #define SDR0_XCRn_PCWE_DISABLE          0x00000000
3023 #define SDR0_XCRn_PCWE_ENABLE           0x10000000
3024 #define SDR0_XCRn_PCWE_ENCODE(n)        ((((unsigned long)(n))&0x01)<<28)
3025 #define SDR0_XCRn_PCWE_DECODE(n)        ((((unsigned long)(n))>>28)&0x01)
3026 #define SDR0_XCRn_PPIM_MASK             0x0F000000
3027 #define SDR0_XCRn_PPIM_ENCODE(n)        ((((unsigned long)(n))&0x0F)<<24)
3028 #define SDR0_XCRn_PPIM_DECODE(n)        ((((unsigned long)(n))>>24)&0x0F)
3029 #define SDR0_XCRn_PR64E_MASK            0x00800000
3030 #define SDR0_XCRn_PR64E_DISABLE         0x00000000
3031 #define SDR0_XCRn_PR64E_ENABLE          0x00800000
3032 #define SDR0_XCRn_PR64E_ENCODE(n)       ((((unsigned long)(n))&0x01)<<23)
3033 #define SDR0_XCRn_PR64E_DECODE(n)       ((((unsigned long)(n))>>23)&0x01)
3034 #define SDR0_XCRn_PXFS_MASK             0x00600000
3035 #define SDR0_XCRn_PXFS_100_133          0x00000000
3036 #define SDR0_XCRn_PXFS_66_100           0x00200000
3037 #define SDR0_XCRn_PXFS_50_66            0x00400000
3038 #define SDR0_XCRn_PXFS_0_33             0x00600000
3039 #define SDR0_XCRn_PXFS_ENCODE(n)        ((((unsigned long)(n))&0x03)<<21)
3040 #define SDR0_XCRn_PXFS_DECODE(n)        ((((unsigned long)(n))>>21)&0x03)
3041
3042 #define SDR0_XPLLC0                     0x01C1
3043 #define SDR0_XPLLD0                     0x01C2
3044 #define SDR0_XPLLC1                     0x01C4
3045 #define SDR0_XPLLD1                     0x01C5
3046 #define SDR0_XPLLC2                     0x01C7
3047 #define SDR0_XPLLD2                     0x01C8
3048 #define SDR0_SRST                       0x0200
3049 #define SDR0_SLPIPE                     0x0220
3050
3051 #define SDR0_AMP0                       0x0240
3052 #define SDR0_AMP0_PRIORITY              0xFFFF0000
3053 #define SDR0_AMP0_ALTERNATE_PRIORITY    0x0000FF00
3054 #define SDR0_AMP0_RESERVED_BITS_MASK    0x000000FF
3055
3056 #define SDR0_AMP1                       0x0241
3057 #define SDR0_AMP1_PRIORITY              0xFC000000
3058 #define SDR0_AMP1_ALTERNATE_PRIORITY    0x0000E000
3059 #define SDR0_AMP1_RESERVED_BITS_MASK    0x03FF1FFF
3060
3061 #define SDR0_MIRQ0                      0x0260
3062 #define SDR0_MIRQ1                      0x0261
3063 #define SDR0_MALTBL                     0x0280
3064 #define SDR0_MALRBL                     0x02A0
3065 #define SDR0_MALTBS                     0x02C0
3066 #define SDR0_MALRBS                     0x02E0
3067
3068 /* Reserved for Customer Use */
3069 #define SDR0_CUST0                      0x4000
3070 #define SDR0_CUST0_AUTONEG_MASK         0x8000000
3071 #define SDR0_CUST0_NO_AUTONEG           0x0000000
3072 #define SDR0_CUST0_AUTONEG              0x8000000
3073 #define SDR0_CUST0_ETH_FORCE_MASK       0x6000000
3074 #define SDR0_CUST0_ETH_FORCE_10MHZ      0x0000000
3075 #define SDR0_CUST0_ETH_FORCE_100MHZ     0x2000000
3076 #define SDR0_CUST0_ETH_FORCE_1000MHZ    0x4000000
3077 #define SDR0_CUST0_ETH_DUPLEX_MASK      0x1000000
3078 #define SDR0_CUST0_ETH_HALF_DUPLEX      0x0000000
3079 #define SDR0_CUST0_ETH_FULL_DUPLEX      0x1000000
3080
3081 #define SDR0_SDSTP4                     0x4001
3082 #define SDR0_CUST1                      0x4002
3083 #define SDR0_SDSTP5                     0x4003
3084 #define SDR0_CUST2                      0x4004
3085 #define SDR0_SDSTP6                     0x4005
3086 #define SDR0_CUST3                      0x4006
3087 #define SDR0_SDSTP7                     0x4007
3088
3089 #define SDR0_PFC0                       0x4100
3090 #define SDR0_PFC0_GPIO_0                0x80000000
3091 #define SDR0_PFC0_PCIX0REQ2_N           0x00000000
3092 #define SDR0_PFC0_GPIO_1                0x40000000
3093 #define SDR0_PFC0_PCIX0REQ3_N           0x00000000
3094 #define SDR0_PFC0_GPIO_2                0x20000000
3095 #define SDR0_PFC0_PCIX0GNT2_N           0x00000000
3096 #define SDR0_PFC0_GPIO_3                0x10000000
3097 #define SDR0_PFC0_PCIX0GNT3_N           0x00000000
3098 #define SDR0_PFC0_GPIO_4                0x08000000
3099 #define SDR0_PFC0_PCIX1REQ2_N           0x00000000
3100 #define SDR0_PFC0_GPIO_5                0x04000000
3101 #define SDR0_PFC0_PCIX1REQ3_N           0x00000000
3102 #define SDR0_PFC0_GPIO_6                0x02000000
3103 #define SDR0_PFC0_PCIX1GNT2_N           0x00000000
3104 #define SDR0_PFC0_GPIO_7                0x01000000
3105 #define SDR0_PFC0_PCIX1GNT3_N           0x00000000
3106 #define SDR0_PFC0_GPIO_8                0x00800000
3107 #define SDR0_PFC0_PERREADY              0x00000000
3108 #define SDR0_PFC0_GPIO_9                0x00400000
3109 #define SDR0_PFC0_PERCS1_N              0x00000000
3110 #define SDR0_PFC0_GPIO_10               0x00200000
3111 #define SDR0_PFC0_PERCS2_N              0x00000000
3112 #define SDR0_PFC0_GPIO_11               0x00100000
3113 #define SDR0_PFC0_IRQ0                  0x00000000
3114 #define SDR0_PFC0_GPIO_12               0x00080000
3115 #define SDR0_PFC0_IRQ1                  0x00000000
3116 #define SDR0_PFC0_GPIO_13               0x00040000
3117 #define SDR0_PFC0_IRQ2                  0x00000000
3118 #define SDR0_PFC0_GPIO_14               0x00020000
3119 #define SDR0_PFC0_IRQ3                  0x00000000
3120 #define SDR0_PFC0_GPIO_15               0x00010000
3121 #define SDR0_PFC0_IRQ4                  0x00000000
3122 #define SDR0_PFC0_GPIO_16               0x00008000
3123 #define SDR0_PFC0_IRQ5                  0x00000000
3124 #define SDR0_PFC0_GPIO_17               0x00004000
3125 #define SDR0_PFC0_PERBE0_N              0x00000000
3126 #define SDR0_PFC0_GPIO_18               0x00002000
3127 #define SDR0_PFC0_PCI0GNT0_N            0x00000000
3128 #define SDR0_PFC0_GPIO_19               0x00001000
3129 #define SDR0_PFC0_PCI0GNT1_N            0x00000000
3130 #define SDR0_PFC0_GPIO_20               0x00000800
3131 #define SDR0_PFC0_PCI0REQ0_N            0x00000000
3132 #define SDR0_PFC0_GPIO_21               0x00000400
3133 #define SDR0_PFC0_PCI0REQ1_N            0x00000000
3134 #define SDR0_PFC0_GPIO_22               0x00000200
3135 #define SDR0_PFC0_PCI1GNT0_N            0x00000000
3136 #define SDR0_PFC0_GPIO_23               0x00000100
3137 #define SDR0_PFC0_PCI1GNT1_N            0x00000000
3138 #define SDR0_PFC0_GPIO_24               0x00000080
3139 #define SDR0_PFC0_PCI1REQ0_N            0x00000000
3140 #define SDR0_PFC0_GPIO_25               0x00000040
3141 #define SDR0_PFC0_PCI1REQ1_N            0x00000000
3142 #define SDR0_PFC0_GPIO_26               0x00000020
3143 #define SDR0_PFC0_PCI2GNT0_N            0x00000000
3144 #define SDR0_PFC0_GPIO_27               0x00000010
3145 #define SDR0_PFC0_PCI2GNT1_N            0x00000000
3146 #define SDR0_PFC0_GPIO_28               0x00000008
3147 #define SDR0_PFC0_PCI2REQ0_N            0x00000000
3148 #define SDR0_PFC0_GPIO_29               0x00000004
3149 #define SDR0_PFC0_PCI2REQ1_N            0x00000000
3150 #define SDR0_PFC0_GPIO_30               0x00000002
3151 #define SDR0_PFC0_UART1RX               0x00000000
3152 #define SDR0_PFC0_GPIO_31               0x00000001
3153 #define SDR0_PFC0_UART1TX               0x00000000
3154
3155 #define SDR0_PFC1                       0x4101
3156 #define SDR0_PFC1_UART1_CTS_RTS_MASK    0x02000000
3157 #define SDR0_PFC1_UART1_DSR_DTR         0x00000000
3158 #define SDR0_PFC1_UART1_CTS_RTS         0x02000000
3159 #define SDR0_PFC1_UART2_IN_SERVICE_MASK 0x01000000
3160 #define SDR0_PFC1_UART2_NOT_IN_SERVICE  0x00000000
3161 #define SDR0_PFC1_UART2_IN_SERVICE      0x01000000
3162 #define SDR0_PFC1_ETH_GIGA_MASK         0x00200000
3163 #define SDR0_PFC1_ETH_10_100            0x00000000
3164 #define SDR0_PFC1_ETH_GIGA              0x00200000
3165 #define SDR0_PFC1_ETH_GIGA_ENCODE(n)    ((((unsigned long)(n))&0x1)<<21)
3166 #define SDR0_PFC1_ETH_GIGA_DECODE(n)    ((((unsigned long)(n))>>21)&0x01)
3167 #define SDR0_PFC1_CPU_TRACE_MASK        0x00180000   /* $218C */
3168 #define SDR0_PFC1_CPU_NO_TRACE          0x00000000
3169 #define SDR0_PFC1_CPU_TRACE             0x00080000
3170 #define SDR0_PFC1_CPU_TRACE_ENCODE(n)   ((((unsigned long)(n))&0x3)<<19)     /* $218C */
3171 #define SDR0_PFC1_CPU_TRACE_DECODE(n)   ((((unsigned long)(n))>>19)&0x03)    /* $218C */
3172
3173 #define SDR0_MFR                        0x4300
3174 #endif  /* CONFIG_440SPE        */
3175
3176 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
3177 /* Pin Function Control Register 0 (SDR0_PFC0) */
3178 #define SDR0_PFC0               0x4100
3179 #define SDR0_PFC0_DBG           0x00008000      /* debug enable */
3180 #define SDR0_PFC0_G49E          0x00004000      /* GPIO 49 enable */
3181 #define SDR0_PFC0_G50E          0x00002000      /* GPIO 50 enable */
3182 #define SDR0_PFC0_G51E          0x00001000      /* GPIO 51 enable */
3183 #define SDR0_PFC0_G52E          0x00000800      /* GPIO 52 enable */
3184 #define SDR0_PFC0_G53E          0x00000400      /* GPIO 53 enable */
3185 #define SDR0_PFC0_G54E          0x00000200      /* GPIO 54 enable */
3186 #define SDR0_PFC0_G55E          0x00000100      /* GPIO 55 enable */
3187 #define SDR0_PFC0_G56E          0x00000080      /* GPIO 56 enable */
3188 #define SDR0_PFC0_G57E          0x00000040      /* GPIO 57 enable */
3189 #define SDR0_PFC0_G58E          0x00000020      /* GPIO 58 enable */
3190 #define SDR0_PFC0_G59E          0x00000010      /* GPIO 59 enable */
3191 #define SDR0_PFC0_G60E          0x00000008      /* GPIO 60 enable */
3192 #define SDR0_PFC0_G61E          0x00000004      /* GPIO 61 enable */
3193 #define SDR0_PFC0_G62E          0x00000002      /* GPIO 62 enable */
3194 #define SDR0_PFC0_G63E          0x00000001      /* GPIO 63 enable */
3195
3196 /* Pin Function Control Register 1 (SDR0_PFC1) */
3197 #define SDR0_PFC1               0x4101
3198 #define SDR0_PFC1_U1ME_MASK     0x02000000      /* UART1 Mode Enable */
3199 #define SDR0_PFC1_U1ME_DSR_DTR  0x00000000      /* UART1 in DSR/DTR Mode */
3200 #define SDR0_PFC1_U1ME_CTS_RTS  0x02000000      /* UART1 in CTS/RTS Mode */
3201 #define SDR0_PFC1_U0ME_MASK     0x00080000      /* UART0 Mode Enable */
3202 #define SDR0_PFC1_U0ME_DSR_DTR  0x00000000      /* UART0 in DSR/DTR Mode */
3203 #define SDR0_PFC1_U0ME_CTS_RTS  0x00080000      /* UART0 in CTS/RTS Mode */
3204 #define SDR0_PFC1_U0IM_MASK     0x00040000      /* UART0 Interface Mode */
3205 #define SDR0_PFC1_U0IM_8PINS    0x00000000      /* UART0 Interface Mode 8 pins*/
3206 #define SDR0_PFC1_U0IM_4PINS    0x00040000      /* UART0 Interface Mode 4 pins*/
3207 #define SDR0_PFC1_SIS_MASK      0x00020000      /* SCP or IIC1 Selection */
3208 #define SDR0_PFC1_SIS_SCP_SEL   0x00000000      /* SCP Selected */
3209 #define SDR0_PFC1_SIS_IIC1_SEL  0x00020000      /* IIC1 Selected */
3210
3211 /* Ethernet PLL Configuration Register (SDR0_ETH_PLL) */
3212 #define SDR0_ETH_PLL            0x4102
3213 #define SDR0_ETH_PLL_PLLLOCK     0x80000000     /*Ethernet PLL lock indication*/
3214 #define SDR0_ETH_PLL_REF_CLK_SEL 0x10000000     /* Ethernet reference clock */
3215 #define SDR0_ETH_PLL_BYPASS      0x08000000     /* bypass mode enable */
3216 #define SDR0_ETH_PLL_STOPCLK     0x04000000     /* output clock disable */
3217 #define SDR0_ETH_PLL_TUNE_MASK   0x03FF0000     /* loop stability tuning bits */
3218 #define SDR0_ETH_PLL_TUNE_ENCODE(n)     ((((unsigned long)(n))&0x3ff)<<16)
3219 #define SDR0_ETH_PLL_MULTI_MASK  0x0000FF00     /* frequency multiplication */
3220 #define SDR0_ETH_PLL_MULTI_ENCODE(n)    ((((unsigned long)(n))&0xff)<<8)
3221 #define SDR0_ETH_PLL_RANGEB_MASK 0x000000F0     /* PLLOUTB/C frequency */
3222 #define SDR0_ETH_PLL_RANGEB_ENCODE(n)   ((((unsigned long)(n))&0x0f)<<4)
3223 #define SDR0_ETH_PLL_RANGEA_MASK 0x0000000F     /* PLLOUTA frequency */
3224 #define SDR0_ETH_PLL_RANGEA_ENCODE(n)   (((unsigned long)(n))&0x0f)
3225
3226 /* Ethernet Configuration Register (SDR0_ETH_CFG) */
3227 #define SDR0_ETH_CFG            0x4103
3228 #define SDR0_ETH_CFG_SGMII3_LPBK        0x00800000      /* SGMII3 port loopback enable */
3229 #define SDR0_ETH_CFG_SGMII2_LPBK        0x00400000      /* SGMII2 port loopback enable */
3230 #define SDR0_ETH_CFG_SGMII1_LPBK        0x00200000      /* SGMII1 port loopback enable */
3231 #define SDR0_ETH_CFG_SGMII0_LPBK        0x00100000      /* SGMII0 port loopback enable */
3232 #define SDR0_ETH_CFG_SGMII_MASK         0x00070000      /* SGMII Mask */
3233 #define SDR0_ETH_CFG_SGMII2_ENABLE      0x00040000      /* SGMII2 port enable */
3234 #define SDR0_ETH_CFG_SGMII1_ENABLE      0x00020000      /* SGMII1 port enable */
3235 #define SDR0_ETH_CFG_SGMII0_ENABLE      0x00010000      /* SGMII0 port enable */
3236 #define SDR0_ETH_CFG_TAHOE1_BYPASS      0x00002000      /* TAHOE1 Bypass selector */
3237 #define SDR0_ETH_CFG_TAHOE0_BYPASS      0x00001000      /* TAHOE0 Bypass selector */
3238 #define SDR0_ETH_CFG_EMAC3_PHY_CLK_SEL  0x00000800      /* EMAC 3 PHY clock selector */
3239 #define SDR0_ETH_CFG_EMAC2_PHY_CLK_SEL  0x00000400      /* EMAC 2 PHY clock selector */
3240 #define SDR0_ETH_CFG_EMAC1_PHY_CLK_SEL  0x00000200      /* EMAC 1 PHY clock selector */
3241 #define SDR0_ETH_CFG_EMAC0_PHY_CLK_SEL  0x00000100      /* EMAC 0 PHY clock selector */
3242 #define SDR0_ETH_CFG_EMAC_2_1_SWAP      0x00000080      /* Swap EMAC2 with EMAC1 */
3243 #define SDR0_ETH_CFG_EMAC_0_3_SWAP      0x00000040      /* Swap EMAC0 with EMAC3 */
3244 #define SDR0_ETH_CFG_MDIO_SEL_MASK      0x00000030      /* MDIO source selector mask */
3245 #define SDR0_ETH_CFG_MDIO_SEL_EMAC0     0x00000000      /* MDIO source - EMAC0 */
3246 #define SDR0_ETH_CFG_MDIO_SEL_EMAC1     0x00000010      /* MDIO source - EMAC1 */
3247 #define SDR0_ETH_CFG_MDIO_SEL_EMAC2     0x00000020      /* MDIO source - EMAC2 */
3248 #define SDR0_ETH_CFG_MDIO_SEL_EMAC3     0x00000030      /* MDIO source - EMAC3 */
3249 #define SDR0_ETH_CFG_ZMII_MODE_MASK     0x0000000C      /* ZMII bridge mode selector mask */
3250 #define SDR0_ETH_CFG_ZMII_SEL_MII       0x00000000      /* ZMII bridge mode - MII */
3251 #define SDR0_ETH_CFG_ZMII_SEL_SMII      0x00000004      /* ZMII bridge mode - SMII */
3252 #define SDR0_ETH_CFG_ZMII_SEL_RMII_10   0x00000008      /* ZMII bridge mode - RMII (10 Mbps) */
3253 #define SDR0_ETH_CFG_ZMII_SEL_RMII_100  0x0000000C      /* ZMII bridge mode - RMII (100 Mbps) */
3254 #define SDR0_ETH_CFG_GMC1_BRIDGE_SEL    0x00000002      /* GMC Port 1 bridge selector */
3255 #define SDR0_ETH_CFG_GMC0_BRIDGE_SEL    0x00000001      /* GMC Port 0 bridge selector */
3256
3257 #define SDR0_ETH_CFG_ZMII_MODE_SHIFT            4
3258 #define SDR0_ETH_CFG_ZMII_MII_MODE              0x00
3259 #define SDR0_ETH_CFG_ZMII_SMII_MODE             0x01
3260 #define SDR0_ETH_CFG_ZMII_RMII_MODE_10M         0x10
3261 #define SDR0_ETH_CFG_ZMII_RMII_MODE_100M        0x11
3262
3263 /* Miscealleneaous Function Reg. (SDR0_MFR) */
3264 #define SDR0_MFR                0x4300
3265 #define SDR0_MFR_T0TxFL         0x00800000      /* force parity error TAHOE0 Tx FIFO bits 0:63 */
3266 #define SDR0_MFR_T0TxFH         0x00400000      /* force parity error TAHOE0 Tx FIFO bits 64:127 */
3267 #define SDR0_MFR_T1TxFL         0x00200000      /* force parity error TAHOE1 Tx FIFO bits 0:63 */
3268 #define SDR0_MFR_T1TxFH         0x00100000      /* force parity error TAHOE1 Tx FIFO bits 64:127 */
3269 #define SDR0_MFR_E0TxFL         0x00008000      /* force parity error EMAC0 Tx FIFO bits 0:63 */
3270 #define SDR0_MFR_E0TxFH         0x00004000      /* force parity error EMAC0 Tx FIFO bits 64:127 */
3271 #define SDR0_MFR_E0RxFL         0x00002000      /* force parity error EMAC0 Rx FIFO bits 0:63 */
3272 #define SDR0_MFR_E0RxFH         0x00001000      /* force parity error EMAC0 Rx FIFO bits 64:127 */
3273 #define SDR0_MFR_E1TxFL         0x00000800      /* force parity error EMAC1 Tx FIFO bits 0:63 */
3274 #define SDR0_MFR_E1TxFH         0x00000400      /* force parity error EMAC1 Tx FIFO bits 64:127 */
3275 #define SDR0_MFR_E1RxFL         0x00000200      /* force parity error EMAC1 Rx FIFO bits 0:63 */
3276 #define SDR0_MFR_E1RxFH         0x00000100      /* force parity error EMAC1 Rx FIFO bits 64:127 */
3277 #define SDR0_MFR_E2TxFL         0x00000080      /* force parity error EMAC2 Tx FIFO bits 0:63 */
3278 #define SDR0_MFR_E2TxFH         0x00000040      /* force parity error EMAC2 Tx FIFO bits 64:127 */
3279 #define SDR0_MFR_E2RxFL         0x00000020      /* force parity error EMAC2 Rx FIFO bits 0:63 */
3280 #define SDR0_MFR_E2RxFH         0x00000010      /* force parity error EMAC2 Rx FIFO bits 64:127 */
3281 #define SDR0_MFR_E3TxFL         0x00000008      /* force parity error EMAC3 Tx FIFO bits 0:63 */
3282 #define SDR0_MFR_E3TxFH         0x00000004      /* force parity error EMAC3 Tx FIFO bits 64:127 */
3283 #define SDR0_MFR_E3RxFL         0x00000002      /* force parity error EMAC3 Rx FIFO bits 0:63 */
3284 #define SDR0_MFR_E3RxFH         0x00000001      /* force parity error EMAC3 Rx FIFO bits 64:127 */
3285
3286 /* EMACx TX Status Register (SDR0_EMACxTXST)*/
3287 #define SDR0_EMAC0TXST          0x4400
3288 #define SDR0_EMAC1TXST          0x4401
3289 #define SDR0_EMAC2TXST          0x4402
3290 #define SDR0_EMAC3TXST          0x4403
3291
3292 #define SDR0_EMACxTXST_FUR      0x02000000      /* TX FIFO underrun */
3293 #define SDR0_EMACxTXST_BC       0x01000000      /* broadcase address */
3294 #define SDR0_EMACxTXST_MC       0x00800000      /* multicast address */
3295 #define SDR0_EMACxTXST_UC       0x00400000      /* unicast address */
3296 #define SDR0_EMACxTXST_FP       0x00200000      /* frame paused by control packet */
3297 #define SDR0_EMACxTXST_BFCS     0x00100000      /* bad FCS in the transmitted frame */
3298 #define SDR0_EMACxTXST_CPF      0x00080000      /* TX control pause frame */
3299 #define SDR0_EMACxTXST_CF       0x00040000      /* TX control frame */
3300 #define SDR0_EMACxTXST_MSIZ     0x00020000      /* 1024-maxsize bytes transmitted */
3301 #define SDR0_EMACxTXST_1023     0x00010000      /* 512-1023 bytes transmitted */
3302 #define SDR0_EMACxTXST_511      0x00008000      /* 256-511 bytes transmitted */
3303 #define SDR0_EMACxTXST_255      0x00004000      /* 128-255 bytes transmitted */
3304 #define SDR0_EMACxTXST_127      0x00002000      /* 65-127 bytes transmitted */
3305 #define SDR0_EMACxTXST_64       0x00001000      /* 64 bytes transmitted */
3306 #define SDR0_EMACxTXST_SQE      0x00000800      /* SQE indication */
3307 #define SDR0_EMACxTXST_LOC      0x00000400      /* loss of carrier sense */
3308 #define SDR0_EMACxTXST_IERR     0x00000080      /* EMAC internal error */
3309 #define SDR0_EMACxTXST_EDF      0x00000040      /* excessive deferral */
3310 #define SDR0_EMACxTXST_ECOL     0x00000020      /* excessive collisions */
3311 #define SDR0_EMACxTXST_LCOL     0x00000010      /* late collision */
3312 #define SDR0_EMACxTXST_DFFR     0x00000008      /* deferred frame */
3313 #define SDR0_EMACxTXST_MCOL     0x00000004      /* multiple collision frame */
3314 #define SDR0_EMACxTXST_SCOL     0x00000002      /* single collision frame */
3315 #define SDR0_EMACxTXST_TXOK     0x00000001      /* transmit OK */
3316
3317 /* EMACx RX Status Register (SDR0_EMACxRXST)*/
3318 #define SDR0_EMAC0RXST          0x4404
3319 #define SDR0_EMAC1RXST          0x4405
3320 #define SDR0_EMAC2RXST          0x4406
3321 #define SDR0_EMAC3RXST          0x4407
3322
3323 #define SDR0_EMACxRXST_FOR      0x20000000      /* RX FIFO overrun */
3324 #define SDR0_EMACxRXST_BC       0x10000000      /* broadcast address */
3325 #define SDR0_EMACxRXST_MC       0x08000000      /* multicast address */
3326 #define SDR0_EMACxRXST_UC       0x04000000      /* unicast address */
3327 #define SDR0_EMACxRXST_UPR_MASK 0x03800000      /* user priority field */
3328 #define SDR0_EMACxRXST_UPR_ENCODE(n)    ((((unsigned long)(n))&0x07)<<23)
3329 #define SDR0_EMACxRXST_VLAN     0x00400000      /* RX VLAN tagged frame */
3330 #define SDR0_EMACxRXST_LOOP     0x00200000      /* received in loop-back mode */
3331 #define SDR0_EMACxRXST_UOP      0x00100000      /* RX unsupported opcode */
3332 #define SDR0_EMACxRXST_CPF      0x00080000      /* RX control pause frame */
3333 #define SDR0_EMACxRXST_CF       0x00040000      /* RX control frame*/
3334 #define SDR0_EMACxRXST_MSIZ     0x00020000      /* 1024-MaxSize bytes recieved*/
3335 #define SDR0_EMACxRXST_1023     0x00010000      /* 512-1023 bytes received */
3336 #define SDR0_EMACxRXST_511      0x00008000      /* 128-511 bytes received */
3337 #define SDR0_EMACxRXST_255      0x00004000      /* 128-255 bytes received */
3338 #define SDR0_EMACxRXST_127      0x00002000      /* 65-127 bytes received */
3339 #define SDR0_EMACxRXST_64       0x00001000      /* 64 bytes received */
3340 #define SDR0_EMACxRXST_RUNT     0x00000800      /* runt frame */
3341 #define SDR0_EMACxRXST_SEVT     0x00000400      /* short event */
3342 #define SDR0_EMACxRXST_AERR     0x00000200      /* alignment error */
3343 #define SDR0_EMACxRXST_SERR     0x00000100      /* received with symbol error */
3344 #define SDR0_EMACxRXST_BURST    0x00000040      /* received burst */
3345 #define SDR0_EMACxRXST_F2L      0x00000020      /* frame is to long */
3346 #define SDR0_EMACxRXST_OERR     0x00000010      /* out of range length error */
3347 #define SDR0_EMACxRXST_IERR     0x00000008      /* in range length error */
3348 #define SDR0_EMACxRXST_LOST     0x00000004      /* frame lost due to internal EMAC receive error */
3349 #define SDR0_EMACxRXST_BFCS     0x00000002      /* bad FCS in the recieved frame */
3350 #define SDR0_EMACxRXST_RXOK     0x00000001      /* Recieve OK */
3351
3352 /* EMACx TX Status Register (SDR0_EMACxREJCNT)*/
3353 #define SDR0_EMAC0REJCNT        0x4408
3354 #define SDR0_EMAC1REJCNT        0x4409
3355 #define SDR0_EMAC2REJCNT        0x440A
3356 #define SDR0_EMAC3REJCNT        0x440B
3357
3358 #define SDR0_DDR0                       0x00E1
3359 #define SDR0_DDR0_DPLLRST               0x80000000
3360 #define SDR0_DDR0_DDRM_MASK             0x60000000
3361 #define SDR0_DDR0_DDRM_DDR1             0x20000000
3362 #define SDR0_DDR0_DDRM_DDR2             0x40000000
3363 #define SDR0_DDR0_DDRM_ENCODE(n)        ((((unsigned long)(n))&0x03)<<29)
3364 #define SDR0_DDR0_DDRM_DECODE(n)        ((((unsigned long)(n))>>29)&0x03)
3365 #define SDR0_DDR0_TUNE_ENCODE(n)        ((((unsigned long)(n))&0x2FF)<<0)
3366 #define SDR0_DDR0_TUNE_DECODE(n)        ((((unsigned long)(n))>>0)&0x2FF)
3367
3368 #define AHB_TOP                 0xA4
3369 #define AHB_BOT                 0xA5
3370 #endif /* CONFIG_460EX || CONFIG_460GT */
3371
3372 #define SDR0_SDCS_SDD                   (0x80000000 >> 31)
3373
3374 #if defined(CONFIG_440GP)
3375 #define CPC0_STRP1_PAE_MASK             (0x80000000 >> 11)
3376 #define CPC0_STRP1_PISE_MASK            (0x80000000 >> 13)
3377 #endif /* defined(CONFIG_440GP) */
3378 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
3379 #define SDR0_SDSTP1_PAE_MASK            (0x80000000 >> 13)
3380 #define SDR0_SDSTP1_PISE_MASK           (0x80000000 >> 15)
3381 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
3382 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
3383     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
3384 #define SDR0_SDSTP1_PAE_MASK            (0x80000000 >> 21)
3385 #define SDR0_SDSTP1_PAME_MASK           (0x80000000 >> 27)
3386 #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
3387
3388 #define SDR0_UARTX_UXICS_MASK           0xF0000000
3389 #define SDR0_UARTX_UXICS_PLB            0x20000000
3390 #define SDR0_UARTX_UXEC_MASK            0x00800000
3391 #define SDR0_UARTX_UXEC_INT             0x00000000
3392 #define SDR0_UARTX_UXEC_EXT             0x00800000
3393 #define SDR0_UARTX_UXDTE_MASK           0x00400000
3394 #define SDR0_UARTX_UXDTE_DISABLE        0x00000000
3395 #define SDR0_UARTX_UXDTE_ENABLE         0x00400000
3396 #define SDR0_UARTX_UXDRE_MASK           0x00200000
3397 #define SDR0_UARTX_UXDRE_DISABLE        0x00000000
3398 #define SDR0_UARTX_UXDRE_ENABLE         0x00200000
3399 #define SDR0_UARTX_UXDC_MASK            0x00100000
3400 #define SDR0_UARTX_UXDC_NOTCLEARED      0x00000000
3401 #define SDR0_UARTX_UXDC_CLEARED         0x00100000
3402 #define SDR0_UARTX_UXDIV_MASK           0x000000FF
3403 #define SDR0_UARTX_UXDIV_ENCODE(n)      ((((unsigned long)(n))&0xFF)<<0)
3404 #define SDR0_UARTX_UXDIV_DECODE(n)      ((((((unsigned long)(n))>>0)-1)&0xFF)+1)
3405
3406 #define SDR0_CPU440_EARV_MASK           0x30000000
3407 #define SDR0_CPU440_EARV_EBC            0x10000000
3408 #define SDR0_CPU440_EARV_PCI            0x20000000
3409 #define SDR0_CPU440_EARV_ENCODE(n)      ((((unsigned long)(n))&0x03)<<28)
3410 #define SDR0_CPU440_EARV_DECODE(n)      ((((unsigned long)(n))>>28)&0x03)
3411 #define SDR0_CPU440_NTO1_MASK           0x00000002
3412 #define SDR0_CPU440_NTO1_NTOP           0x00000000
3413 #define SDR0_CPU440_NTO1_NTO1           0x00000002
3414 #define SDR0_CPU440_NTO1_ENCODE(n)      ((((unsigned long)(n))&0x01)<<1)
3415 #define SDR0_CPU440_NTO1_DECODE(n)      ((((unsigned long)(n))>>1)&0x01)
3416
3417 #define SDR0_XCR_PAE_MASK               0x80000000
3418 #define SDR0_XCR_PAE_DISABLE            0x00000000
3419 #define SDR0_XCR_PAE_ENABLE             0x80000000
3420 #define SDR0_XCR_PAE_ENCODE(n)          ((((unsigned long)(n))&0x01)<<31)
3421 #define SDR0_XCR_PAE_DECODE(n)          ((((unsigned long)(n))>>31)&0x01)
3422 #define SDR0_XCR_PHCE_MASK              0x40000000
3423 #define SDR0_XCR_PHCE_DISABLE           0x00000000
3424 #define SDR0_XCR_PHCE_ENABLE            0x40000000
3425 #define SDR0_XCR_PHCE_ENCODE(n)         ((((unsigned long)(n))&0x01)<<30)
3426 #define SDR0_XCR_PHCE_DECODE(n)         ((((unsigned long)(n))>>30)&0x01)
3427 #define SDR0_XCR_PISE_MASK              0x20000000
3428 #define SDR0_XCR_PISE_DISABLE           0x00000000
3429 #define SDR0_XCR_PISE_ENABLE            0x20000000
3430 #define SDR0_XCR_PISE_ENCODE(n)         ((((unsigned long)(n))&0x01)<<29)
3431 #define SDR0_XCR_PISE_DECODE(n)         ((((unsigned long)(n))>>29)&0x01)
3432 #define SDR0_XCR_PCWE_MASK              0x10000000
3433 #define SDR0_XCR_PCWE_DISABLE           0x00000000
3434 #define SDR0_XCR_PCWE_ENABLE            0x10000000
3435 #define SDR0_XCR_PCWE_ENCODE(n)         ((((unsigned long)(n))&0x01)<<28)
3436 #define SDR0_XCR_PCWE_DECODE(n)         ((((unsigned long)(n))>>28)&0x01)
3437 #define SDR0_XCR_PPIM_MASK              0x0F000000
3438 #define SDR0_XCR_PPIM_ENCODE(n)         ((((unsigned long)(n))&0x0F)<<24)
3439 #define SDR0_XCR_PPIM_DECODE(n)         ((((unsigned long)(n))>>24)&0x0F)
3440 #define SDR0_XCR_PR64E_MASK             0x00800000
3441 #define SDR0_XCR_PR64E_DISABLE          0x00000000
3442 #define SDR0_XCR_PR64E_ENABLE           0x00800000
3443 #define SDR0_XCR_PR64E_ENCODE(n)        ((((unsigned long)(n))&0x01)<<23)
3444 #define SDR0_XCR_PR64E_DECODE(n)        ((((unsigned long)(n))>>23)&0x01)
3445 #define SDR0_XCR_PXFS_MASK              0x00600000
3446 #define SDR0_XCR_PXFS_HIGH              0x00000000
3447 #define SDR0_XCR_PXFS_MED               0x00200000
3448 #define SDR0_XCR_PXFS_LOW               0x00400000
3449 #define SDR0_XCR_PXFS_ENCODE(n)         ((((unsigned long)(n))&0x03)<<21)
3450 #define SDR0_XCR_PXFS_DECODE(n)         ((((unsigned long)(n))>>21)&0x03)
3451 #define SDR0_XCR_PDM_MASK               0x00000040
3452 #define SDR0_XCR_PDM_MULTIPOINT         0x00000000
3453 #define SDR0_XCR_PDM_P2P                0x00000040
3454 #define SDR0_XCR_PDM_ENCODE(n)          ((((unsigned long)(n))&0x01)<<19)
3455 #define SDR0_XCR_PDM_DECODE(n)          ((((unsigned long)(n))>>19)&0x01)
3456
3457 #define SDR0_PFC0_UART1_DSR_CTS_EN_MASK 0x00030000
3458 #define SDR0_PFC0_GEIE_MASK             0x00003E00
3459 #define SDR0_PFC0_GEIE_TRE              0x00003E00
3460 #define SDR0_PFC0_GEIE_NOTRE            0x00000000
3461 #define SDR0_PFC0_TRE_MASK              0x00000100
3462 #define SDR0_PFC0_TRE_DISABLE           0x00000000
3463 #define SDR0_PFC0_TRE_ENABLE            0x00000100
3464 #define SDR0_PFC0_TRE_ENCODE(n)         ((((unsigned long)(n))&0x01)<<8)
3465 #define SDR0_PFC0_TRE_DECODE(n)         ((((unsigned long)(n))>>8)&0x01)
3466
3467 #define SDR0_PFC1_UART1_DSR_CTS_MASK    0x02000000
3468 #define SDR0_PFC1_EPS_MASK              0x01C00000
3469 #define SDR0_PFC1_EPS_GROUP0            0x00000000
3470 #define SDR0_PFC1_EPS_GROUP1            0x00400000
3471 #define SDR0_PFC1_EPS_GROUP2            0x00800000
3472 #define SDR0_PFC1_EPS_GROUP3            0x00C00000
3473 #define SDR0_PFC1_EPS_GROUP4            0x01000000
3474 #define SDR0_PFC1_EPS_GROUP5            0x01400000
3475 #define SDR0_PFC1_EPS_GROUP6            0x01800000
3476 #define SDR0_PFC1_EPS_GROUP7            0x01C00000
3477 #define SDR0_PFC1_EPS_ENCODE(n)         ((((unsigned long)(n))&0x07)<<22)
3478 #define SDR0_PFC1_EPS_DECODE(n)         ((((unsigned long)(n))>>22)&0x07)
3479 #define SDR0_PFC1_RMII_MASK             0x00200000
3480 #define SDR0_PFC1_RMII_100MBIT          0x00000000
3481 #define SDR0_PFC1_RMII_10MBIT           0x00200000
3482 #define SDR0_PFC1_RMII_ENCODE(n)        ((((unsigned long)(n))&0x01)<<21)
3483 #define SDR0_PFC1_RMII_DECODE(n)        ((((unsigned long)(n))>>21)&0x01)
3484 #define SDR0_PFC1_CTEMS_MASK            0x00100000
3485 #define SDR0_PFC1_CTEMS_EMS             0x00000000
3486 #define SDR0_PFC1_CTEMS_CPUTRACE        0x00100000
3487
3488 #define SDR0_MFR_TAH0_MASK              0x80000000
3489 #define SDR0_MFR_TAH0_ENABLE            0x00000000
3490 #define SDR0_MFR_TAH0_DISABLE           0x80000000
3491 #define SDR0_MFR_TAH1_MASK              0x40000000
3492 #define SDR0_MFR_TAH1_ENABLE            0x00000000
3493 #define SDR0_MFR_TAH1_DISABLE           0x40000000
3494 #define SDR0_MFR_PCM_MASK               0x20000000
3495 #define SDR0_MFR_PCM_PPC440GX           0x00000000
3496 #define SDR0_MFR_PCM_PPC440GP           0x20000000
3497 #define SDR0_MFR_ECS_MASK               0x10000000
3498 #define SDR0_MFR_ECS_INTERNAL           0x10000000
3499
3500 #define SDR0_MFR_ETH0_CLK_SEL        0x08000000   /* Ethernet0 Clock Select */
3501 #define SDR0_MFR_ETH1_CLK_SEL        0x04000000   /* Ethernet1 Clock Select */
3502 #define SDR0_MFR_ZMII_MODE_MASK      0x03000000   /* ZMII Mode Mask   */
3503 #define SDR0_MFR_ZMII_MODE_MII       0x00000000     /* ZMII Mode MII  */
3504 #define SDR0_MFR_ZMII_MODE_SMII      0x01000000     /* ZMII Mode SMII */
3505 #define SDR0_MFR_ZMII_MODE_RMII_10M  0x02000000     /* ZMII Mode RMII - 10 Mbs   */
3506 #define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000     /* ZMII Mode RMII - 100 Mbs  */
3507 #define SDR0_MFR_ZMII_MODE_BIT0      0x02000000     /* ZMII Mode Bit0 */
3508 #define SDR0_MFR_ZMII_MODE_BIT1      0x01000000     /* ZMII Mode Bit1 */
3509 #define SDR0_MFR_ERRATA3_EN0         0x00800000
3510 #define SDR0_MFR_ERRATA3_EN1         0x00400000
3511 #if defined(CONFIG_440GX) /* test-only: only 440GX or 440SPE??? */
3512 #define SDR0_MFR_PKT_REJ_MASK        0x00300000   /* Pkt Rej. Enable Mask */
3513 #define SDR0_MFR_PKT_REJ_EN          0x00300000   /* Pkt Rej. Enable on both EMAC3 0-1 */
3514 #define SDR0_MFR_PKT_REJ_EN0         0x00200000   /* Pkt Rej. Enable on EMAC3(0) */
3515 #define SDR0_MFR_PKT_REJ_EN1         0x00100000   /* Pkt Rej. Enable on EMAC3(1) */
3516 #define SDR0_MFR_PKT_REJ_POL         0x00080000   /* Packet Reject Polarity      */
3517 #endif
3518
3519 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
3520 #define SDR0_PFC1_EPS_ENCODE(n)         ((((unsigned long)(n))&0x07)<<22)
3521 #define SDR0_PFC1_EPS_DECODE(n)         ((((unsigned long)(n))>>22)&0x07)
3522 #define SDR0_PFC2_EPS_ENCODE(n)         ((((unsigned long)(n))&0x07)<<29)
3523 #define SDR0_PFC2_EPS_DECODE(n)         ((((unsigned long)(n))>>29)&0x07)
3524 #endif
3525
3526 #define SDR0_MFR_ECS_MASK               0x10000000
3527 #define SDR0_MFR_ECS_INTERNAL           0x10000000
3528
3529 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
3530 #define SDR0_SRST0        0x200
3531 #define SDR0_SRST0_BGO          0x80000000 /* PLB to OPB bridge */
3532 #define SDR0_SRST0_PLB4         0x40000000 /* PLB4 arbiter */
3533 #define SDR0_SRST0_EBC          0x20000000 /* External bus controller */
3534 #define SDR0_SRST0_OPB          0x10000000 /* OPB arbiter */
3535 #define SDR0_SRST0_UART0        0x08000000 /* Universal asynchronous receiver/transmitter 0 */
3536 #define SDR0_SRST0_UART1        0x04000000 /* Universal asynchronous receiver/transmitter 1 */
3537 #define SDR0_SRST0_IIC0         0x02000000 /* Inter integrated circuit 0 */
3538 #define SDR0_SRST0_USB2H        0x01000000 /* USB2.0 Host */
3539 #define SDR0_SRST0_GPIO         0x00800000 /* General purpose I/O */
3540 #define SDR0_SRST0_GPT          0x00400000 /* General purpose timer */
3541 #define SDR0_SRST0_DMC          0x00200000 /* DDR SDRAM memory controller */
3542 #define SDR0_SRST0_PCI          0x00100000 /* PCI */
3543 #define SDR0_SRST0_EMAC0        0x00080000 /* Ethernet media access controller 0 */
3544 #define SDR0_SRST0_EMAC1        0x00040000 /* Ethernet media access controller 1 */
3545 #define SDR0_SRST0_CPM0         0x00020000 /* Clock and power management */
3546 #define SDR0_SRST0_ZMII         0x00010000 /* ZMII bridge */
3547 #define SDR0_SRST0_UIC0         0x00008000 /* Universal interrupt controller 0 */
3548 #define SDR0_SRST0_UIC1         0x00004000 /* Universal interrupt controller 1 */
3549 #define SDR0_SRST0_IIC1         0x00002000 /* Inter integrated circuit 1 */
3550 #define SDR0_SRST0_SCP          0x00001000 /* Serial communications port */
3551 #define SDR0_SRST0_BGI          0x00000800 /* OPB to PLB bridge */
3552 #define SDR0_SRST0_DMA          0x00000400 /* Direct memory access controller */
3553 #define SDR0_SRST0_DMAC         0x00000200 /* DMA channel */
3554 #define SDR0_SRST0_MAL          0x00000100 /* Media access layer */
3555 #define SDR0_SRST0_USB2D        0x00000080 /* USB2.0 device */
3556 #define SDR0_SRST0_GPTR         0x00000040 /* General purpose timer */
3557 #define SDR0_SRST0_P4P3         0x00000010 /* PLB4 to PLB3 bridge */
3558 #define SDR0_SRST0_P3P4         0x00000008 /* PLB3 to PLB4 bridge */
3559 #define SDR0_SRST0_PLB3         0x00000004 /* PLB3 arbiter */
3560 #define SDR0_SRST0_UART2        0x00000002 /* Universal asynchronous receiver/transmitter 2 */
3561 #define SDR0_SRST0_UART3        0x00000001 /* Universal asynchronous receiver/transmitter 3 */
3562
3563 #define SDR0_SRST1        0x201
3564 #define SDR0_SRST1_NDFC         0x80000000 /* Nand flash controller */
3565 #define SDR0_SRST1_OPBA1        0x40000000 /* OPB Arbiter attached to PLB4 */
3566 #define SDR0_SRST1_P4OPB0       0x20000000 /* PLB4 to OPB Bridge0 */
3567 #define SDR0_SRST1_PLB42OPB0    SDR0_SRST1_P4OPB0
3568 #define SDR0_SRST1_DMA4         0x10000000 /* DMA to PLB4 */
3569 #define SDR0_SRST1_DMA4CH       0x08000000 /* DMA Channel to PLB4 */
3570 #define SDR0_SRST1_OPBA2        0x04000000 /* OPB Arbiter attached to PLB4 USB 2.0 Host */
3571 #define SDR0_SRST1_OPB2PLB40    0x02000000 /* OPB to PLB4 Bridge attached to USB 2.0 Host */
3572 #define SDR0_SRST1_PLB42OPB1    0x01000000 /* PLB4 to OPB Bridge attached to USB 2.0 Host */
3573 #define SDR0_SRST1_CPM1         0x00800000 /* Clock and Power management 1 */
3574 #define SDR0_SRST1_UIC2         0x00400000 /* Universal Interrupt Controller 2 */
3575 #define SDR0_SRST1_CRYP0        0x00200000 /* Security Engine */
3576 #define SDR0_SRST1_USB20PHY     0x00100000 /* USB 2.0 Phy */
3577 #define SDR0_SRST1_USB2HUTMI    0x00080000 /* USB 2.0 Host UTMI Interface */
3578 #define SDR0_SRST1_USB2HPHY     0x00040000 /* USB 2.0 Host Phy Interface */
3579 #define SDR0_SRST1_SRAM0        0x00020000 /* Internal SRAM Controller */
3580 #define SDR0_SRST1_RGMII0       0x00010000 /* RGMII Bridge */
3581 #define SDR0_SRST1_ETHPLL       0x00008000 /* Ethernet PLL */
3582 #define SDR0_SRST1_FPU          0x00004000 /* Floating Point Unit */
3583 #define SDR0_SRST1_KASU0        0x00002000 /* Kasumi Engine */
3584
3585 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
3586
3587 #define SDR0_SRST0              0x0200
3588 #define SDR0_SRST               SDR0_SRST0 /* for compatability reasons */
3589 #define SDR0_SRST0_BGO          0x80000000 /* PLB to OPB bridge */
3590 #define SDR0_SRST0_PLB4         0x40000000 /* PLB4 arbiter */
3591 #define SDR0_SRST0_EBC          0x20000000 /* External bus controller */
3592 #define SDR0_SRST0_OPB          0x10000000 /* OPB arbiter */
3593 #define SDR0_SRST0_UART0        0x08000000 /* Universal asynchronous receiver/transmitter 0 */
3594 #define SDR0_SRST0_UART1        0x04000000 /* Universal asynchronous receiver/transmitter 1 */
3595 #define SDR0_SRST0_IIC0         0x02000000 /* Inter integrated circuit 0 */
3596 #define SDR0_SRST0_IIC1         0x01000000 /* Inter integrated circuit 1 */
3597 #define SDR0_SRST0_GPIO0        0x00800000 /* General purpose I/O 0 */
3598 #define SDR0_SRST0_GPT          0x00400000 /* General purpose timer */
3599 #define SDR0_SRST0_DMC          0x00200000 /* DDR SDRAM memory controller */
3600 #define SDR0_SRST0_PCI          0x00100000 /* PCI */
3601 #define SDR0_SRST0_CPM0         0x00020000 /* Clock and power management */
3602 #define SDR0_SRST0_IMU          0x00010000 /* I2O DMA */
3603 #define SDR0_SRST0_UIC0         0x00008000 /* Universal interrupt controller 0*/
3604 #define SDR0_SRST0_UIC1         0x00004000 /* Universal interrupt controller 1*/
3605 #define SDR0_SRST0_SRAM         0x00002000 /* Universal interrupt controller 0*/
3606 #define SDR0_SRST0_UIC2         0x00001000 /* Universal interrupt controller 2*/
3607 #define SDR0_SRST0_UIC3         0x00000800 /* Universal interrupt controller 3*/
3608 #define SDR0_SRST0_OCM          0x00000400 /* Universal interrupt controller 0*/
3609 #define SDR0_SRST0_UART2        0x00000200 /* Universal asynchronous receiver/transmitter 2 */
3610 #define SDR0_SRST0_MAL          0x00000100 /* Media access layer */
3611 #define SDR0_SRST0_GPTR         0x00000040 /* General purpose timer */
3612 #define SDR0_SRST0_L2CACHE      0x00000004 /* L2 Cache */
3613 #define SDR0_SRST0_UART3        0x00000002 /* Universal asynchronous receiver/transmitter 3 */
3614 #define SDR0_SRST0_GPIO1        0x00000001 /* General purpose I/O 1 */
3615
3616 #define SDR0_SRST1              0x201
3617 #define SDR0_SRST1_RLL          0x80000000 /* SRIO RLL */
3618 #define SDR0_SRST1_SCP          0x40000000 /* Serial communications port */
3619 #define SDR0_SRST1_PLBARB       0x20000000 /* PLB Arbiter */
3620 #define SDR0_SRST1_EIPPKP       0x10000000 /* EIPPPKP */
3621 #define SDR0_SRST1_EIP94        0x08000000 /* EIP 94 */
3622 #define SDR0_SRST1_EMAC0        0x04000000 /* Ethernet media access controller 0 */
3623 #define SDR0_SRST1_EMAC1        0x02000000 /* Ethernet media access controller 1 */
3624 #define SDR0_SRST1_EMAC2        0x01000000 /* Ethernet media access controller 2 */
3625 #define SDR0_SRST1_EMAC3        0x00800000 /* Ethernet media access controller 3 */
3626 #define SDR0_SRST1_ZMII         0x00400000 /* Ethernet ZMII/RMII/SMII */
3627 #define SDR0_SRST1_RGMII0       0x00200000 /* Ethernet RGMII/RTBI 0 */
3628 #define SDR0_SRST1_RGMII1       0x00100000 /* Ethernet RGMII/RTBI 1 */
3629 #define SDR0_SRST1_DMA4         0x00080000 /* DMA to PLB4 */
3630 #define SDR0_SRST1_DMA4CH       0x00040000 /* DMA Channel to PLB4 */
3631 #define SDR0_SRST1_SATAPHY      0x00020000 /* Serial ATA PHY */
3632 #define SDR0_SRST1_SRIODEV      0x00010000 /* Serial Rapid IO core, PCS, and serdes */
3633 #define SDR0_SRST1_SRIOPCS      0x00008000 /* Serial Rapid IO core and PCS */
3634 #define SDR0_SRST1_NDFC         0x00004000 /* Nand flash controller */
3635 #define SDR0_SRST1_SRIOPLB      0x00002000 /* Serial Rapid IO PLB */
3636 #define SDR0_SRST1_ETHPLL       0x00001000 /* Ethernet PLL */
3637 #define SDR0_SRST1_TAHOE1       0x00000800 /* Ethernet Tahoe 1 */
3638 #define SDR0_SRST1_TAHOE0       0x00000400 /* Ethernet Tahoe 0 */
3639 #define SDR0_SRST1_SGMII0       0x00000200 /* Ethernet SGMII 0 */
3640 #define SDR0_SRST1_SGMII1       0x00000100 /* Ethernet SGMII 1 */
3641 #define SDR0_SRST1_SGMII2       0x00000080 /* Ethernet SGMII 2 */
3642 #define SDR0_SRST1_AHB          0x00000040 /* PLB4XAHB bridge */
3643 #define SDR0_SRST1_USBOTGPHY    0x00000020 /* USB 2.0 OTG PHY */
3644 #define SDR0_SRST1_USBOTG       0x00000010 /* USB 2.0 OTG controller */
3645 #define SDR0_SRST1_USBHOST      0x00000008 /* USB 2.0 Host controller */
3646 #define SDR0_SRST1_AHBDMAC      0x00000004 /* AHB DMA controller */
3647 #define SDR0_SRST1_AHBICM       0x00000002 /* AHB inter-connect matrix */
3648 #define SDR0_SRST1_SATA         0x00000001 /* Serial ATA controller */
3649
3650 #define SDR0_PCI0               0x1c0           /* PCI Configuration Register */
3651
3652 #else
3653
3654 #define SDR0_SRST_BGO                   0x80000000
3655 #define SDR0_SRST_PLB                   0x40000000
3656 #define SDR0_SRST_EBC                   0x20000000
3657 #define SDR0_SRST_OPB                   0x10000000
3658 #define SDR0_SRST_UART0                 0x08000000
3659 #define SDR0_SRST_UART1                 0x04000000
3660 #define SDR0_SRST_IIC0                  0x02000000
3661 #define SDR0_SRST_IIC1                  0x01000000
3662 #define SDR0_SRST_GPIO                  0x00800000
3663 #define SDR0_SRST_GPT                   0x00400000
3664 #define SDR0_SRST_DMC                   0x00200000
3665 #define SDR0_SRST_PCI                   0x00100000
3666 #define SDR0_SRST_EMAC0                 0x00080000
3667 #define SDR0_SRST_EMAC1                 0x00040000
3668 #define SDR0_SRST_CPM                   0x00020000
3669 #define SDR0_SRST_IMU                   0x00010000
3670 #define SDR0_SRST_UIC01                 0x00008000
3671 #define SDR0_SRST_UICB2                 0x00004000
3672 #define SDR0_SRST_SRAM                  0x00002000
3673 #define SDR0_SRST_EBM                   0x00001000
3674 #define SDR0_SRST_BGI                   0x00000800
3675 #define SDR0_SRST_DMA                   0x00000400
3676 #define SDR0_SRST_DMAC                  0x00000200
3677 #define SDR0_SRST_MAL                   0x00000100
3678 #define SDR0_SRST_ZMII                  0x00000080
3679 #define SDR0_SRST_GPTR                  0x00000040
3680 #define SDR0_SRST_PPM                   0x00000020
3681 #define SDR0_SRST_EMAC2                 0x00000010
3682 #define SDR0_SRST_EMAC3                 0x00000008
3683 #define SDR0_SRST_RGMII                 0x00000001
3684
3685 #endif
3686
3687 /*-----------------------------------------------------------------------------+
3688 |  Clocking
3689 +-----------------------------------------------------------------------------*/
3690 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
3691 #define PLLSYS0_FWD_DIV_A_MASK  0x000000f0      /* Fwd Div A */
3692 #define PLLSYS0_FWD_DIV_B_MASK  0x0000000f      /* Fwd Div B */
3693 #define PLLSYS0_FB_DIV_MASK     0x0000ff00      /* Feedback divisor */
3694 #define PLLSYS0_OPB_DIV_MASK    0x0c000000      /* OPB Divisor */
3695 #define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000     /* PLB Early Clock Divisor */
3696 #define PLLSYS0_PERCLK_DIV_MASK 0x03000000      /* Peripheral Clk Divisor */
3697 #define PLLSYS0_SEL_MASK        0x18000000      /* 0 = PLL, 1 = PerClk */
3698 #elif !defined (CONFIG_440GX) && \
3699     !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
3700     !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
3701     !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
3702 #define PLLSYS0_TUNE_MASK       0xffc00000      /* PLL TUNE bits            */
3703 #define PLLSYS0_FB_DIV_MASK     0x003c0000      /* Feedback divisor         */
3704 #define PLLSYS0_FWD_DIV_A_MASK  0x00038000      /* Forward divisor A        */
3705 #define PLLSYS0_FWD_DIV_B_MASK  0x00007000      /* Forward divisor B        */
3706 #define PLLSYS0_OPB_DIV_MASK    0x00000c00      /* OPB divisor              */
3707 #define PLLSYS0_EPB_DIV_MASK    0x00000300      /* EPB divisor              */
3708 #define PLLSYS0_EXTSL_MASK      0x00000080      /* PerClk feedback path     */
3709 #define PLLSYS0_RW_MASK         0x00000060      /* ROM width                */
3710 #define PLLSYS0_RL_MASK         0x00000010      /* ROM location             */
3711 #define PLLSYS0_ZMII_SEL_MASK   0x0000000c      /* ZMII selection           */
3712 #define PLLSYS0_BYPASS_MASK     0x00000002      /* Bypass PLL               */
3713 #define PLLSYS0_NTO1_MASK       0x00000001      /* CPU:PLB N-to-1 ratio     */
3714
3715 #define PLL_VCO_FREQ_MIN        500             /* Min VCO freq (MHz)       */
3716 #define PLL_VCO_FREQ_MAX        1000            /* Max VCO freq (MHz)       */
3717 #define PLL_CPU_FREQ_MAX        400             /* Max CPU freq (MHz)       */
3718 #define PLL_PLB_FREQ_MAX        133             /* Max PLB freq (MHz)       */
3719 #else /* !CONFIG_440GX or CONFIG_440EP or CONFIG_440GR */
3720 #define PLLSYS0_ENG_MASK        0x80000000      /* 0 = SysClk, 1 = PLL VCO */
3721 #define PLLSYS0_SRC_MASK        0x40000000      /* 0 = PLL A, 1 = PLL B */
3722 #define PLLSYS0_SEL_MASK        0x38000000      /* 0 = PLL, 1 = CPU, 5 = PerClk */
3723 #define PLLSYS0_TUNE_MASK       0x07fe0000      /* PLL Tune bits */
3724 #define PLLSYS0_FB_DIV_MASK     0x0001f000      /* Feedback divisor */
3725 #define PLLSYS0_FWD_DIV_A_MASK  0x00000f00      /* Fwd Div A */
3726 #define PLLSYS0_FWD_DIV_B_MASK  0x000000e0      /* Fwd Div B */
3727 #define PLLSYS0_PRI_DIV_B_MASK  0x0000001c      /* PLL Primary Divisor B */
3728 #define PLLSYS0_OPB_DIV_MASK    0x00000003      /* OPB Divisor */
3729
3730 #define PLLC_ENG_MASK       0x20000000  /* PLL primary forward divisor source   */
3731 #define PLLC_SRC_MASK       0x20000000  /* PLL feedback source   */
3732 #define PLLD_FBDV_MASK      0x1f000000  /* PLL Feedback Divisor  */
3733 #define PLLD_FWDVA_MASK     0x000f0000  /* PLL Forward Divisor A */
3734 #define PLLD_FWDVB_MASK     0x00000700  /* PLL Forward Divisor B */
3735 #define PLLD_LFBDV_MASK     0x0000003f  /* PLL Local Feedback Divisor */
3736
3737 #define OPBDDV_MASK         0x03000000  /* OPB Clock Divisor Register */
3738 #define PERDV_MASK          0x07000000  /* Periferal Clock Divisor */
3739 #define PRADV_MASK          0x07000000  /* Primary Divisor A */
3740 #define PRBDV_MASK          0x07000000  /* Primary Divisor B */
3741 #define SPCID_MASK          0x03000000  /* Sync PCI Divisor  */
3742
3743 #define PLL_VCO_FREQ_MIN        500             /* Min VCO freq (MHz)       */
3744 #define PLL_VCO_FREQ_MAX        1000            /* Max VCO freq (MHz)       */
3745 #define PLL_CPU_FREQ_MAX        400             /* Max CPU freq (MHz)       */
3746 #define PLL_PLB_FREQ_MAX        133             /* Max PLB freq (MHz)       */
3747
3748 /* Strap 1 Register */
3749 #define PLLSYS1_LF_DIV_MASK     0xfc000000      /* PLL Local Feedback Divisor */
3750 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000      /* Peripheral Clk Divisor */
3751 #define PLLSYS1_MAL_DIV_MASK    0x00c00000      /* MAL Clk Divisor */
3752 #define PLLSYS1_RW_MASK         0x00300000      /* ROM width */
3753 #define PLLSYS1_EAR_MASK        0x00080000      /* ERAP Addres reset vector */
3754 #define PLLSYS1_PAE_MASK        0x00040000      /* PCI arbitor enable */
3755 #define PLLSYS1_PCHE_MASK       0x00020000      /* PCI host config enable */
3756 #define PLLSYS1_PISE_MASK       0x00010000      /* PCI init seq. enable */
3757 #define PLLSYS1_PCWE_MASK       0x00008000      /* PCI local cpu wait enable */
3758 #define PLLSYS1_PPIM_MASK       0x00007800      /* PCI inbound map */
3759 #define PLLSYS1_PR64E_MASK      0x00000400      /* PCI init Req64 enable */
3760 #define PLLSYS1_PXFS_MASK       0x00000300      /* PCI-X Freq Sel */
3761 #define PLLSYS1_RSVD_MASK       0x00000080      /* RSVD */
3762 #define PLLSYS1_PDM_MASK        0x00000040      /* PCI-X Driver Mode */
3763 #define PLLSYS1_EPS_MASK        0x00000038      /* Ethernet Pin Select */
3764 #define PLLSYS1_RMII_MASK       0x00000004      /* RMII Mode */
3765 #define PLLSYS1_TRE_MASK        0x00000002      /* GPIO Trace Enable */
3766 #define PLLSYS1_NTO1_MASK       0x00000001      /* CPU:PLB N-to-1 ratio */
3767 #endif /* CONFIG_440GX */
3768
3769 #if defined (CONFIG_440EPX) || defined (CONFIG_440GRX)
3770 /*--------------------------------------*/
3771 #define CPR0_PLLC                   0x40
3772 #define   CPR0_PLLC_RST_MASK           0x80000000
3773 #define   CPR0_PLLC_RST_PLLLOCKED      0x00000000
3774 #define   CPR0_PLLC_RST_PLLRESET       0x80000000
3775 #define   CPR0_PLLC_ENG_MASK           0x40000000
3776 #define   CPR0_PLLC_ENG_DISABLE        0x00000000
3777 #define   CPR0_PLLC_ENG_ENABLE         0x40000000
3778 #define   CPR0_PLLC_ENG_ENCODE(n)      ((((unsigned long)(n))&0x01)<<30)
3779 #define   CPR0_PLLC_ENG_DECODE(n)      ((((unsigned long)(n))>>30)&0x01)
3780 #define   CPR0_PLLC_SRC_MASK           0x20000000
3781 #define   CPR0_PLLC_SRC_PLLOUTA        0x00000000
3782 #define   CPR0_PLLC_SRC_PLLOUTB        0x20000000
3783 #define   CPR0_PLLC_SRC_ENCODE(n)      ((((unsigned long)(n))&0x01)<<29)
3784 #define   CPR0_PLLC_SRC_DECODE(n)      ((((unsigned long)(n))>>29)&0x01)
3785 #define   CPR0_PLLC_SEL_MASK           0x07000000
3786 #define   CPR0_PLLC_SEL_PLL            0x00000000
3787 #define   CPR0_PLLC_SEL_CPU            0x01000000
3788 #define   CPR0_PLLC_SEL_PER            0x05000000
3789 #define   CPR0_PLLC_SEL_ENCODE(n)      ((((unsigned long)(n))&0x07)<<24)
3790 #define   CPR0_PLLC_SEL_DECODE(n)      ((((unsigned long)(n))>>24)&0x07)
3791 #define   CPR0_PLLC_TUNE_MASK          0x000003FF
3792 #define   CPR0_PLLC_TUNE_ENCODE(n)     ((((unsigned long)(n))&0x3FF)<<0)
3793 #define   CPR0_PLLC_TUNE_DECODE(n)     ((((unsigned long)(n))>>0)&0x3FF)
3794 /*--------------------------------------*/
3795 #define CPR0_PLLD                   0x60
3796 #define   CPR0_PLLD_FBDV_MASK          0x1F000000
3797 #define   CPR0_PLLD_FBDV_ENCODE(n)     ((((unsigned long)(n))&0x1F)<<24)
3798 #define   CPR0_PLLD_FBDV_DECODE(n)     ((((((unsigned long)(n))>>24)-1)&0x1F)+1)
3799 #define   CPR0_PLLD_FWDVA_MASK         0x000F0000
3800 #define   CPR0_PLLD_FWDVA_ENCODE(n)    ((((unsigned long)(n))&0x0F)<<16)
3801 #define   CPR0_PLLD_FWDVA_DECODE(n)    ((((((unsigned long)(n))>>16)-1)&0x0F)+1)
3802 #define   CPR0_PLLD_FWDVB_MASK         0x00000700
3803 #define   CPR0_PLLD_FWDVB_ENCODE(n)    ((((unsigned long)(n))&0x07)<<8)
3804 #define   CPR0_PLLD_FWDVB_DECODE(n)    ((((((unsigned long)(n))>>8)-1)&0x07)+1)
3805 #define   CPR0_PLLD_LFBDV_MASK         0x0000003F
3806 #define   CPR0_PLLD_LFBDV_ENCODE(n)    ((((unsigned long)(n))&0x3F)<<0)
3807 #define   CPR0_PLLD_LFBDV_DECODE(n)    ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
3808 /*--------------------------------------*/
3809 #define CPR0_PRIMAD                 0x80
3810 #define   CPR0_PRIMAD_PRADV0_MASK      0x07000000
3811 #define   CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
3812 #define   CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
3813 /*--------------------------------------*/
3814 #define CPR0_PRIMBD                 0xA0
3815 #define   CPR0_PRIMBD_PRBDV0_MASK      0x07000000
3816 #define   CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
3817 #define   CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
3818 /*--------------------------------------*/
3819 #if 0
3820 #define CPR0_CPM0_ER                0xB0    /* CPM Enable Register */
3821 #define CPR0_CPM0_FR                0xB1    /* CPM Force Register */
3822 #define CPR0_CPM0_SR                0xB2    /* CPM Status Register */
3823 #define CPR0_CPM0_IIC0               0x80000000    /* Inter-Intergrated Circuit0 */
3824 #define CPR0_CPM0_IIC1               0x40000000    /* Inter-Intergrated Circuit1 */
3825 #define CPR0_CPM0_PCI                0x20000000    /* Peripheral Component Interconnect */
3826 #define CPR0_CPM0_USB1H              0x08000000    /* USB1.1 Host */
3827 #define CPR0_CPM0_FPU                0x04000000    /* PPC440 FPU */
3828 #define CPR0_CPM0_CPU                0x02000000    /* PPC440x5 Processor Core */
3829 #define CPR0_CPM0_DMA                0x01000000    /* Direct Memory Access Controller */
3830 #define CPR0_CPM0_BGO                0x00800000    /* PLB to OPB Bridge */
3831 #define CPR0_CPM0_BGI                0x00400000    /* OPB to PLB Bridge */
3832 #define CPR0_CPM0_EBC                0x00200000    /* External Bus Controller */
3833 #define CPR0_CPM0_NDFC               0x00100000    /* Nand Flash Controller */
3834 #define CPR0_CPM0_MADMAL             0x00080000    /* DDR SDRAM Controller or MADMAL ??? */
3835 #define CPR0_CPM0_DMC                0x00080000    /* DDR SDRAM Controller or MADMAL ??? */
3836 #define CPR0_CPM0_PLB4               0x00040000    /* PLB4 Arbiter */
3837 #define CPR0_CPM0_PLB4x3x            0x00020000    /* PLB4 to PLB3 */
3838 #define CPR0_CPM0_PLB3x4x            0x00010000    /* PLB3 to PLB4 */
3839 #define CPR0_CPM0_PLB3               0x00008000    /* PLB3 Arbiter */
3840 #define CPR0_CPM0_PPM                0x00002000    /* PLB Performance Monitor */
3841 #define CPR0_CPM0_UIC1               0x00001000    /* Universal Interrupt Controller 1 */
3842 #define CPR0_CPM0_GPIO               0x00000800    /* General Purpose IO */
3843 #define CPR0_CPM0_GPT                0x00000400    /* General Purpose Timer */
3844 #define CPR0_CPM0_UART0              0x00000200    /* Universal Asynchronous Rcver/Xmitter 0 */
3845 #define CPR0_CPM0_UART1              0x00000100    /* Universal Asynchronous Rcver/Xmitter 1 */
3846 #define CPR0_CPM0_UIC0               0x00000080    /* Universal Interrupt Controller 0 */
3847 #define CPR0_CPM0_TMRCLK             0x00000040    /* CPU Timer */
3848 #define CPR0_CPM0_EMC0               0x00000020    /* Ethernet 0 */
3849 #define CPR0_CPM0_EMC1               0x00000010    /* Ethernet 1 */
3850 #define CPR0_CPM0_UART2              0x00000008    /* Universal Asynchronous Rcver/Xmitter 2 */
3851 #define CPR0_CPM0_UART3              0x00000004    /* Universal Asynchronous Rcver/Xmitter 3 */
3852 #define CPR0_CPM0_USB2D              0x00000002    /* USB2.0 Device */
3853 #define CPR0_CPM0_USB2H              0x00000001    /* USB2.0 Host */
3854 #endif
3855 /*--------------------------------------*/
3856 #define CPR0_OPBD                   0xC0
3857 #define   CPR0_OPBD_OPBDV0_MASK        0x03000000
3858 #define   CPR0_OPBD_OPBDV0_ENCODE(n)   ((((unsigned long)(n))&0x03)<<24)
3859 #define   CPR0_OPBD_OPBDV0_DECODE(n)   ((((((unsigned long)(n))>>24)-1)&0x03)+1)
3860 /*--------------------------------------*/
3861 #define CPR0_PERD                   0xE0
3862 #define   CPR0_PERD_PERDV0_MASK        0x07000000
3863 #define   CPR0_PERD_PERDV0_ENCODE(n)   ((((unsigned long)(n))&0x07)<<24)
3864 #define   CPR0_PERD_PERDV0_DECODE(n)   ((((((unsigned long)(n))>>24)-1)&0x07)+1)
3865 /*--------------------------------------*/
3866 #define CPR0_MALD                  0x100
3867 #define   CPR0_MALD_MALDV0_MASK        0x03000000
3868 #define   CPR0_MALD_MALDV0_ENCODE(n)   ((((unsigned long)(n))&0x03)<<24)
3869 #define   CPR0_MALD_MALDV0_DECODE(n)   ((((((unsigned long)(n))>>24)-1)&0x03)+1)
3870 /*--------------------------------------*/
3871 #define CPR0_SPCID                 0x120
3872 #define   CPR0_SPCID_SPCIDV0_MASK      0x03000000
3873 #define   CPR0_SPCID_SPCIDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
3874 #define   CPR0_SPCID_SPCIDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
3875 /*--------------------------------------*/
3876 #define CPR0_ICFG                  0x140
3877 #define   CPR0_ICFG_RLI_MASK           0x80000000
3878 #define   CPR0_ICFG_RLI_RESETCPR       0x00000000
3879 #define   CPR0_ICFG_RLI_PRESERVECPR    0x80000000
3880 #define   CPR0_ICFG_ICS_MASK           0x00000007
3881 #endif /* defined (CONFIG_440EPX) || defined (CONFIG_440GRX) */
3882
3883 /*-----------------------------------------------------------------------------
3884 | IIC Register Offsets
3885 '----------------------------------------------------------------------------*/
3886 #define IICMDBUF                0x00
3887 #define IICSDBUF                0x02
3888 #define IICLMADR                0x04
3889 #define IICHMADR                0x05
3890 #define IICCNTL                 0x06
3891 #define IICMDCNTL               0x07
3892 #define IICSTS                  0x08
3893 #define IICEXTSTS               0x09
3894 #define IICLSADR                0x0A
3895 #define IICHSADR                0x0B
3896 #define IICCLKDIV               0x0C
3897 #define IICINTRMSK              0x0D
3898 #define IICXFRCNT               0x0E
3899 #define IICXTCNTLSS             0x0F
3900 #define IICDIRECTCNTL           0x10
3901
3902 /*-----------------------------------------------------------------------------
3903 | UART Register Offsets
3904 '----------------------------------------------------------------------------*/
3905 #define DATA_REG                0x00
3906 #define DL_LSB                  0x00
3907 #define DL_MSB                  0x01
3908 #define INT_ENABLE              0x01
3909 #define FIFO_CONTROL            0x02
3910 #define LINE_CONTROL            0x03
3911 #define MODEM_CONTROL           0x04
3912 #define LINE_STATUS             0x05
3913 #define MODEM_STATUS            0x06
3914 #define SCRATCH                 0x07
3915
3916 /*-----------------------------------------------------------------------------
3917 | PCI Internal Registers et. al. (accessed via plb)
3918 +----------------------------------------------------------------------------*/
3919 #define PCIX0_CFGADR            (CFG_PCI_BASE + 0x0ec00000)
3920 #define PCIX0_CFGDATA           (CFG_PCI_BASE + 0x0ec00004)
3921 #define PCIX0_CFGBASE           (CFG_PCI_BASE + 0x0ec80000)
3922 #define PCIX0_IOBASE            (CFG_PCI_BASE + 0x08000000)
3923
3924 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
3925     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
3926
3927 /* PCI Local Configuration Registers
3928    --------------------------------- */
3929 #define PCI_MMIO_LCR_BASE (CFG_PCI_BASE + 0x0f400000)    /* Real => 0x0EF400000 */
3930
3931 /* PCI Master Local Configuration Registers */
3932 #define PCIX0_PMM0LA         (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
3933 #define PCIX0_PMM0MA         (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */
3934 #define PCIX0_PMM0PCILA      (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */
3935 #define PCIX0_PMM0PCIHA      (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */
3936 #define PCIX0_PMM1LA         (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */
3937 #define PCIX0_PMM1MA         (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */
3938 #define PCIX0_PMM1PCILA      (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */
3939 #define PCIX0_PMM1PCIHA      (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */
3940 #define PCIX0_PMM2LA         (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */
3941 #define PCIX0_PMM2MA         (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */
3942 #define PCIX0_PMM2PCILA      (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */
3943 #define PCIX0_PMM2PCIHA      (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */
3944
3945 /* PCI Target Local Configuration Registers */
3946 #define PCIX0_PTM1MS         (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/Attribute */
3947 #define PCIX0_PTM1LA         (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */
3948 #define PCIX0_PTM2MS         (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/Attribute */
3949 #define PCIX0_PTM2LA         (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */
3950
3951 #else
3952
3953 #define PCIX0_VENDID            (PCIX0_CFGBASE + PCI_VENDOR_ID )
3954 #define PCIX0_DEVID             (PCIX0_CFGBASE + PCI_DEVICE_ID )
3955 #define PCIX0_CMD               (PCIX0_CFGBASE + PCI_COMMAND )
3956 #define PCIX0_STATUS            (PCIX0_CFGBASE + PCI_STATUS )
3957 #define PCIX0_REVID             (PCIX0_CFGBASE + PCI_REVISION_ID )
3958 #define PCIX0_CLS               (PCIX0_CFGBASE + PCI_CLASS_CODE)
3959 #define PCIX0_CACHELS           (PCIX0_CFGBASE + PCI_CACHE_LINE_SIZE )
3960 #define PCIX0_LATTIM            (PCIX0_CFGBASE + PCI_LATENCY_TIMER )
3961 #define PCIX0_HDTYPE            (PCIX0_CFGBASE + PCI_HEADER_TYPE )
3962 #define PCIX0_BIST              (PCIX0_CFGBASE + PCI_BIST )
3963 #define PCIX0_BAR0              (PCIX0_CFGBASE + PCI_BASE_ADDRESS_0 )
3964 #define PCIX0_BAR1              (PCIX0_CFGBASE + PCI_BASE_ADDRESS_1 )
3965 #define PCIX0_BAR2              (PCIX0_CFGBASE + PCI_BASE_ADDRESS_2 )
3966 #define PCIX0_BAR3              (PCIX0_CFGBASE + PCI_BASE_ADDRESS_3 )
3967 #define PCIX0_BAR4              (PCIX0_CFGBASE + PCI_BASE_ADDRESS_4 )
3968 #define PCIX0_BAR5              (PCIX0_CFGBASE + PCI_BASE_ADDRESS_5 )
3969 #define PCIX0_CISPTR            (PCIX0_CFGBASE + PCI_CARDBUS_CIS )
3970 #define PCIX0_SBSYSVID          (PCIX0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
3971 #define PCIX0_SBSYSID           (PCIX0_CFGBASE + PCI_SUBSYSTEM_ID )
3972 #define PCIX0_EROMBA            (PCIX0_CFGBASE + PCI_ROM_ADDRESS )
3973 #define PCIX0_CAP               (PCIX0_CFGBASE + PCI_CAPABILITY_LIST )
3974 #define PCIX0_RES0              (PCIX0_CFGBASE + 0x0035 )
3975 #define PCIX0_RES1              (PCIX0_CFGBASE + 0x0036 )
3976 #define PCIX0_RES2              (PCIX0_CFGBASE + 0x0038 )
3977 #define PCIX0_INTLN             (PCIX0_CFGBASE + PCI_INTERRUPT_LINE )
3978 #define PCIX0_INTPN             (PCIX0_CFGBASE + PCI_INTERRUPT_PIN )
3979 #define PCIX0_MINGNT            (PCIX0_CFGBASE + PCI_MIN_GNT )
3980 #define PCIX0_MAXLTNCY          (PCIX0_CFGBASE + PCI_MAX_LAT )
3981
3982 #define PCIX0_BRDGOPT1          (PCIX0_CFGBASE + 0x0040)
3983 #define PCIX0_BRDGOPT2          (PCIX0_CFGBASE + 0x0044)
3984
3985 #define PCIX0_POM0LAL           (PCIX0_CFGBASE + 0x0068)
3986 #define PCIX0_POM0LAH           (PCIX0_CFGBASE + 0x006c)
3987 #define PCIX0_POM0SA            (PCIX0_CFGBASE + 0x0070)
3988 #define PCIX0_POM0PCIAL         (PCIX0_CFGBASE + 0x0074)
3989 #define PCIX0_POM0PCIAH         (PCIX0_CFGBASE + 0x0078)
3990 #define PCIX0_POM1LAL           (PCIX0_CFGBASE + 0x007c)
3991 #define PCIX0_POM1LAH           (PCIX0_CFGBASE + 0x0080)
3992 #define PCIX0_POM1SA            (PCIX0_CFGBASE + 0x0084)
3993 #define PCIX0_POM1PCIAL         (PCIX0_CFGBASE + 0x0088)
3994 #define PCIX0_POM1PCIAH         (PCIX0_CFGBASE + 0x008c)
3995 #define PCIX0_POM2SA            (PCIX0_CFGBASE + 0x0090)
3996
3997 #define PCIX0_PIM0SA            (PCIX0_CFGBASE + 0x0098)
3998 #define PCIX0_PIM0LAL           (PCIX0_CFGBASE + 0x009c)
3999 #define PCIX0_PIM0LAH           (PCIX0_CFGBASE + 0x00a0)
4000 #define PCIX0_PIM1SA            (PCIX0_CFGBASE + 0x00a4)
4001 #define PCIX0_PIM1LAL           (PCIX0_CFGBASE + 0x00a8)
4002 #define PCIX0_PIM1LAH           (PCIX0_CFGBASE + 0x00ac)
4003 #define PCIX0_PIM2SA            (PCIX0_CFGBASE + 0x00b0)
4004 #define PCIX0_PIM2LAL           (PCIX0_CFGBASE + 0x00b4)
4005 #define PCIX0_PIM2LAH           (PCIX0_CFGBASE + 0x00b8)
4006
4007 #define PCIX0_STS               (PCIX0_CFGBASE + 0x00e0)
4008
4009 #endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */
4010
4011 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
4012
4013 /* USB2.0 Device */
4014 #define USB2D0_BASE         CFG_USB2D0_BASE
4015
4016 #define USB2D0_INTRIN       (USB2D0_BASE + 0x00000000)
4017
4018 #define USB2D0_INTRIN       (USB2D0_BASE + 0x00000000) /* Interrupt register for Endpoint 0 plus IN Endpoints 1 to 3 */
4019 #define USB2D0_POWER        (USB2D0_BASE + 0x00000000) /* Power management register */
4020 #define USB2D0_FADDR        (USB2D0_BASE + 0x00000000) /* Function address register */
4021 #define USB2D0_INTRINE      (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRIN */
4022 #define USB2D0_INTROUT      (USB2D0_BASE + 0x00000000) /* Interrupt register for OUT Endpoints 1 to 3 */
4023 #define USB2D0_INTRUSBE     (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRUSB */
4024 #define USB2D0_INTRUSB      (USB2D0_BASE + 0x00000000) /* Interrupt register for common USB interrupts */
4025 #define USB2D0_INTROUTE     (USB2D0_BASE + 0x00000000) /* Interrupt enable register for IntrOut */
4026 #define USB2D0_TSTMODE      (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 test modes */
4027 #define USB2D0_INDEX        (USB2D0_BASE + 0x00000000) /* Index register for selecting the Endpoint status/control registers */
4028 #define USB2D0_FRAME        (USB2D0_BASE + 0x00000000) /* Frame number */
4029 #define USB2D0_INCSR0       (USB2D0_BASE + 0x00000000) /* Control Status register for Endpoint 0. (Index register set to select Endpoint 0) */
4030 #define USB2D0_INCSR        (USB2D0_BASE + 0x00000000) /* Control Status register for IN Endpoint. (Index register set to select Endpoints 13) */
4031 #define USB2D0_INMAXP       (USB2D0_BASE + 0x00000000) /* Maximum packet size for IN Endpoint. (Index register set to select Endpoints 13) */
4032 #define USB2D0_OUTCSR       (USB2D0_BASE + 0x00000000) /* Control Status register for OUT Endpoint. (Index register set to select Endpoints 13) */
4033 #define USB2D0_OUTMAXP      (USB2D0_BASE + 0x00000000) /* Maximum packet size for OUT Endpoint. (Index register set to select Endpoints 13) */
4034 #define USB2D0_OUTCOUNT0    (USB2D0_BASE + 0x00000000) /* Number of received bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */
4035 #define USB2D0_OUTCOUNT     (USB2D0_BASE + 0x00000000) /* Number of bytes in OUT Endpoint FIFO. (Index register set to select Endpoints 13) */
4036 #endif
4037
4038 /******************************************************************************
4039  * GPIO macro register defines
4040  ******************************************************************************/
4041 #if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
4042     defined(CONFIG_440SP) || defined(CONFIG_440SPE)
4043 #define GPIO0_BASE             (CFG_PERIPHERAL_BASE+0x00000700)
4044
4045 #define GPIO0_OR               (GPIO0_BASE+0x0)
4046 #define GPIO0_TCR              (GPIO0_BASE+0x4)
4047 #define GPIO0_ODR              (GPIO0_BASE+0x18)
4048 #define GPIO0_IR               (GPIO0_BASE+0x1C)
4049 #endif /* CONFIG_440GP */
4050
4051 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
4052     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
4053     defined(CONFIG_460EX) || defined(CONFIG_460GT)
4054 #define GPIO0_BASE             (CFG_PERIPHERAL_BASE+0x00000B00)
4055 #define GPIO1_BASE             (CFG_PERIPHERAL_BASE+0x00000C00)
4056
4057 #define GPIO0_OR               (GPIO0_BASE+0x0)
4058 #define GPIO0_TCR              (GPIO0_BASE+0x4)
4059 #define GPIO0_OSRL             (GPIO0_BASE+0x8)
4060 #define GPIO0_OSRH             (GPIO0_BASE+0xC)
4061 #define GPIO0_TSRL             (GPIO0_BASE+0x10)
4062 #define GPIO0_TSRH             (GPIO0_BASE+0x14)
4063 #define GPIO0_ODR              (GPIO0_BASE+0x18)
4064 #define GPIO0_IR               (GPIO0_BASE+0x1C)
4065 #define GPIO0_RR1              (GPIO0_BASE+0x20)
4066 #define GPIO0_RR2              (GPIO0_BASE+0x24)
4067 #define GPIO0_RR3              (GPIO0_BASE+0x28)
4068 #define GPIO0_ISR1L            (GPIO0_BASE+0x30)
4069 #define GPIO0_ISR1H            (GPIO0_BASE+0x34)
4070 #define GPIO0_ISR2L            (GPIO0_BASE+0x38)
4071 #define GPIO0_ISR2H            (GPIO0_BASE+0x3C)
4072 #define GPIO0_ISR3L            (GPIO0_BASE+0x40)
4073 #define GPIO0_ISR3H            (GPIO0_BASE+0x44)
4074
4075 #define GPIO1_OR               (GPIO1_BASE+0x0)
4076 #define GPIO1_TCR              (GPIO1_BASE+0x4)
4077 #define GPIO1_OSRL             (GPIO1_BASE+0x8)
4078 #define GPIO1_OSRH             (GPIO1_BASE+0xC)
4079 #define GPIO1_TSRL             (GPIO1_BASE+0x10)
4080 #define GPIO1_TSRH             (GPIO1_BASE+0x14)
4081 #define GPIO1_ODR              (GPIO1_BASE+0x18)
4082 #define GPIO1_IR               (GPIO1_BASE+0x1C)
4083 #define GPIO1_RR1              (GPIO1_BASE+0x20)
4084 #define GPIO1_RR2              (GPIO1_BASE+0x24)
4085 #define GPIO1_RR3              (GPIO1_BASE+0x28)
4086 #define GPIO1_ISR1L            (GPIO1_BASE+0x30)
4087 #define GPIO1_ISR1H            (GPIO1_BASE+0x34)
4088 #define GPIO1_ISR2L            (GPIO1_BASE+0x38)
4089 #define GPIO1_ISR2H            (GPIO1_BASE+0x3C)
4090 #define GPIO1_ISR3L            (GPIO1_BASE+0x40)
4091 #define GPIO1_ISR3H            (GPIO1_BASE+0x44)
4092 #endif
4093
4094 #ifndef __ASSEMBLY__
4095
4096 static inline u32 get_mcsr(void)
4097 {
4098         u32 val;
4099
4100         asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
4101         return val;
4102 }
4103
4104 static inline void set_mcsr(u32 val)
4105 {
4106         asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
4107 }
4108
4109 #endif  /* _ASMLANGUAGE */
4110
4111 #endif  /* __PPC440_H__ */