include/pcf50633.h

   1 #ifndef _PCF50633_H
   2 #define _PCF50633_H
   3
   4 /* Philips PCF50633 Power Managemnt Unit (PMU) driver
   5  * (C) 2006-2007 by OpenMoko, Inc.
   6  * Author: Harald Welte <laforge@openmoko.org>
   7  *
   8  */
   9
  10 enum pfc50633_regs {
  11         PCF50633_REG_VERSION    = 0x00,
  12         PCF50633_REG_VARIANT    = 0x01,
  13         PCF50633_REG_INT1       = 0x02, /* Interrupt Status */
  14         PCF50633_REG_INT2       = 0x03, /* Interrupt Status */
  15         PCF50633_REG_INT3       = 0x04, /* Interrupt Status */
  16         PCF50633_REG_INT4       = 0x05, /* Interrupt Status */
  17         PCF50633_REG_INT5       = 0x06, /* Interrupt Status */
  18         PCF50633_REG_INT1M      = 0x07, /* Interrupt Mask */
  19         PCF50633_REG_INT2M      = 0x08, /* Interrupt Mask */
  20         PCF50633_REG_INT3M      = 0x09, /* Interrupt Mask */
  21         PCF50633_REG_INT4M      = 0x0a, /* Interrupt Mask */
  22         PCF50633_REG_INT5M      = 0x0b, /* Interrupt Mask */
  23         PCF50633_REG_OOCSHDWN   = 0x0c,
  24         PCF50633_REG_OOCWAKE    = 0x0d,
  25         PCF50633_REG_OOCTIM1    = 0x0e,
  26         PCF50633_REG_OOCTIM2    = 0x0f,
  27         PCF50633_REG_OOCMODE    = 0x10,
  28         PCF50633_REG_OOCCTL     = 0x11,
  29         PCF50633_REG_OOCSTAT    = 0x12,
  30         PCF50633_REG_GPIOCTL    = 0x13,
  31         PCF50633_REG_GPIO1CFG   = 0x14,
  32         PCF50633_REG_GPIO2CFG   = 0x15,
  33         PCF50633_REG_GPIO3CFG   = 0x16,
  34         PCF50633_REG_GPOCFG     = 0x17,
  35         PCF50633_REG_BVMCTL     = 0x18,
  36         PCF50633_REG_SVMCTL     = 0x19,
  37         PCF50633_REG_AUTOOUT    = 0x1a,
  38         PCF50633_REG_AUTOENA    = 0x1b,
  39         PCF50633_REG_AUTOCTL    = 0x1c,
  40         PCF50633_REG_AUTOMXC    = 0x1d,
  41         PCF50633_REG_DOWN1OUT   = 0x1e,
  42         PCF50633_REG_DOWN1ENA   = 0x1f,
  43         PCF50633_REG_DOWN1CTL   = 0x20,
  44         PCF50633_REG_DOWN1MXC   = 0x21,
  45         PCF50633_REG_DOWN2OUT   = 0x22,
  46         PCF50633_REG_DOWN2ENA   = 0x23,
  47         PCF50633_REG_DOWN2CTL   = 0x24,
  48         PCF50633_REG_DOWN2MXC   = 0x25,
  49         PCF50633_REG_MEMLDOOUT  = 0x26,
  50         PCF50633_REG_MEMLDOENA  = 0x27,
  51         PCF50633_REG_LEDOUT     = 0x28,
  52         PCF50633_REG_LEDENA     = 0x29,
  53         PCF50633_REG_LEDCTL     = 0x2a,
  54         PCF50633_REG_LEDDIM     = 0x2b,
  55         /* reserved */
  56         PCF50633_REG_LDO1OUT    = 0x2d,
  57         PCF50633_REG_LDO1ENA    = 0x2e,
  58         PCF50633_REG_LDO2OUT    = 0x2f,
  59         PCF50633_REG_LDO2ENA    = 0x30,
  60         PCF50633_REG_LDO3OUT    = 0x31,
  61         PCF50633_REG_LDO3ENA    = 0x32,
  62         PCF50633_REG_LDO4OUT    = 0x33,
  63         PCF50633_REG_LDO4ENA    = 0x34,
  64         PCF50633_REG_LDO5OUT    = 0x35,
  65         PCF50633_REG_LDO5ENA    = 0x36,
  66         PCF50633_REG_LDO6OUT    = 0x37,
  67         PCF50633_REG_LDO6ENA    = 0x38,
  68         PCF50633_REG_HCLDOOUT   = 0x39,
  69         PCF50633_REG_HCLDOENA   = 0x3a,
  70         PCF50633_REG_STBYCTL1   = 0x3b,
  71         PCF50633_REG_STBYCTL2   = 0x3c,
  72         PCF50633_REG_DEBPF1     = 0x3d,
  73         PCF50633_REG_DEBPF2     = 0x3e,
  74         PCF50633_REG_DEBPF3     = 0x3f,
  75         PCF50633_REG_HCLDOOVL   = 0x40,
  76         PCF50633_REG_DCDCSTAT   = 0x41,
  77         PCF50633_REG_LDOSTAT    = 0x42,
  78         PCF50633_REG_MBCC1      = 0x43,
  79         PCF50633_REG_MBCC2      = 0x44,
  80         PCF50633_REG_MBCC3      = 0x45,
  81         PCF50633_REG_MBCC4      = 0x46,
  82         PCF50633_REG_MBCC5      = 0x47,
  83         PCF50633_REG_MBCC6      = 0x48,
  84         PCF50633_REG_MBCC7      = 0x49,
  85         PCF50633_REG_MBCC8      = 0x4a,
  86         PCF50633_REG_MBCS1      = 0x4b,
  87         PCF50633_REG_MBCS2      = 0x4c,
  88         PCF50633_REG_MBCS3      = 0x4d,
  89         PCF50633_REG_BBCCTL     = 0x4e,
  90         PCF50633_REG_ALMGAIN    = 0x4f,
  91         PCF50633_REG_ALMDATA    = 0x50,
  92         /* reserved */
  93         PCF50633_REG_ADCC3      = 0x52,
  94         PCF50633_REG_ADCC2      = 0x53,
  95         PCF50633_REG_ADCC1      = 0x54,
  96         PCF50633_REG_ADCS1      = 0x55,
  97         PCF50633_REG_ADCS2      = 0x56,
  98         PCF50633_REG_ADCS3      = 0x57,
  99         /* reserved */
 100         PCF50633_REG_RTCSC      = 0x59, /* Second */
 101         PCF50633_REG_RTCMN      = 0x5a, /* Minute */
 102         PCF50633_REG_RTCHR      = 0x5b, /* Hour */
 103         PCF50633_REG_RTCWD      = 0x5c, /* Weekday */
 104         PCF50633_REG_RTCDT      = 0x5d, /* Day */
 105         PCF50633_REG_RTCMT      = 0x5e, /* Month */
 106         PCF50633_REG_RTCYR      = 0x5f, /* Year */
 107         PCF50633_REG_RTCSCA     = 0x60, /* Alarm Second */
 108         PCF50633_REG_RTCMNA     = 0x61, /* Alarm Minute */
 109         PCF50633_REG_RTCHRA     = 0x62, /* Alarm Hour */
 110         PCF50633_REG_RTCWDA     = 0x63, /* Alarm Weekday */
 111         PCF50633_REG_RTCDTA     = 0x64, /* Alarm Day */
 112         PCF50633_REG_RTCMTA     = 0x65, /* Alarm Month */
 113         PCF50633_REG_RTCYRA     = 0x66, /* Alarm Year */
 114
 115         PCF50633_REG_MEMBYTE0   = 0x67,
 116         PCF50633_REG_MEMBYTE1   = 0x68,
 117         PCF50633_REG_MEMBYTE2   = 0x69,
 118         PCF50633_REG_MEMBYTE3   = 0x6a,
 119         PCF50633_REG_MEMBYTE4   = 0x6b,
 120         PCF50633_REG_MEMBYTE5   = 0x6c,
 121         PCF50633_REG_MEMBYTE6   = 0x6d,
 122         PCF50633_REG_MEMBYTE7   = 0x6e,
 123         /* reserved */
 124         PCF50633_REG_DCDCPFM    = 0x84,
 125         __NUM_PCF50633_REGS
 126 };
 127
 128 enum pcf50633_reg_int1 {
 129         PCF50633_INT1_ADPINS    = 0x01, /* Adapter inserted */
 130         PCF50633_INT1_ADPREM    = 0x02, /* Adapter removed */
 131         PCF50633_INT1_USBINS    = 0x04, /* USB inserted */
 132         PCF50633_INT1_USBREM    = 0x08, /* USB removed */
 133         /* reserved */
 134         PCF50633_INT1_ALARM     = 0x40, /* RTC alarm time is reached */
 135         PCF50633_INT1_SECOND    = 0x80, /* RTC periodic second interrupt */
 136 };
 137
 138 enum pcf50633_reg_int2 {
 139         PCF50633_INT2_ONKEYR    = 0x01, /* ONKEY rising edge */
 140         PCF50633_INT2_ONKEYF    = 0x02, /* ONKEY falling edge */
 141         PCF50633_INT2_EXTON1R   = 0x04, /* EXTON1 rising edge */
 142         PCF50633_INT2_EXTON1F   = 0x08, /* EXTON1 falling edge */
 143         PCF50633_INT2_EXTON2R   = 0x10, /* EXTON2 rising edge */
 144         PCF50633_INT2_EXTON2F   = 0x20, /* EXTON2 falling edge */
 145         PCF50633_INT2_EXTON3R   = 0x40, /* EXTON3 rising edge */
 146         PCF50633_INT2_EXTON3F   = 0x80, /* EXTON3 falling edge */
 147 };
 148
 149 enum pcf50633_reg_int3 {
 150         PCF50633_INT3_BATFULL   = 0x01, /* Battery full */
 151         PCF50633_INT3_CHGHALT   = 0x02, /* Charger halt */
 152         PCF50633_INT3_THLIMON   = 0x04,
 153         PCF50633_INT3_THLIMOFF  = 0x08,
 154         PCF50633_INT3_USBLIMON  = 0x10,
 155         PCF50633_INT3_USBLIMOFF = 0x20,
 156         PCF50633_INT3_ADCRDY    = 0x40, /* ADC conversion finished */
 157         PCF50633_INT3_ONKEY1S   = 0x80, /* ONKEY pressed 1 second */
 158 };
 159
 160 enum pcf50633_reg_int4 {
 161         PCF50633_INT4_LOWSYS            = 0x01,
 162         PCF50633_INT4_LOWBAT            = 0x02,
 163         PCF50633_INT4_HIGHTMP           = 0x04,
 164         PCF50633_INT4_AUTOPWRFAIL       = 0x08,
 165         PCF50633_INT4_DWN1PWRFAIL       = 0x10,
 166         PCF50633_INT4_DWN2PWRFAIL       = 0x20,
 167         PCF50633_INT4_LEDPWRFAIL        = 0x40,
 168         PCF50633_INT4_LEDOVP            = 0x80,
 169 };
 170
 171 enum pcf50633_reg_int5 {
 172         PCF50633_INT4_LDO1PWRFAIL       = 0x01,
 173         PCF50633_INT4_LDO2PWRFAIL       = 0x02,
 174         PCF50633_INT4_LDO3PWRFAIL       = 0x04,
 175         PCF50633_INT4_LDO4PWRFAIL       = 0x08,
 176         PCF50633_INT4_LDO5PWRFAIL       = 0x10,
 177         PCF50633_INT4_LDO6PWRFAIL       = 0x20,
 178         PCF50633_INT4_HCLDOPWRFAIL      = 0x40,
 179         PCF50633_INT4_HCLDOOVL          = 0x80,
 180 };
 181
 182 enum pcf50633_reg_oocwake {
 183         PCF50633_OOCWAKE_ONKEY          = 0x01,
 184         PCF50633_OOCWAKE_EXTON1         = 0x02,
 185         PCF50633_OOCWAKE_EXTON2         = 0x04,
 186         PCF50633_OOCWAKE_EXTON3         = 0x08,
 187         PCF50633_OOCWAKE_RTC            = 0x10,
 188         /* reserved */
 189         PCF50633_OOCWAKE_USB            = 0x40,
 190         PCF50633_OOCWAKE_ADP            = 0x80,
 191 };
 192
 193 enum pcf50633_reg_mbcc1 {
 194         PCF50633_MBCC1_CHGENA           = 0x01, /* Charger enable */
 195         PCF50633_MBCC1_AUTOSTOP         = 0x02,
 196         PCF50633_MBCC1_AUTORES          = 0x04, /* automatic resume */
 197         PCF50633_MBCC1_RESUME           = 0x08, /* explicit resume cmd */
 198         PCF50633_MBCC1_RESTART          = 0x10, /* restart charging */
 199         PCF50633_MBCC1_PREWDTIME_60M    = 0x20, /* max. precharging time */
 200         PCF50633_MBCC1_WDTIME_1H        = 0x00,
 201         PCF50633_MBCC1_WDTIME_2H        = 0x40,
 202         PCF50633_MBCC1_WDTIME_4H        = 0x80,
 203         PCF50633_MBCC1_WDTIME_6H        = 0xc0,
 204 };
 205 #define PCF50633_MBCC1_WDTIME_MASK        0xc0
 206
 207 enum pcf50633_reg_mbcc2 {
 208         PCF50633_MBCC2_VBATCOND_2V7     = 0x00,
 209         PCF50633_MBCC2_VBATCOND_2V85    = 0x01,
 210         PCF50633_MBCC2_VBATCOND_3V      = 0x02,
 211         PCF50633_MBCC2_VBATCOND_3V15    = 0x03,
 212         PCF50633_MBCC2_VMAX_4V          = 0x00,
 213         PCF50633_MBCC2_VMAX_4V20        = 0x28,
 214         PCF50633_MBCC2_VRESDEBTIME_64S  = 0x80, /* debounce time (32/64sec) */
 215 };
 216 #define PCF50633_MBCC2_VBATCOND_MASK      0x03
 217 #define PCF50633_MBCC2_VMAX_MASK          0x3c
 218
 219 #define PCF50633_OOCSTAT_ONKEY          0x01
 220
 221
 222 enum pcf50633_reg_adcc1 {
 223         PCF50633_ADCC1_ADCSTART         = 0x01,
 224         PCF50633_ADCC1_RES_10BIT        = 0x02,
 225         PCF50633_ADCC1_AVERAGE_NO       = 0x00,
 226         PCF50633_ADCC1_AVERAGE_4        = 0x04,
 227         PCF50633_ADCC1_AVERAGE_8        = 0x08,
 228         PCF50633_ADCC1_AVERAGE_16       = 0x0c,
 229
 230         PCF50633_ADCC1_MUX_BATSNS_RES   = 0x00,
 231         PCF50633_ADCC1_MUX_BATSNS_SUBTR = 0x10,
 232         PCF50633_ADCC1_MUX_ADCIN2_RES   = 0x20,
 233         PCF50633_ADCC1_MUX_ADCIN2_SUBTR = 0x30,
 234         PCF50633_ADCC1_MUX_BATTEMP      = 0x60,
 235         PCF50633_ADCC1_MUX_ADCIN1       = 0x70,
 236 };
 237 #define PCF50633_ADCC1_AVERAGE_MASK     0x0c
 238 #define PCF50633_ADCC1_ADCMUX_MASK      0xf0
 239
 240 enum pcf50633_reg_adcc2 {
 241         PCF50633_ADCC2_RATIO_NONE       = 0x00,
 242         PCF50633_ADCC2_RATIO_BATTEMP    = 0x01,
 243         PCF50633_ADCC2_RATIO_ADCIN1     = 0x02,
 244         PCF50633_ADCC2_RATIO_BOTH       = 0x03,
 245         PCF50633_ADCC2_RATIOSETTL_100US = 0x04,
 246 };
 247 #define PCF50633_ADCC2_RATIO_MASK       0x03
 248
 249 enum pcf50633_reg_adcc3 {
 250         PCF50633_ADCC3_ACCSW_EN         = 0x01,
 251         PCF50633_ADCC3_NTCSW_EN         = 0x04,
 252         PCF50633_ADCC3_RES_DIV_TWO      = 0x10,
 253         PCF50633_ADCC3_RES_DIV_THREE    = 0x00,
 254 };
 255
 256 enum pcf50633_reg_adcs3 {
 257         PCF50633_ADCS3_REF_NTCSW        = 0x00,
 258         PCF50633_ADCS3_REF_ACCSW        = 0x10,
 259         PCF50633_ADCS3_REF_2V0          = 0x20,
 260         PCF50633_ADCS3_REF_VISA         = 0x30,
 261         PCF50633_ADCS3_REF_2V0_2        = 0x70,
 262         PCF50633_ADCS3_ADCRDY           = 0x80,
 263 };
 264 #define PCF50633_ADCS3_ADCDAT1L_MASK    0x03
 265 #define PCF50633_ADCS3_ADCDAT2L_MASK    0x0c
 266 #define PCF50633_ADCS3_ADCDAT2L_SHIFT   2
 267 #define PCF50633_ASCS3_REF_MASK         0x70
 268
 269 enum pcf50633_regulator_enable {
 270         PCF50633_REGULATOR_ON           = 0x01,
 271         PCF50633_REGULATOR_ON_GPIO1     = 0x02,
 272         PCF50633_REGULATOR_ON_GPIO2     = 0x04,
 273         PCF50633_REGULATOR_ON_GPIO3     = 0x08,
 274 };
 275 #define PCF50633_REGULATOR_ON_MASK      0x0f
 276
 277 enum pcf50633_regulator_phase {
 278         PCF50633_REGULATOR_ACTPH1       = 0x00,
 279         PCF50633_REGULATOR_ACTPH2       = 0x10,
 280         PCF50633_REGULATOR_ACTPH3       = 0x20,
 281         PCF50633_REGULATOR_ACTPH4       = 0x30,
 282 };
 283 #define PCF50633_REGULATOR_ACTPH_MASK   0x30
 284
 285 enum pcf50633_reg_gpocfg {
 286         PCF50633_GPOCFG_GPOSEL_0        = 0x00,
 287         PCF50633_GPOCFG_GPOSEL_LED_NFET = 0x01,
 288         PCF50633_GPOCFG_GPOSEL_SYSxOK   = 0x02,
 289         PCF50633_GPOCFG_GPOSEL_CLK32K   = 0x03,
 290         PCF50633_GPOCFG_GPOSEL_ADAPUSB  = 0x04,
 291         PCF50633_GPOCFG_GPOSEL_USBxOK   = 0x05,
 292         PCF50633_GPOCFG_GPOSEL_ACTPH4   = 0x06,
 293         PCF50633_GPOCFG_GPOSEL_1        = 0x07,
 294         PCF50633_GPOCFG_GPOSEL_INVERSE  = 0x08,
 295 };
 296 #define PCF50633_GPOCFG_GPOSEL_MASK     0x07
 297
 298 #if 0
 299 enum pcf50633_reg_mbcc1 {
 300         PCF50633_MBCC1_CHGENA           = 0x01,
 301         PCF50633_MBCC1_AUTOSTOP         = 0x02,
 302         PCF50633_MBCC1_AUTORES          = 0x04,
 303         PCF50633_MBCC1_RESUME           = 0x08,
 304         PCF50633_MBCC1_RESTART          = 0x10,
 305         PCF50633_MBCC1_PREWDTIME_30MIN  = 0x00,
 306         PCF50633_MBCC1_PREWDTIME_60MIN  = 0x20,
 307         PCF50633_MBCC1_WDTIME_2HRS      = 0x40,
 308         PCF50633_MBCC1_WDTIME_4HRS      = 0x80,
 309         PCF50633_MBCC1_WDTIME_6HRS      = 0xc0,
 310 };
 311
 312 enum pcf50633_reg_mbcc2 {
 313         PCF50633_MBCC2_VBATCOND_2V7     = 0x00,
 314         PCF50633_MBCC2_VBATCOND_2V85    = 0x01,
 315         PCF50633_MBCC2_VBATCOND_3V0     = 0x02,
 316         PCF50633_MBCC2_VBATCOND_3V15    = 0x03,
 317         PCF50633_MBCC2_VRESDEBTIME_64S  = 0x80,
 318 };
 319 #define PCF50633_MBCC2_VMAX_MASK        0x3c
 320 #endif
 321
 322 enum pcf50633_reg_mbcc7 {
 323         PCF50633_MBCC7_USB_100mA        = 0x00,
 324         PCF50633_MBCC7_USB_500mA        = 0x01,
 325         PCF50633_MBCC7_USB_1000mA       = 0x02,
 326         PCF50633_MBCC7_USB_SUSPEND      = 0x03,
 327         PCF50633_MBCC7_BATTEMP_EN       = 0x04,
 328         PCF50633_MBCC7_BATSYSIMAX_1A6   = 0x00,
 329         PCF50633_MBCC7_BATSYSIMAX_1A8   = 0x40,
 330         PCF50633_MBCC7_BATSYSIMAX_2A0   = 0x80,
 331         PCF50633_MBCC7_BATSYSIMAX_2A2   = 0xc0,
 332 };
 333 #define PCF56033_MBCC7_USB_MASK         0x03
 334
 335 enum pcf50633_reg_mbcc8 {
 336         PCF50633_MBCC8_USBENASUS        = 0x10,
 337 };
 338
 339 enum pcf50633_reg_mbcs1 {
 340         PCF50633_MBCS1_USBPRES          = 0x01,
 341         PCF50633_MBCS1_USBOK            = 0x02,
 342         PCF50633_MBCS1_ADAPTPRES        = 0x04,
 343         PCF50633_MBCS1_ADAPTOK          = 0x08,
 344         PCF50633_MBCS1_TBAT_OK          = 0x00,
 345         PCF50633_MBCS1_TBAT_ABOVE       = 0x10,
 346         PCF50633_MBCS1_TBAT_BELOW       = 0x20,
 347         PCF50633_MBCS1_TBAT_UNDEF       = 0x30,
 348         PCF50633_MBCS1_PREWDTEXP        = 0x40,
 349         PCF50633_MBCS1_WDTEXP           = 0x80,
 350 };
 351
 352 enum pcf50633_reg_mbcs2_mbcmod {
 353         PCF50633_MBCS2_MBC_PLAY         = 0x00,
 354         PCF50633_MBCS2_MBC_USB_PRE      = 0x01,
 355         PCF50633_MBCS2_MBC_USB_PRE_WAIT = 0x02,
 356         PCF50633_MBCS2_MBC_USB_FAST     = 0x03,
 357         PCF50633_MBCS2_MBC_USB_FAST_WAIT= 0x04,
 358         PCF50633_MBCS2_MBC_USB_SUSPEND  = 0x05,
 359         PCF50633_MBCS2_MBC_ADP_PRE      = 0x06,
 360         PCF50633_MBCS2_MBC_ADP_PRE_WAIT = 0x07,
 361         PCF50633_MBCS2_MBC_ADP_FAST     = 0x08,
 362         PCF50633_MBCS2_MBC_ADP_FAST_WAIT= 0x09,
 363         PCF50633_MBCS2_MBC_BAT_FULL     = 0x0a,
 364         PCF50633_MBCS2_MBC_HALT         = 0x0b,
 365 };
 366 #define PCF50633_MBCS2_MBC_MASK         0x0f
 367 enum pcf50633_reg_mbcs2_chgstat {
 368         PCF50633_MBCS2_CHGS_NONE        = 0x00,
 369         PCF50633_MBCS2_CHGS_ADAPTER     = 0x10,
 370         PCF50633_MBCS2_CHGS_USB         = 0x20,
 371         PCF50633_MBCS2_CHGS_BOTH        = 0x30,
 372 };
 373 #define PCF50633_MBCS2_RESSTAT_AUTO     0x40
 374
 375 enum pcf50633_reg_mbcs3 {
 376         PCF50633_MBCS3_USBLIM_PLAY      = 0x01,
 377         PCF50633_MBCS3_USBLIM_CGH       = 0x02,
 378         PCF50633_MBCS3_TLIM_PLAY        = 0x04,
 379         PCF50633_MBCS3_TLIM_CHG         = 0x08,
 380         PCF50633_MBCS3_ILIM             = 0x10, /* 1: Ibat > Icutoff */
 381         PCF50633_MBCS3_VLIM             = 0x20, /* 1: Vbat == Vmax */
 382         PCF50633_MBCS3_VBATSTAT         = 0x40, /* 1: Vbat > Vbatcond */
 383         PCF50633_MBCS3_VRES             = 0x80, /* 1: Vbat > Vth(RES) */
 384 };
 385
 386
 387 /* this is to be provided by the board implementation */
 388 extern const u_int8_t pcf50633_initial_regs[__NUM_PCF50633_REGS];
 389
 390 extern int pcf50633_usb_last_maxcurrent; /* mA or -1 if unknown */
 391
 392 void pcf50633_reg_write(u_int8_t reg, u_int8_t val);
 393
 394 u_int8_t pcf50633_reg_read(u_int8_t reg);
 395
 396 void pcf50633_reg_set_bit_mask(u_int8_t reg, u_int8_t mask, u_int8_t val);
 397 void pcf50633_reg_clear_bits(u_int8_t reg, u_int8_t bits);
 398
 399 void pcf50633_init(void);
 400 void pcf50633_usb_maxcurrent(unsigned int ma);
 401
 402 const char *pcf50633_charger_state(void);
 403
 404 int pcf50633_read_charger_type(void);
 405 u_int16_t pcf50633_read_battvolt(void);
 406
 407 #endif /* _PCF50633_H */
 408