add SDHC support in mmc driver
[u-boot-openmoko/mini2440.git] / include / nios.h
blob46b685ab9d55f29b1c946bc248cab55ed985fd9e
1 /*
2 * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
3 * Scott McNutt <smcnutt@psyent.com>
5 * See file CREDITS for list of people who contributed to this
6 * project.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
24 #ifndef __NIOS_H__
25 #define __NIOS_H__
27 /*------------------------------------------------------------------------
28 * Control registers -- use with wrctl() & rdctl()
29 *----------------------------------------------------------------------*/
30 #define CTL_STATUS 0x00 /* Processor status */
31 #define CTL_ISTATUS 0x01 /* Saved status (exception) */
32 #define CTL_WVALID 0x02 /* Valid window limit */
33 #define CTL_ICACHE 0x05 /* I-cache line-invalidate */
34 #define CTL_CPU_ID 0x06 /* CPU version id */
35 #define CTL_DCACHE 0x07 /* D-cache line-invalidate */
36 #define CTL_CLR_IE 0x08 /* Interrupt clear (disable) */
37 #define CTL_SET_IE 0x09 /* Interrupt set (enable) */
39 /*------------------------------------------------------------------------
40 * Access to control regs
41 *----------------------------------------------------------------------*/
42 #define _str_(s) #s
44 #define rdctl(reg)\
45 ({unsigned int val;\
46 asm volatile( "pfx " _str_(reg) "\n\t rdctl %0"\
47 : "=r" (val) ); val;})
49 #define wrctl(reg,val)\
50 asm volatile( "pfx " _str_(reg) "\n\t wrctl %0 \n\t nop"\
51 : : "r" (val))
53 /*------------------------------------------------------------------------
54 * Control reg bit masks
55 *----------------------------------------------------------------------*/
56 #define STATUS_DC (1<<17) /* Data cache enable */
57 #define STATUS_IC (1<<16) /* Instruction cache enable */
58 #define STATUS_IE (1<<15) /* Interrupt enable */
59 #define STATUS_IPRI (0x3f<<9) /* Interrupt priority */
60 #define STATUS_CWP (0x1f<<4) /* Current window pointer */
61 #define STATUS_N (1<<3) /* Condition code: negative */
62 #define STATUS_V (1<<2) /* Condition code: overflow */
63 #define STATUS_Z (1<<1) /* Condition code: zero */
64 #define STATUS_C (1<<0) /* Condition code: carry/borrow */
66 static inline unsigned ipri( unsigned prio )
68 unsigned tmp;
69 unsigned status = rdctl(CTL_STATUS);
70 prio = (prio << 9) & STATUS_IPRI;
71 tmp = (status & ~STATUS_IPRI) | prio;
72 wrctl(CTL_STATUS,tmp);
73 return( (status & STATUS_IPRI) >> 9);
77 #endif /* __NIOS_H__ */