include/mpc512x.h

   1 /*
   2  * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
   3  * (C) Copyright 2007 DENX Software Engineering
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * Derived from the MPC83xx header.
  14  */
  15
  16 #ifndef __MPC512X_H__
  17 #define __MPC512X_H__
  18
  19 #include <config.h>
  20 #if defined(CONFIG_E300)
  21 #include <asm/e300.h>
  22 #endif
  23
  24 /* System reset offset (PowerPC standard)
  25  */
  26 #define EXC_OFF_SYS_RESET               0x0100
  27 #define _START_OFFSET                   EXC_OFF_SYS_RESET
  28
  29
  30 /* IMMRBAR - Internal Memory Register Base Address
  31  */
  32 #define CONFIG_DEFAULT_IMMR             0xFF400000      /* Default IMMR base address */
  33 #define IMMRBAR                         0x0000          /* Register offset to immr */
  34 #define IMMRBAR_BASE_ADDR               0xFFF00000      /* Base address mask */
  35 #define IMMRBAR_RES                     ~(IMMRBAR_BASE_ADDR)
  36
  37 /* LAWBAR - Local Access Window Base Address Register
  38  */
  39 #define LPBAW                   0x0020          /* Register offset to immr */
  40 #define LPCS0AW                 0x0024
  41 #define LPCS1AW                 0x0028
  42 #define LPCS2AW                 0x002C
  43 #define LPCS3AW                 0x0030
  44 #define LPCS4AW                 0x0034
  45 #define LPCS5AW                 0x0038
  46 #define LPCS6AW                 0x003C
  47 #define LPCA7AW                 0x0040
  48 #define SRAMBAR                 0x00C4
  49 #define LAWBAR_BAR              0xFFFFF000      /* Base address mask */
  50
  51 #define LPC_OFFSET              0x10000
  52
  53 #define CS0_CONFIG              0x00000
  54 #define CS1_CONFIG              0x00004
  55 #define CS2_CONFIG              0x00008
  56 #define CS3_CONFIG              0x0000C
  57 #define CS4_CONFIG              0x00010
  58 #define CS5_CONFIG              0x00014
  59 #define CS6_CONFIG              0x00018
  60 #define CS7_CONFIG              0x0001C
  61
  62 #define CS_CTRL                 0x00020
  63 #define CS_CTRL_ME              0x01000000      /* CS Master Enable bit */
  64 #define CS_CTRL_IE              0x08000000      /* CS Interrupt Enable bit */
  65
  66 /* SPRIDR - System Part and Revision ID Register
  67  */
  68 #define SPRIDR_PARTID           0xFFFF0000      /* Part Identification */
  69 #define SPRIDR_REVID            0x0000FFFF      /* Revision Identification */
  70
  71 #define SPR_5121E               0x80180000
  72
  73 /* SPCR - System Priority Configuration Register
  74  */
  75 #define SPCR_PCIHPE                     0x10000000      /* PCI Highest Priority Enable */
  76 #define SPCR_PCIHPE_SHIFT               (31-3)
  77 #define SPCR_PCIPR                      0x03000000      /* PCI bridge system bus request priority */
  78 #define SPCR_PCIPR_SHIFT                (31-7)
  79 #define SPCR_TBEN                       0x00400000      /* E300 PowerPC core time base unit enable */
  80 #define SPCR_TBEN_SHIFT                 (31-9)
  81 #define SPCR_COREPR                     0x00300000      /* E300 PowerPC Core system bus request priority */
  82 #define SPCR_COREPR_SHIFT               (31-11)
  83
  84 /* SWCRR - System Watchdog Control Register
  85  */
  86 #define SWCRR                           0x0904          /* Register offset to immr */
  87 #define SWCRR_SWTC                      0xFFFF0000      /* Software Watchdog Time Count */
  88 #define SWCRR_SWEN                      0x00000004      /* Watchdog Enable bit */
  89 #define SWCRR_SWRI                      0x00000002      /* Software Watchdog Reset/Interrupt Select bit */
  90 #define SWCRR_SWPR                      0x00000001      /* Software Watchdog Counter Prescale bit */
  91 #define SWCRR_RES                       ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
  92
  93 /* SWCNR - System Watchdog Counter Register
  94  */
  95 #define SWCNR                           0x0908          /* Register offset to immr */
  96 #define SWCNR_SWCN                      0x0000FFFF      /* Software Watchdog Count mask */
  97 #define SWCNR_RES                       ~(SWCNR_SWCN)
  98
  99 /* SWSRR - System Watchdog Service Register
 100  */
 101 #define SWSRR                           0x090E          /* Register offset to immr */
 102
 103 /* ACR - Arbiter Configuration Register
 104  */
 105 #define ACR_COREDIS                     0x10000000      /* Core disable */
 106 #define ACR_COREDIS_SHIFT               (31-7)
 107 #define ACR_PIPE_DEP                    0x00070000      /* Pipeline depth */
 108 #define ACR_PIPE_DEP_SHIFT              (31-15)
 109 #define ACR_PCI_RPTCNT                  0x00007000      /* PCI repeat count */
 110 #define ACR_PCI_RPTCNT_SHIFT            (31-19)
 111 #define ACR_RPTCNT                      0x00000700      /* Repeat count */
 112 #define ACR_RPTCNT_SHIFT                (31-23)
 113 #define ACR_APARK                       0x00000030      /* Address parking */
 114 #define ACR_APARK_SHIFT                 (31-27)
 115 #define ACR_PARKM                       0x0000000F      /* Parking master */
 116 #define ACR_PARKM_SHIFT                 (31-31)
 117
 118 /* ATR - Arbiter Timers Register
 119  */
 120 #define ATR_DTO                         0x00FF0000      /* Data time out */
 121 #define ATR_ATO                         0x000000FF      /* Address time out */
 122
 123 /* AER - Arbiter Event Register
 124  */
 125 #define AER_ETEA                        0x00000020      /* Transfer error */
 126 #define AER_RES                         0x00000010      /* Reserved transfer type */
 127 #define AER_ECW                         0x00000008      /* External control word transfer type */
 128 #define AER_AO                          0x00000004      /* Address Only transfer type */
 129 #define AER_DTO                         0x00000002      /* Data time out */
 130 #define AER_ATO                         0x00000001      /* Address time out */
 131
 132 /* AEATR - Arbiter Event Address Register
 133  */
 134 #define AEATR_EVENT                     0x07000000      /* Event type */
 135 #define AEATR_MSTR_ID                   0x001F0000      /* Master Id */
 136 #define AEATR_TBST                      0x00000800      /* Transfer burst */
 137 #define AEATR_TSIZE                     0x00000700      /* Transfer Size */
 138 #define AEATR_TTYPE                     0x0000001F      /* Transfer Type */
 139
 140 /* RSR - Reset Status Register
 141  */
 142 #define RSR_SWSR                        0x00002000      /* software soft reset */
 143 #define RSR_SWSR_SHIFT                  13
 144 #define RSR_SWHR                        0x00001000      /* software hard reset */
 145 #define RSR_SWHR_SHIFT                  12
 146 #define RSR_JHRS                        0x00000200      /* jtag hreset */
 147 #define RSR_JHRS_SHIFT                  9
 148 #define RSR_JSRS                        0x00000100      /* jtag sreset status */
 149 #define RSR_JSRS_SHIFT                  8
 150 #define RSR_CSHR                        0x00000010      /* checkstop reset status */
 151 #define RSR_CSHR_SHIFT                  4
 152 #define RSR_SWRS                        0x00000008      /* software watchdog reset status */
 153 #define RSR_SWRS_SHIFT                  3
 154 #define RSR_BMRS                        0x00000004      /* bus monitop reset status */
 155 #define RSR_BMRS_SHIFT                  2
 156 #define RSR_SRS                         0x00000002      /* soft reset status */
 157 #define RSR_SRS_SHIFT                   1
 158 #define RSR_HRS                         0x00000001      /* hard reset status */
 159 #define RSR_HRS_SHIFT                   0
 160 #define RSR_RES                         ~(RSR_SWSR | RSR_SWHR |\
 161                                          RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\
 162                                          RSR_BMRS | RSR_SRS | RSR_HRS)
 163 /* RMR - Reset Mode Register
 164  */
 165 #define RMR_CSRE                        0x00000001      /* checkstop reset enable */
 166 #define RMR_CSRE_SHIFT                  0
 167 #define RMR_RES                         ~(RMR_CSRE)
 168
 169 /* RCR - Reset Control Register
 170  */
 171 #define RCR_SWHR                        0x00000002      /* software hard reset */
 172 #define RCR_SWSR                        0x00000001      /* software soft reset */
 173 #define RCR_RES                         ~(RCR_SWHR | RCR_SWSR)
 174
 175 /* RCER - Reset Control Enable Register
 176  */
 177 #define RCER_CRE                        0x00000001      /* software hard reset */
 178 #define RCER_RES                        ~(RCER_CRE)
 179
 180 /* SPMR - System PLL Mode Register
 181  */
 182 #define SPMR_SPMF                       0x0F000000
 183 #define SPMR_SPMF_SHIFT                 24
 184 #define SPMR_CPMF                       0x000F0000
 185 #define SPMR_CPMF_SHIFT                 16
 186
 187 /* SCFR1 System Clock Frequency Register 1
 188  */
 189 #define SCFR1_IPS_DIV                   0x3
 190 #define SCFR1_IPS_DIV_MASK              0x03800000
 191 #define SCFR1_IPS_DIV_SHIFT             23
 192
 193 #define SCFR1_PCI_DIV                   0x6
 194 #define SCFR1_PCI_DIV_MASK              0x00700000
 195 #define SCFR1_PCI_DIV_SHIFT             20
 196
 197 /* SCFR2 System Clock Frequency Register 2
 198  */
 199 #define SCFR2_SYS_DIV                   0xFC000000
 200 #define SCFR2_SYS_DIV_SHIFT             26
 201
 202 /* SCCR - System Clock Control Registers
 203  */
 204
 205 /* System Clock Control Register 1 commands */
 206 #define CLOCK_SCCR1_CFG_EN              0x80000000
 207 #define CLOCK_SCCR1_LPC_EN              0x40000000
 208 #define CLOCK_SCCR1_NFC_EN              0x20000000
 209 #define CLOCK_SCCR1_PATA_EN             0x10000000
 210 #define CLOCK_SCCR1_PSC_EN(cn)          (0x08000000 >> (cn))
 211 #define CLOCK_SCCR1_PSCFIFO_EN          0x00008000
 212 #define CLOCK_SCCR1_SATA_EN             0x00004000
 213 #define CLOCK_SCCR1_FEC_EN              0x00002000
 214 #define CLOCK_SCCR1_TPR_EN              0x00001000
 215 #define CLOCK_SCCR1_PCI_EN              0x00000800
 216 #define CLOCK_SCCR1_DDR_EN              0x00000400
 217
 218 /* System Clock Control Register 2 commands */
 219 #define CLOCK_SCCR2_DIU_EN              0x80000000
 220 #define CLOCK_SCCR2_AXE_EN              0x40000000
 221 #define CLOCK_SCCR2_MEM_EN              0x20000000
 222 #define CLOCK_SCCR2_USB2_EN             0x10000000
 223 #define CLOCK_SCCR2_USB1_EN             0x08000000
 224 #define CLOCK_SCCR2_I2C_EN              0x04000000
 225 #define CLOCK_SCCR2_BDLC_EN             0x02000000
 226 #define CLOCK_SCCR2_SDHC_EN             0x01000000
 227 #define CLOCK_SCCR2_SPDIF_EN            0x00800000
 228 #define CLOCK_SCCR2_MBX_BUS_EN          0x00400000
 229 #define CLOCK_SCCR2_MBX_EN              0x00200000
 230 #define CLOCK_SCCR2_MBX_3D_EN           0x00100000
 231 #define CLOCK_SCCR2_IIM_EN              0x00080000
 232
 233 /* PSC FIFO Command values */
 234 #define PSC_FIFO_RESET_SLICE            0x80
 235 #define PSC_FIFO_ENABLE_SLICE           0x01
 236
 237 /* PSC FIFO Controller Command values */
 238 #define FIFOC_ENABLE_CLOCK_GATE         0x01
 239 #define FIFOC_DISABLE_CLOCK_GATE        0x00
 240
 241 /* PSC FIFO status */
 242 #define PSC_FIFO_EMPTY                  0x01
 243
 244 /* PSC Command values */
 245 #define PSC_RX_ENABLE           0x01
 246 #define PSC_RX_DISABLE          0x02
 247 #define PSC_TX_ENABLE           0x04
 248 #define PSC_TX_DISABLE          0x08
 249 #define PSC_SEL_MODE_REG_1      0x10
 250 #define PSC_RST_RX              0x20
 251 #define PSC_RST_TX              0x30
 252 #define PSC_RST_ERR_STAT        0x40
 253 #define PSC_RST_BRK_CHG_INT     0x50
 254 #define PSC_START_BRK           0x60
 255 #define PSC_STOP_BRK            0x70
 256
 257 /* PSC status register bits */
 258 #define PSC_SR_CDE              0x0080
 259 #define PSC_SR_TXEMP            0x0800
 260 #define PSC_SR_OE               0x1000
 261 #define PSC_SR_PE               0x2000
 262 #define PSC_SR_FE               0x4000
 263 #define PSC_SR_RB               0x8000
 264
 265 /* PSC mode fields */
 266 #define PSC_MODE_5_BITS         0x00
 267 #define PSC_MODE_6_BITS         0x01
 268 #define PSC_MODE_7_BITS         0x02
 269 #define PSC_MODE_8_BITS         0x03
 270 #define PSC_MODE_PAREVEN        0x00
 271 #define PSC_MODE_PARODD         0x04
 272 #define PSC_MODE_PARFORCE       0x08
 273 #define PSC_MODE_PARNONE        0x10
 274 #define PSC_MODE_ENTIMEOUT      0x20
 275 #define PSC_MODE_RXRTS          0x80
 276 #define PSC_MODE_1_STOPBIT      0x07
 277
 278 /*
 279  * Centralized FIFO Controller has internal memory for all 12 PSCs FIFOs
 280  *
 281  * NOTE: individual PSC units are free to use whatever area (and size) of the
 282  * FIFOC internal memory, so make sure memory areas for FIFO slices used by
 283  * different PSCs do not overlap!
 284  *
 285  * Overall size of FIFOC memory is not documented in the MPC5121e RM, but
 286  * tests indicate that it is 1024 words total.
 287  */
 288 #define FIFOC_PSC0_TX_SIZE      0x0     /* number of 4-byte words for FIFO slice */
 289 #define FIFOC_PSC0_TX_ADDR      0x0
 290 #define FIFOC_PSC0_RX_SIZE      0x0
 291 #define FIFOC_PSC0_RX_ADDR      0x0
 292
 293 #define FIFOC_PSC1_TX_SIZE      0x0
 294 #define FIFOC_PSC1_TX_ADDR      0x0
 295 #define FIFOC_PSC1_RX_SIZE      0x0
 296 #define FIFOC_PSC1_RX_ADDR      0x0
 297
 298 #define FIFOC_PSC2_TX_SIZE      0x0
 299 #define FIFOC_PSC2_TX_ADDR      0x0
 300 #define FIFOC_PSC2_RX_SIZE      0x0
 301 #define FIFOC_PSC2_RX_ADDR      0x0
 302
 303 #define FIFOC_PSC3_TX_SIZE      0x04
 304 #define FIFOC_PSC3_TX_ADDR      0x0
 305 #define FIFOC_PSC3_RX_SIZE      0x04
 306 #define FIFOC_PSC3_RX_ADDR      0x10
 307
 308 #define FIFOC_PSC4_TX_SIZE      0x0
 309 #define FIFOC_PSC4_TX_ADDR      0x0
 310 #define FIFOC_PSC4_RX_SIZE      0x0
 311 #define FIFOC_PSC4_RX_ADDR      0x0
 312
 313 #define FIFOC_PSC5_TX_SIZE      0x0
 314 #define FIFOC_PSC5_TX_ADDR      0x0
 315 #define FIFOC_PSC5_RX_SIZE      0x0
 316 #define FIFOC_PSC5_RX_ADDR      0x0
 317
 318 #define FIFOC_PSC6_TX_SIZE      0x0
 319 #define FIFOC_PSC6_TX_ADDR      0x0
 320 #define FIFOC_PSC6_RX_SIZE      0x0
 321 #define FIFOC_PSC6_RX_ADDR      0x0
 322
 323 #define FIFOC_PSC7_TX_SIZE      0x0
 324 #define FIFOC_PSC7_TX_ADDR      0x0
 325 #define FIFOC_PSC7_RX_SIZE      0x0
 326 #define FIFOC_PSC7_RX_ADDR      0x0
 327
 328 #define FIFOC_PSC8_TX_SIZE      0x0
 329 #define FIFOC_PSC8_TX_ADDR      0x0
 330 #define FIFOC_PSC8_RX_SIZE      0x0
 331 #define FIFOC_PSC8_RX_ADDR      0x0
 332
 333 #define FIFOC_PSC9_TX_SIZE      0x0
 334 #define FIFOC_PSC9_TX_ADDR      0x0
 335 #define FIFOC_PSC9_RX_SIZE      0x0
 336 #define FIFOC_PSC9_RX_ADDR      0x0
 337
 338 #define FIFOC_PSC10_TX_SIZE     0x0
 339 #define FIFOC_PSC10_TX_ADDR     0x0
 340 #define FIFOC_PSC10_RX_SIZE     0x0
 341 #define FIFOC_PSC10_RX_ADDR     0x0
 342
 343 #define FIFOC_PSC11_TX_SIZE     0x0
 344 #define FIFOC_PSC11_TX_ADDR     0x0
 345 #define FIFOC_PSC11_RX_SIZE     0x0
 346 #define FIFOC_PSC11_RX_ADDR     0x0
 347
 348 /* IO Control Register
 349  */
 350
 351 /* Indexes in regs array */
 352 #define MEM_IDX                 0x00
 353 #define PATA_CE1_IDX            0x2e
 354 #define PATA_CE2_IDX            0x2f
 355 #define PATA_ISOLATE_IDX        0x30
 356 #define PATA_IOR_IDX            0x31
 357 #define PATA_IOW_IDX            0x32
 358 #define PATA_IOCHRDY_IDX        0x33
 359 #define PATA_INTRQ_IDX          0x34
 360 #define PATA_DRQ_IDX            0x35
 361 #define PATA_DACK_IDX           0x36
 362 #define SPDIF_TXCLOCK_IDX       0x73
 363 #define SPDIF_TX_IDX            0x74
 364 #define SPDIF_RX_IDX            0x75
 365 #define PSC0_0_IDX              0x83
 366 #define PSC0_1_IDX              0x84
 367 #define PSC0_2_IDX              0x85
 368 #define PSC0_3_IDX              0x86
 369 #define PSC0_4_IDX              0x87
 370 #define PSC1_0_IDX              0x88
 371 #define PSC1_1_IDX              0x89
 372 #define PSC1_2_IDX              0x8a
 373 #define PSC1_3_IDX              0x8b
 374 #define PSC1_4_IDX              0x8c
 375 #define PSC2_0_IDX              0x8d
 376 #define PSC2_1_IDX              0x8e
 377 #define PSC2_2_IDX              0x8f
 378 #define PSC2_3_IDX              0x90
 379 #define PSC2_4_IDX              0x91
 380
 381 #define IOCTRL_FUNCMUX_SHIFT    7
 382 #define IOCTRL_FUNCMUX_FEC      1
 383 #define IOCTRL_MUX_FEC          (IOCTRL_FUNCMUX_FEC << IOCTRL_FUNCMUX_SHIFT)
 384
 385 /* Set for DDR */
 386 #define IOCTRL_MUX_DDR          0x00000036
 387
 388  /* Register Offset Base */
 389 #define MPC512X_FEC             (CFG_IMMR + 0x02800)
 390
 391 /* Number of I2C buses */
 392 #define I2C_BUS_CNT     3
 393
 394 /* I2Cn control register bits */
 395 #define I2C_EN          0x80
 396 #define I2C_IEN         0x40
 397 #define I2C_STA         0x20
 398 #define I2C_TX          0x10
 399 #define I2C_TXAK        0x08
 400 #define I2C_RSTA        0x04
 401 #define I2C_INIT_MASK   (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
 402
 403 /* I2Cn status register bits */
 404 #define I2C_CF          0x80
 405 #define I2C_AAS         0x40
 406 #define I2C_BB          0x20
 407 #define I2C_AL          0x10
 408 #define I2C_SRW         0x04
 409 #define I2C_IF          0x02
 410 #define I2C_RXAK        0x01
 411
 412 /* POTAR - PCI Outbound Translation Address Register
 413  */
 414 #define POTAR_TA_MASK                   0x000fffff
 415
 416 /* POBAR - PCI Outbound Base Address Register
 417  */
 418 #define POBAR_BA_MASK                   0x000fffff
 419
 420 /* POCMR - PCI Outbound Comparision Mask Register
 421  */
 422 #define POCMR_EN        0x80000000
 423 #define POCMR_IO        0x40000000      /* 0-memory space 1-I/O space */
 424 #define POCMR_PRE       0x20000000      /* prefetch enable */
 425 #define POCMR_SBS       0x00100000      /* special byte swap enable */
 426 #define POCMR_CM_MASK   0x000fffff
 427 #define POCMR_CM_4G     0x00000000
 428 #define POCMR_CM_2G     0x00080000
 429 #define POCMR_CM_1G     0x000C0000
 430 #define POCMR_CM_512M   0x000E0000
 431 #define POCMR_CM_256M   0x000F0000
 432 #define POCMR_CM_128M   0x000F8000
 433 #define POCMR_CM_64M    0x000FC000
 434 #define POCMR_CM_32M    0x000FE000
 435 #define POCMR_CM_16M    0x000FF000
 436 #define POCMR_CM_8M     0x000FF800
 437 #define POCMR_CM_4M     0x000FFC00
 438 #define POCMR_CM_2M     0x000FFE00
 439 #define POCMR_CM_1M     0x000FFF00
 440 #define POCMR_CM_512K   0x000FFF80
 441 #define POCMR_CM_256K   0x000FFFC0
 442 #define POCMR_CM_128K   0x000FFFE0
 443 #define POCMR_CM_64K    0x000FFFF0
 444 #define POCMR_CM_32K    0x000FFFF8
 445 #define POCMR_CM_16K    0x000FFFFC
 446 #define POCMR_CM_8K     0x000FFFFE
 447 #define POCMR_CM_4K     0x000FFFFF
 448
 449 /* PITAR - PCI Inbound Translation Address Register
 450  */
 451 #define PITAR_TA_MASK                   0x000fffff
 452
 453 /* PIBAR - PCI Inbound Base/Extended Address Register
 454  */
 455 #define PIBAR_MASK                      0xffffffff
 456 #define PIEBAR_EBA_MASK                 0x000fffff
 457
 458 /* PIWAR - PCI Inbound Windows Attributes Register
 459  */
 460 #define PIWAR_EN                        0x80000000
 461 #define PIWAR_SBS                       0x40000000
 462 #define PIWAR_PF                        0x20000000
 463 #define PIWAR_RTT_MASK                  0x000f0000
 464 #define PIWAR_RTT_NO_SNOOP              0x00040000
 465 #define PIWAR_RTT_SNOOP                 0x00050000
 466 #define PIWAR_WTT_MASK                  0x0000f000
 467 #define PIWAR_WTT_NO_SNOOP              0x00004000
 468 #define PIWAR_WTT_SNOOP                 0x00005000
 469 #define PIWAR_IWS_MASK                  0x0000003F
 470 #define PIWAR_IWS_4K                    0x0000000B
 471 #define PIWAR_IWS_8K                    0x0000000C
 472 #define PIWAR_IWS_16K                   0x0000000D
 473 #define PIWAR_IWS_32K                   0x0000000E
 474 #define PIWAR_IWS_64K                   0x0000000F
 475 #define PIWAR_IWS_128K                  0x00000010
 476 #define PIWAR_IWS_256K                  0x00000011
 477 #define PIWAR_IWS_512K                  0x00000012
 478 #define PIWAR_IWS_1M                    0x00000013
 479 #define PIWAR_IWS_2M                    0x00000014
 480 #define PIWAR_IWS_4M                    0x00000015
 481 #define PIWAR_IWS_8M                    0x00000016
 482 #define PIWAR_IWS_16M                   0x00000017
 483 #define PIWAR_IWS_32M                   0x00000018
 484 #define PIWAR_IWS_64M                   0x00000019
 485 #define PIWAR_IWS_128M                  0x0000001A
 486 #define PIWAR_IWS_256M                  0x0000001B
 487 #define PIWAR_IWS_512M                  0x0000001C
 488 #define PIWAR_IWS_1G                    0x0000001D
 489 #define PIWAR_IWS_2G                    0x0000001E
 490
 491 #endif  /* __MPC512X_H__ */