include/lxt971a.h

   1 /***********************************************************************
   2  *
   3  * Copyright (C) 2004 by FS Forth-Systeme GmbH.
   4  * All rights reserved.
   5  *
   6  * $Id: ns9750_eth.h,v 1.2 2004/02/24 13:25:39 mpietrek Exp $
   7  * @Author: Markus Pietrek
   8  * @References: [1] NS9750 Hardware Reference, December 2003
   9  *              [2] Intel LXT971 Datasheet #249414 Rev. 02
  10  *              [3] NS7520 Linux Ethernet Driver
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  *
  27  ***********************************************************************/
  28
  29 #ifndef __LXT971A_H__
  30 #define __LXT971A_H__
  31
  32 /* PHY definitions (LXT971A) [2] */
  33 #define PHY_COMMON_CTRL                 (0x00)
  34 #define PHY_COMMON_STAT                 (0x01)
  35 #define PHY_COMMON_ID1                  (0x02)
  36 #define PHY_COMMON_ID2                  (0x03)
  37 #define PHY_COMMON_AUTO_ADV             (0x04)
  38 #define PHY_COMMON_AUTO_LNKB            (0x05)
  39 #define PHY_COMMON_AUTO_EXP             (0x06)
  40 #define PHY_COMMON_AUTO_NEXT            (0x07)
  41 #define PHY_COMMON_AUTO_LNKN            (0x08)
  42 #define PHY_LXT971_PORT_CFG             (0x10)
  43 #define PHY_LXT971_STAT2                (0x11)
  44 #define PHY_LXT971_INT_ENABLE           (0x12)
  45 #define PHY_LXT971_INT_STATUS           (0x13)
  46 #define PHY_LXT971_LED_CFG              (0x14)
  47 #define PHY_LXT971_DIG_CFG              (0x1A)
  48 #define PHY_LXT971_TX_CTRL              (0x1E)
  49
  50 /* CTRL PHY Control Register Bit Fields */
  51 #define PHY_COMMON_CTRL_RESET           (0x8000)
  52 #define PHY_COMMON_CTRL_LOOPBACK        (0x4000)
  53 #define PHY_COMMON_CTRL_SPD_MA          (0x2040)
  54 #define PHY_COMMON_CTRL_SPD_10          (0x0000)
  55 #define PHY_COMMON_CTRL_SPD_100         (0x2000)
  56 #define PHY_COMMON_CTRL_SPD_1000        (0x0040)
  57 #define PHY_COMMON_CTRL_SPD_RES         (0x2040)
  58 #define PHY_COMMON_CTRL_AUTO_NEG        (0x1000)
  59 #define PHY_COMMON_CTRL_POWER_DN        (0x0800)
  60 #define PHY_COMMON_CTRL_ISOLATE         (0x0400)
  61 #define PHY_COMMON_CTRL_RES_AUTO        (0x0200)
  62 #define PHY_COMMON_CTRL_DUPLEX          (0x0100)
  63 #define PHY_COMMON_CTRL_COL_TEST        (0x0080)
  64 #define PHY_COMMON_CTRL_RES1            (0x003F)
  65
  66 /* STAT Status Register Bit Fields */
  67 #define PHY_COMMON_STAT_100BT4          (0x8000)
  68 #define PHY_COMMON_STAT_100BXFD         (0x4000)
  69 #define PHY_COMMON_STAT_100BXHD         (0x2000)
  70 #define PHY_COMMON_STAT_10BTFD          (0x1000)
  71 #define PHY_COMMON_STAT_10BTHD          (0x0800)
  72 #define PHY_COMMON_STAT_100BT2FD        (0x0400)
  73 #define PHY_COMMON_STAT_100BT2HD        (0x0200)
  74 #define PHY_COMMON_STAT_EXT_STAT        (0x0100)
  75 #define PHY_COMMON_STAT_RES1            (0x0080)
  76 #define PHY_COMMON_STAT_MF_PSUP         (0x0040)
  77 #define PHY_COMMON_STAT_AN_COMP         (0x0020)
  78 #define PHY_COMMON_STAT_RMT_FLT         (0x0010)
  79 #define PHY_COMMON_STAT_AN_CAP          (0x0008)
  80 #define PHY_COMMON_STAT_LNK_STAT        (0x0004)
  81 #define PHY_COMMON_STAT_JAB_DTCT        (0x0002)
  82 #define PHY_COMMON_STAT_EXT_CAP         (0x0001)
  83
  84 /* AUTO_ADV Auto-neg Advert Register Bit Fields */
  85 #define PHY_COMMON_AUTO_ADV_NP          (0x8000)
  86 #define PHY_COMMON_AUTO_ADV_RES1        (0x4000)
  87 #define PHY_COMMON_AUTO_ADV_RMT_FLT     (0x2000)
  88 #define PHY_COMMON_AUTO_ADV_RES2        (0x1000)
  89 #define PHY_COMMON_AUTO_ADV_AS_PAUSE    (0x0800)
  90 #define PHY_COMMON_AUTO_ADV_PAUSE       (0x0400)
  91 #define PHY_COMMON_AUTO_ADV_100BT4      (0x0200)
  92 #define PHY_COMMON_AUTO_ADV_100BTXFD    (0x0100)
  93 #define PHY_COMMON_AUTO_ADV_100BTX      (0x0080)
  94 #define PHY_COMMON_AUTO_ADV_10BTFD      (0x0040)
  95 #define PHY_COMMON_AUTO_ADV_10BT        (0x0020)
  96 #define PHY_COMMON_AUTO_ADV_SEL_FLD_MA  (0x001F)
  97 #define PHY_COMMON_AUTO_ADV_802_9       (0x0002)
  98 #define PHY_COMMON_AUTO_ADV_802_3       (0x0001)
  99
 100 /* AUTO_LNKB Auto-neg Link Ability Register Bit Fields */
 101 #define PHY_COMMON_AUTO_LNKB_NP         (0x8000)
 102 #define PHY_COMMON_AUTO_LNKB_ACK        (0x4000)
 103 #define PHY_COMMON_AUTO_LNKB_RMT_FLT    (0x2000)
 104 #define PHY_COMMON_AUTO_LNKB_RES2       (0x1000)
 105 #define PHY_COMMON_AUTO_LNKB_AS_PAUSE   (0x0800)
 106 #define PHY_COMMON_AUTO_LNKB_PAUSE      (0x0400)
 107 #define PHY_COMMON_AUTO_LNKB_100BT4     (0x0200)
 108 #define PHY_COMMON_AUTO_LNKB_100BTXFD   (0x0100)
 109 #define PHY_COMMON_AUTO_LNKB_100BTX     (0x0080)
 110 #define PHY_COMMON_AUTO_LNKB_10BTFD     (0x0040)
 111 #define PHY_COMMON_AUTO_LNKB_10BT       (0x0020)
 112 #define PHY_COMMON_AUTO_LNKB_SEL_FLD_MA (0x001F)
 113 #define PHY_COMMON_AUTO_LNKB_802_9      (0x0002)
 114 #define PHY_COMMON_AUTO_LNKB_802_3      (0x0001)
 115
 116 /* AUTO_EXP Auto-neg Expansion Register Bit Fields */
 117 #define PHY_COMMON_AUTO_EXP_RES1        (0xFFC0)
 118 #define PHY_COMMON_AUTO_EXP_BASE_PAGE   (0x0020)
 119 #define PHY_COMMON_AUTO_EXP_PAR_DT_FLT  (0x0010)
 120 #define PHY_COMMON_AUTO_EXP_LNK_NP_CAP  (0x0008)
 121 #define PHY_COMMON_AUTO_EXP_NP_CAP      (0x0004)
 122 #define PHY_COMMON_AUTO_EXP_PAGE_REC    (0x0002)
 123 #define PHY_COMMON_AUTO_EXP_LNK_AN_CAP  (0x0001)
 124
 125 /* AUTO_NEXT Aut-neg Next Page Tx Register Bit Fields */
 126 #define PHY_COMMON_AUTO_NEXT_NP         (0x8000)
 127 #define PHY_COMMON_AUTO_NEXT_RES1       (0x4000)
 128 #define PHY_COMMON_AUTO_NEXT_MSG_PAGE   (0x2000)
 129 #define PHY_COMMON_AUTO_NEXT_ACK_2      (0x1000)
 130 #define PHY_COMMON_AUTO_NEXT_TOGGLE     (0x0800)
 131 #define PHY_COMMON_AUTO_NEXT_MSG        (0x07FF)
 132
 133 /* AUTO_LNKN Auto-neg Link Partner Rx Reg Bit Fields */
 134 #define PHY_COMMON_AUTO_LNKN_NP         (0x8000)
 135 #define PHY_COMMON_AUTO_LNKN_ACK        (0x4000)
 136 #define PHY_COMMON_AUTO_LNKN_MSG_PAGE   (0x2000)
 137 #define PHY_COMMON_AUTO_LNKN_ACK_2      (0x1000)
 138 #define PHY_COMMON_AUTO_LNKN_TOGGLE     (0x0800)
 139 #define PHY_COMMON_AUTO_LNKN_MSG        (0x07FF)
 140
 141 /* PORT_CFG Port Configuration Register Bit Fields */
 142 #define PHY_LXT971_PORT_CFG_RES1        (0x8000)
 143 #define PHY_LXT971_PORT_CFG_FORCE_LNK   (0x4000)
 144 #define PHY_LXT971_PORT_CFG_TX_DISABLE  (0x2000)
 145 #define PHY_LXT971_PORT_CFG_BYPASS_SCR  (0x1000)
 146 #define PHY_LXT971_PORT_CFG_RES2        (0x0800)
 147 #define PHY_LXT971_PORT_CFG_JABBER      (0x0400)
 148 #define PHY_LXT971_PORT_CFG_SQE         (0x0200)
 149 #define PHY_LXT971_PORT_CFG_TP_LOOPBACK (0x0100)
 150 #define PHY_LXT971_PORT_CFG_CRS_SEL     (0x0080)
 151 #define PHY_LXT971_PORT_CFG_SLEEP_MODE  (0x0040)
 152 #define PHY_LXT971_PORT_CFG_PRE_EN      (0x0020)
 153 #define PHY_LXT971_PORT_CFG_SLEEP_T_MA  (0x0018)
 154 #define PHY_LXT971_PORT_CFG_SLEEP_T_104 (0x0010)
 155 #define PHY_LXT971_PORT_CFG_SLEEP_T_200 (0x0001)
 156 #define PHY_LXT971_PORT_CFG_SLEEP_T_304 (0x0000)
 157 #define PHY_LXT971_PORT_CFG_FLT_CODE_EN (0x0004)
 158 #define PHY_LXT971_PORT_CFG_ALT_NP      (0x0002)
 159 #define PHY_LXT971_PORT_CFG_FIBER_SEL   (0x0001)
 160
 161 /* STAT2 Status Register #2 Bit Fields */
 162 #define PHY_LXT971_STAT2_RES1           (0x8000)
 163 #define PHY_LXT971_STAT2_100BTX         (0x4000)
 164 #define PHY_LXT971_STAT2_TX_STATUS      (0x2000)
 165 #define PHY_LXT971_STAT2_RX_STATUS      (0x1000)
 166 #define PHY_LXT971_STAT2_COL_STATUS     (0x0800)
 167 #define PHY_LXT971_STAT2_LINK           (0x0400)
 168 #define PHY_LXT971_STAT2_DUPLEX_MODE    (0x0200)
 169 #define PHY_LXT971_STAT2_AUTO_NEG       (0x0100)
 170 #define PHY_LXT971_STAT2_AUTO_NEG_COMP  (0x0080)
 171 #define PHY_LXT971_STAT2_RES2           (0x0040)
 172 #define PHY_LXT971_STAT2_POLARITY       (0x0020)
 173 #define PHY_LXT971_STAT2_PAUSE          (0x0010)
 174 #define PHY_LXT971_STAT2_ERROR          (0x0008)
 175 #define PHY_LXT971_STAT2_RES3           (0x0007)
 176
 177 /* INT_ENABLE Interrupt Enable Register Bit Fields */
 178 #define PHY_LXT971_INT_ENABLE_RES1      (0xFF00)
 179 #define PHY_LXT971_INT_ENABLE_ANMSK     (0x0080)
 180 #define PHY_LXT971_INT_ENABLE_SPEEDMSK  (0x0040)
 181 #define PHY_LXT971_INT_ENABLE_DUPLEXMSK (0x0020)
 182 #define PHY_LXT971_INT_ENABLE_LINKMSK   (0x0010)
 183 #define PHY_LXT971_INT_ENABLE_RES2      (0x000C)
 184 #define PHY_LXT971_INT_ENABLE_INTEN     (0x0002)
 185 #define PHY_LXT971_INT_ENABLE_TINT      (0x0001)
 186
 187 /* INT_STATUS Interrupt Status Register Bit Fields */
 188 #define PHY_LXT971_INT_STATUS_RES1      (0xFF00)
 189 #define PHY_LXT971_INT_STATUS_ANDONE    (0x0080)
 190 #define PHY_LXT971_INT_STATUS_SPEEDCHG  (0x0040)
 191 #define PHY_LXT971_INT_STATUS_DUPLEXCHG (0x0020)
 192 #define PHY_LXT971_INT_STATUS_LINKCHG   (0x0010)
 193 #define PHY_LXT971_INT_STATUS_RES2      (0x0008)
 194 #define PHY_LXT971_INT_STATUS_MDINT     (0x0004)
 195 #define PHY_LXT971_INT_STATUS_RES3      (0x0003)
 196
 197 /* LED_CFG Interrupt LED Configuration Register Bit Fields */
 198 #define PHY_LXT971_LED_CFG_SHIFT_LED1   (0x000C)
 199 #define PHY_LXT971_LED_CFG_SHIFT_LED2   (0x0008)
 200 #define PHY_LXT971_LED_CFG_SHIFT_LED3   (0x0004)
 201 #define PHY_LXT971_LED_CFG_LEDFREQ_MA   (0x000C)
 202 #define PHY_LXT971_LED_CFG_LEDFREQ_RES  (0x000C)
 203 #define PHY_LXT971_LED_CFG_LEDFREQ_100  (0x0008)
 204 #define PHY_LXT971_LED_CFG_LEDFREQ_60   (0x0004)
 205 #define PHY_LXT971_LED_CFG_LEDFREQ_30   (0x0000)
 206 #define PHY_LXT971_LED_CFG_PULSE_STR    (0x0002)
 207 #define PHY_LXT971_LED_CFG_RES1         (0x0001)
 208
 209 /* only one of these values must be shifted for each SHIFT_LED?  */
 210 #define PHY_LXT971_LED_CFG_UNUSED1      (0x000F)
 211 #define PHY_LXT971_LED_CFG_DUPLEX_COL   (0x000E)
 212 #define PHY_LXT971_LED_CFG_LINK_ACT     (0x000D)
 213 #define PHY_LXT971_LED_CFG_LINK_RX      (0x000C)
 214 #define PHY_LXT971_LED_CFG_TEST_BLK_SLW (0x000B)
 215 #define PHY_LXT971_LED_CFG_TEST_BLK_FST (0x000A)
 216 #define PHY_LXT971_LED_CFG_TEST_OFF     (0x0009)
 217 #define PHY_LXT971_LED_CFG_TEST_ON      (0x0008)
 218 #define PHY_LXT971_LED_CFG_RX_OR_TX     (0x0007)
 219 #define PHY_LXT971_LED_CFG_UNUSED2      (0x0006)
 220 #define PHY_LXT971_LED_CFG_DUPLEX       (0x0005)
 221 #define PHY_LXT971_LED_CFG_LINK         (0x0004)
 222 #define PHY_LXT971_LED_CFG_COLLISION    (0x0003)
 223 #define PHY_LXT971_LED_CFG_RECEIVE      (0x0002)
 224 #define PHY_LXT971_LED_CFG_TRANSMIT     (0x0001)
 225 #define PHY_LXT971_LED_CFG_SPEED        (0x0000)
 226
 227 /* DIG_CFG Digitial Configuration Register Bit Fields */
 228 #define PHY_LXT971_DIG_CFG_RES1         (0xF000)
 229 #define PHY_LXT971_DIG_CFG_MII_DRIVE    (0x0800)
 230 #define PHY_LXT971_DIG_CFG_RES2         (0x0400)
 231 #define PHY_LXT971_DIG_CFG_SHOW_SYMBOL  (0x0200)
 232 #define PHY_LXT971_DIG_CFG_RES3         (0x01FF)
 233
 234 #define PHY_LXT971_MDIO_MAX_CLK         (8000000)
 235 #define PHY_MDIO_MAX_CLK                (2500000)
 236
 237 /* TX_CTRL Transmit Control Register Bit Fields
 238    documentation is buggy for this register, therefore setting not included */
 239
 240 typedef enum
 241 {
 242         PHY_NONE    = 0x0000, /* no PHY detected yet */
 243         PHY_LXT971A = 0x0013
 244 } PhyType;
 245
 246 #endif /* __LXT971A_H__ */