include/configs/stxxtc.h

   1 /*
   2  * (C) Copyright 2000-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
  26  * U-Boot port on STx XTc 8xx board
  27  * Mostly copied from Panto's NETTA2 board.
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37
  38 #define CONFIG_MPC875           1       /* This is a MPC875 CPU         */
  39 #define CONFIG_STXXTC           1       /* ...on a STx XTc  board       */
  40
  41 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  42 #undef  CONFIG_8xx_CONS_SMC2
  43 #undef  CONFIG_8xx_CONS_NONE
  44
  45 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115.2kbps */
  46
  47 #define CONFIG_XIN              10000000        /* 10 MHz input xtal */
  48
  49 /* Select one of few clock rates defined later in this file.
  50 */
  51 /* #define MPC8XX_HZ            50000000 */
  52 #define MPC8XX_HZ               66666666
  53
  54 #define CONFIG_8xx_GCLK_FREQ    MPC8XX_HZ
  55
  56 #if 0
  57 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  58 #else
  59 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  60 #endif
  61
  62 #undef  CONFIG_CLOCKS_IN_MHZ    /* clocks NOT passsed to Linux in MHz */
  63
  64 #undef  CONFIG_BOOTARGS
  65 #define CONFIG_BOOTCOMMAND                                                      \
  66         "tftpboot; "                                                            \
  67         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  68         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
  69         "bootm"
  70
  71 #define CONFIG_AUTOSCRIPT
  72 #define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
  73 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  74
  75 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  76
  77 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  78 #define CONFIG_BOARD_SPECIFIC_LED       /* version has board specific leds */
  79
  80 /*
  81  * BOOTP options
  82  */
  83 #define CONFIG_BOOTP_SUBNETMASK
  84 #define CONFIG_BOOTP_GATEWAY
  85 #define CONFIG_BOOTP_HOSTNAME
  86 #define CONFIG_BOOTP_BOOTPATH
  87 #define CONFIG_BOOTP_BOOTFILESIZE
  88 #define CONFIG_BOOTP_NISDOMAIN
  89
  90
  91 #undef CONFIG_MAC_PARTITION
  92 #undef CONFIG_DOS_PARTITION
  93
  94 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  95
  96 #define CONFIG_NET_MULTI        1       /* the only way to get the FEC in */
  97 #define FEC_ENET                1       /* eth.c needs it that way... */
  98 #undef CFG_DISCOVER_PHY
  99 #define CONFIG_MII              1
 100 #undef CONFIG_RMII
 101
 102 #define CONFIG_ETHER_ON_FEC1    1
 103 #define CONFIG_FEC1_PHY         1       /* phy address of FEC */
 104 #undef CONFIG_FEC1_PHY_NORXERR
 105
 106 #define CONFIG_ETHER_ON_FEC2    1
 107 #define CONFIG_FEC2_PHY         3
 108 #undef CONFIG_FEC2_PHY_NORXERR
 109
 110 #define CONFIG_ENV_OVERWRITE    1       /* allow modification of vendor params */
 111
 112
 113 /*
 114  * Command line configuration.
 115  */
 116 #include <config_cmd_default.h>
 117
 118 #define CONFIG_CMD_DHCP
 119 #define CONFIG_CMD_MII
 120 #define CONFIG_CMD_NAND
 121 #define CONFIG_CMD_NFS
 122 #define CONFIG_CMD_PING
 123
 124
 125 #define CONFIG_BOARD_EARLY_INIT_F       1
 126 #define CONFIG_MISC_INIT_R
 127
 128 /*
 129  * Miscellaneous configurable options
 130  */
 131 #define CFG_LONGHELP                    /* undef to save memory         */
 132 #define CFG_PROMPT      "xtc> "         /* Monitor Command Prompt       */
 133
 134 #define CFG_HUSH_PARSER 1
 135 #define CFG_PROMPT_HUSH_PS2     "> "
 136
 137 #if defined(CONFIG_CMD_KGDB)
 138 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 139 #else
 140 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 141 #endif
 142 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 143 #define CFG_MAXARGS     16              /* max number of command args   */
 144 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 145
 146 #define CFG_MEMTEST_START       0x0300000       /* memtest works on     */
 147 #define CFG_MEMTEST_END         0x0700000       /* 3 ... 7 MB in DRAM   */
 148
 149 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 150
 151 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 152
 153 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 154
 155 /*
 156  * Low Level Configuration Settings
 157  * (address mappings, register initial values, etc.)
 158  * You should know what you are doing if you make changes here.
 159  */
 160 /*-----------------------------------------------------------------------
 161  * Internal Memory Mapped Register
 162  */
 163 #define CFG_IMMR                0xFF000000
 164
 165 /*-----------------------------------------------------------------------
 166  * Definitions for initial stack pointer and data area (in DPRAM)
 167  */
 168 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 169 #define CFG_INIT_RAM_END        0x3000  /* End of used area in DPRAM    */
 170 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 171 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 172 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 173
 174 /*-----------------------------------------------------------------------
 175  * Start addresses for the final memory configuration
 176  * (Set up by the startup code)
 177  * Please note that CFG_SDRAM_BASE _must_ start at 0
 178  */
 179 #define CFG_SDRAM_BASE          0x00000000
 180 #define CFG_FLASH_BASE          0x40000000
 181 #if defined(DEBUG)
 182 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 183 #else
 184 #define CFG_MONITOR_LEN         (192 << 10)     /* Reserve 192 kB for Monitor   */
 185 #endif
 186
 187 /* yes this is weird, I know :) */
 188 #define CFG_MONITOR_BASE        (CFG_FLASH_BASE | 0x00F00000)
 189 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 190
 191 #define CFG_RESET_ADDRESS       0x80000000
 192
 193 /*
 194  * For booting Linux, the board info and command line data
 195  * have to be in the first 8 MB of memory, since this is
 196  * the maximum mapped by the Linux kernel during initialization.
 197  */
 198 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 199
 200 /*-----------------------------------------------------------------------
 201  * FLASH organization
 202  */
 203 #define CFG_ENV_IS_IN_FLASH     1
 204 #define CFG_ENV_SECT_SIZE       0x10000
 205
 206 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00000000)
 207 #define CFG_ENV_OFFSET          0
 208 #define CFG_ENV_SIZE            0x4000
 209
 210 #define CFG_ENV_ADDR_REDUND     (CFG_FLASH_BASE + 0x00010000)
 211 #define CFG_ENV_OFFSET_REDUND   0
 212 #define CFG_ENV_SIZE_REDUND     CFG_ENV_SIZE
 213
 214 #define CFG_FLASH_CFI           1
 215 #define CFG_FLASH_CFI_DRIVER    1
 216 #undef CFG_FLASH_USE_BUFFER_WRITE       /* use buffered writes (20x faster) */
 217 #define CFG_MAX_FLASH_SECT      128     /* max number of sectors on one chip */
 218 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks   */
 219
 220 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + 0x2000000 }
 221
 222 #define CFG_FLASH_PROTECTION
 223
 224 /*-----------------------------------------------------------------------
 225  * Cache Configuration
 226  */
 227 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs */
 228 #if defined(CONFIG_CMD_KGDB)
 229 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value */
 230 #endif
 231
 232 /*-----------------------------------------------------------------------
 233  * SYPCR - System Protection Control                            11-9
 234  * SYPCR can only be written once after reset!
 235  *-----------------------------------------------------------------------
 236  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 237  */
 238 #if defined(CONFIG_WATCHDOG)
 239 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 240                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 241 #else
 242 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 243 #endif
 244
 245 /*-----------------------------------------------------------------------
 246  * SIUMCR - SIU Module Configuration                            11-6
 247  *-----------------------------------------------------------------------
 248  * PCMCIA config., multi-function pin tri-state
 249  */
 250 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E)
 251
 252 /*-----------------------------------------------------------------------
 253  * TBSCR - Time Base Status and Control                         11-26
 254  *-----------------------------------------------------------------------
 255  * Clear Reference Interrupt Status, Timebase freezing enabled
 256  */
 257 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 258
 259 /*-----------------------------------------------------------------------
 260  * RTCSC - Real-Time Clock Status and Control Register          11-27
 261  *-----------------------------------------------------------------------
 262  */
 263 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 264
 265 /*-----------------------------------------------------------------------
 266  * PISCR - Periodic Interrupt Status and Control                11-31
 267  *-----------------------------------------------------------------------
 268  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 269  */
 270 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 271
 272 /*-----------------------------------------------------------------------
 273  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 274  *-----------------------------------------------------------------------
 275  * Reset PLL lock status sticky bit, timer expired status bit and timer
 276  * interrupt status bit
 277  *
 278  */
 279
 280 #if CONFIG_XIN == 10000000
 281
 282 #if MPC8XX_HZ == 50000000
 283 #define CFG_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 284                          (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
 285                          PLPRCR_TEXPS)
 286 #elif MPC8XX_HZ == 66666666
 287 #define CFG_PLPRCR      ((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \
 288                          (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
 289                          PLPRCR_TEXPS)
 290 #else
 291 #error unsupported CPU freq for XIN = 10MHz
 292 #endif
 293 #else
 294 #error unsupported freq for XIN (must be 10MHz)
 295 #endif
 296
 297
 298 /*
 299  *-----------------------------------------------------------------------
 300  * SCCR - System Clock and reset Control Register               15-27
 301  *-----------------------------------------------------------------------
 302  * Set clock output, timebase and RTC source and divider,
 303  * power management and some other internal clocks
 304  *
 305  * Note: When TBS == 0 the timebase is independent of current cpu clock.
 306  */
 307
 308 #define SCCR_MASK       SCCR_EBDF11
 309 #if MPC8XX_HZ > 66666666
 310 #define CFG_SCCR        (/* SCCR_TBS     | */ SCCR_CRQEN | \
 311                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 312                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 313                          SCCR_DFALCD00 | SCCR_EBDF01)
 314 #else
 315 #define CFG_SCCR        (/* SCCR_TBS     | */ SCCR_CRQEN | \
 316                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 317                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 318                          SCCR_DFALCD00)
 319 #endif
 320
 321 /*-----------------------------------------------------------------------
 322  *
 323  *-----------------------------------------------------------------------
 324  *
 325  */
 326 /*#define       CFG_DER 0x2002000F*/
 327 #define CFG_DER 0
 328
 329 /*
 330  * Init Memory Controller:
 331  *
 332  * BR0/1 and OR0/1 (FLASH)
 333  */
 334
 335 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 336 #define FLASH_BASE1_PRELIM      0x42000000      /* FLASH bank #1        */
 337
 338 /* used to re-map FLASH both when starting from SRAM or FLASH:
 339  * restrict access enough to keep SRAM working (if any)
 340  * but not too much to meddle with FLASH accesses
 341  */
 342
 343 #define FLASH_BANK_MAX_SIZE     0x01000000      /* max size per chip */
 344
 345 #define CFG_REMAP_OR_AM         0x80000000
 346 #define CFG_PRELIM_OR_AM        (0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1))
 347
 348 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1        */
 349 #define CFG_OR_TIMING_FLASH     (OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
 350
 351 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 352 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 353 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 354
 355 #define CFG_OR1_PRELIM  ((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CFG_OR_TIMING_FLASH)
 356 #define CFG_BR1_PRELIM  ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 357
 358 /*
 359  * BR4 and OR4 (SDRAM)
 360  *
 361  */
 362 #define SDRAM_BASE1_PRELIM      0x00000000      /* SDRAM bank #0        */
 363 #define SDRAM_MAX_SIZE          (256 << 20)     /* max 256MB per bank   */
 364
 365 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 366 #define CFG_OR_TIMING_SDRAM     (OR_CSNT_SAM | OR_G5LS)
 367
 368 #define CFG_OR4_PRELIM  ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
 369 #define CFG_BR4_PRELIM  ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
 370
 371 /*
 372  * Memory Periodic Timer Prescaler
 373  */
 374
 375 /*
 376  * Memory Periodic Timer Prescaler
 377  *
 378  * The Divider for PTA (refresh timer) configuration is based on an
 379  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 380  * the number of chip selects (NCS) and the actually needed refresh
 381  * rate is done by setting MPTPR.
 382  *
 383  * PTA is calculated from
 384  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 385  *
 386  *      gclk      CPU clock (not bus clock!)
 387  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 388  *
 389  * 4096  Rows from SDRAM example configuration
 390  * 1000  factor s -> ms
 391  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 392  *    4  Number of refresh cycles per period
 393  *   64  Refresh cycle in ms per number of rows
 394  * --------------------------------------------
 395  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 396  *
 397  * 50 MHz => 50.000.000 / Divider =  98
 398  * 66 Mhz => 66.000.000 / Divider = 129
 399  * 80 Mhz => 80.000.000 / Divider = 156
 400  */
 401
 402 #define CFG_MAMR_PTA             234
 403
 404 /*
 405  * For 16 MBit, refresh rates could be 31.3 us
 406  * (= 64 ms / 2K = 125 / quad bursts).
 407  * For a simpler initialization, 15.6 us is used instead.
 408  *
 409  * #define CFG_MPTPR_2BK_2K     MPTPR_PTP_DIV32         for 2 banks
 410  * #define CFG_MPTPR_1BK_2K     MPTPR_PTP_DIV64         for 1 bank
 411  */
 412 #define CFG_MPTPR_2BK_4K        MPTPR_PTP_DIV16         /* setting for 2 banks  */
 413 #define CFG_MPTPR_1BK_4K        MPTPR_PTP_DIV32         /* setting for 1 bank   */
 414
 415 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 416 #define CFG_MPTPR_2BK_8K        MPTPR_PTP_DIV8          /* setting for 2 banks  */
 417 #define CFG_MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
 418
 419 /*
 420  * MAMR settings for SDRAM
 421  */
 422
 423 /* 8 column SDRAM */
 424 #define CFG_MAMR_8COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 425                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 426                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 427
 428 /* 9 column SDRAM */
 429 #define CFG_MAMR_9COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 430                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 431                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 432
 433 /*
 434  * Internal Definitions
 435  *
 436  * Boot Flags
 437  */
 438 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 439 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 440
 441 #define CONFIG_LAST_STAGE_INIT          /* needed to reset the damn phys */
 442
 443 /****************************************************************/
 444
 445 #define NAND_SIZE       0x00010000      /* 64K */
 446 #define NAND_BASE       0xF1000000
 447
 448 /****************************************************************/
 449
 450 /* NAND */
 451 #define CFG_NAND_LEGACY
 452 #define CFG_NAND_BASE           NAND_BASE
 453 #define CONFIG_MTD_NAND_ECC_JFFS2
 454 #define CONFIG_MTD_NAND_VERIFY_WRITE
 455 #define CONFIG_MTD_NAND_UNSAFE
 456
 457 #define CFG_MAX_NAND_DEVICE     1
 458 #undef NAND_NO_RB
 459
 460 #define SECTORSIZE              512
 461 #define ADDR_COLUMN             1
 462 #define ADDR_PAGE               2
 463 #define ADDR_COLUMN_PAGE        3
 464 #define NAND_ChipID_UNKNOWN     0x00
 465 #define NAND_MAX_FLOORS         1
 466 #define NAND_MAX_CHIPS          1
 467
 468 /* ALE = PC15, CLE = PB23, CE = PA7, F_RY_BY = PA6 */
 469 #define NAND_DISABLE_CE(nand) \
 470         do { \
 471                 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat) |=  (1 << (15 - 7)); \
 472         } while(0)
 473
 474 #define NAND_ENABLE_CE(nand) \
 475         do { \
 476                 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat) &= ~(1 << (15 - 7)); \
 477         } while(0)
 478
 479 #define NAND_CTL_CLRALE(nandptr) \
 480         do { \
 481                 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) &= ~(1 << (15 - 15)); \
 482         } while(0)
 483
 484 #define NAND_CTL_SETALE(nandptr) \
 485         do { \
 486                 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) |=  (1 << (15 - 15)); \
 487         } while(0)
 488
 489 #define NAND_CTL_CLRCLE(nandptr) \
 490         do { \
 491                 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) &= ~(1 << (31 - 23)); \
 492         } while(0)
 493
 494 #define NAND_CTL_SETCLE(nandptr) \
 495         do { \
 496                 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) |=  (1 << (31 - 23)); \
 497         } while(0)
 498
 499 #ifndef NAND_NO_RB
 500 #define NAND_WAIT_READY(nand) \
 501         do { \
 502                 int _tries = 0; \
 503                 while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat & (1 << (15 - 6))) == 0) \
 504                         if (++_tries > 100000) \
 505                                 break; \
 506         } while (0)
 507 #else
 508 #define NAND_WAIT_READY(nand) udelay(12)
 509 #endif
 510
 511 #define WRITE_NAND_COMMAND(d, adr) \
 512         do { \
 513                 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
 514         } while(0)
 515
 516 #define WRITE_NAND_ADDRESS(d, adr) \
 517         do { \
 518                 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
 519         } while(0)
 520
 521 #define WRITE_NAND(d, adr) \
 522         do { \
 523                 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
 524         } while(0)
 525
 526 #define READ_NAND(adr) \
 527         ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
 528
 529 /*****************************************************************************/
 530
 531 #define CFG_DIRECT_FLASH_TFTP
 532 #define CFG_DIRECT_NAND_TFTP
 533
 534 /*****************************************************************************/
 535
 536 /* Status Leds are on the MODCK pins, which become the PCMCIA PGCRB,
 537  * CxOE and CxRESET.  We use the CxOE.
 538  */
 539 #define STATUS_LED_BIT          0x00000080              /* bit 24 */
 540
 541 #define STATUS_LED_PERIOD       (CFG_HZ / 2)
 542 #define STATUS_LED_STATE        STATUS_LED_BLINKING
 543
 544 #define STATUS_LED_ACTIVE       0               /* LED on for bit == 0  */
 545 #define STATUS_LED_BOOT         0               /* LED 0 used for boot status */
 546
 547 #ifndef __ASSEMBLY__
 548
 549 /* LEDs */
 550
 551 /* led_id_t is unsigned int mask */
 552 typedef unsigned int led_id_t;
 553
 554 #define __led_toggle(_msk) \
 555         do { \
 556                 ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \
 557         } while(0)
 558
 559 #define __led_set(_msk, _st) \
 560         do { \
 561                 if ((_st)) \
 562                         ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \
 563                 else \
 564                         ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \
 565         } while(0)
 566
 567 #define __led_init(msk, st) __led_set(msk, st)
 568
 569 #endif
 570
 571 /******************************************************************************/
 572
 573 #define CFG_CONSOLE_IS_IN_ENV           1
 574 #define CFG_CONSOLE_OVERWRITE_ROUTINE   1
 575 #define CFG_CONSOLE_ENV_OVERWRITE       1
 576
 577 /******************************************************************************/
 578
 579 /* use board specific hardware */
 580 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 581 #define CONFIG_HW_WATCHDOG
 582 #define CONFIG_SHOW_ACTIVITY
 583
 584 /*****************************************************************************/
 585
 586 #define CONFIG_AUTO_COMPLETE    1
 587 #define CONFIG_CRC32_VERIFY     1
 588 #define CONFIG_HUSH_OLD_PARSER_COMPATIBLE       1
 589
 590 /*****************************************************************************/
 591
 592 /* pass open firmware flat tree */
 593 #define CONFIG_OF_FLAT_TREE     1
 594
 595 #define OF_CPU                  "PowerPC,MPC870@0"
 596 #define OF_TBCLK                (MPC8XX_HZ / 16)
 597
 598 #endif  /* __CONFIG_H */