include/configs/shannon.h

   1 /*
   2  * (C) Copyright 2002
   3  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   4  * Alex Zuepke <azu@sysgo.de>
   5  *
   6  * Configuation settings for the Shannon/TuxScreen/IS2630 WebPhone Board.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*
  31  * Since we use the Inferno-Loader to bring us to live,
  32  * we skip the lowlevel init stuff.
  33  * But U-Boot still relocates itself into RAM
  34  */
  35 #define CONFIG_INFERNO                  /* we are using the inferno bootldr */
  36 #define CONFIG_SKIP_LOWLEVEL_INIT       1
  37 #undef  CONFIG_SKIP_RELOCATE_UBOOT
  38
  39 /*
  40  * High Level Configuration Options
  41  * (easy to change)
  42  */
  43 #define CONFIG_SA1100           1       /* This is an SA1100 CPU        */
  44 #define CONFIG_SHANNON          1       /* on an SHANNON/TuxScreen Board      */
  45
  46 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
  47
  48 /*
  49  * Size of malloc() pool
  50  */
  51 #define CFG_MALLOC_LEN          (CFG_ENV_SIZE + 128*1024)
  52 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
  53
  54 /*
  55  * Hardware drivers
  56  */
  57 #define CONFIG_DRIVER_3C589     1
  58
  59 /*
  60  * select serial console configuration
  61  */
  62 #define CONFIG_SERIAL3          1       /* we use SERIAL 3  */
  63
  64 /* allow to overwrite serial and ethaddr */
  65 #define CONFIG_ENV_OVERWRITE
  66
  67 #define CONFIG_BAUDRATE         115200
  68
  69
  70 /*
  71  * BOOTP options
  72  */
  73 #define CONFIG_BOOTP_BOOTFILESIZE
  74 #define CONFIG_BOOTP_BOOTPATH
  75 #define CONFIG_BOOTP_GATEWAY
  76 #define CONFIG_BOOTP_HOSTNAME
  77
  78
  79 /*
  80  * Command line configuration.
  81  */
  82 #include <config_cmd_default.h>
  83
  84
  85 #define CONFIG_BOOTDELAY        3
  86 #define CONFIG_BOOTARGS         "root=ramfs devfs=mount console=ttySA0,115200"
  87 #define CONFIG_NETMASK          255.255.0.0
  88 #define CONFIG_BOOTCOMMAND      "help"
  89
  90 #if defined(CONFIG_CMD_KGDB)
  91 #define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
  92 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
  93 #endif
  94
  95 /*
  96  * Miscellaneous configurable options
  97  */
  98 #define CFG_LONGHELP                            /* undef to save memory         */
  99 #define CFG_PROMPT              "TuxScreen # "  /* Monitor Command Prompt       */
 100 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
 101 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 102 #define CFG_MAXARGS             16              /* max number of command args   */
 103 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 104
 105 #define CFG_MEMTEST_START       0xc0400000      /* memtest works on     */
 106 #define CFG_MEMTEST_END         0xc0800000      /* 4 ... 8 MB in DRAM   */
 107
 108 #undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
 109
 110 #define CFG_LOAD_ADDR           0xd0000000      /* default load address */
 111
 112 #define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
 113 #define CFG_CPUSPEED            0x09            /* 190 MHz for Shannon */
 114
 115                                                 /* valid baudrates */
 116 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 117
 118 #define CONFIG_DOS_PARTITION    1               /* DOS partitiion support */
 119
 120 /*-----------------------------------------------------------------------
 121  * Stack sizes
 122  *
 123  * The stack sizes are set up in start.S using the settings below
 124  */
 125 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 126 #ifdef CONFIG_USE_IRQ
 127 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
 128 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 129 #endif
 130
 131 /*-----------------------------------------------------------------------
 132  * Physical Memory Map
 133  */
 134 /* BE CAREFUL */
 135 #define CONFIG_NR_DRAM_BANKS    4          /* we have 4 banks of EDORAM */
 136 #define PHYS_SDRAM_1            0xc0000000 /* RAM Bank #1 */
 137 #define PHYS_SDRAM_1_SIZE       0x00400000 /* 4 MB */
 138 #define PHYS_SDRAM_2            0xc8000000 /* RAM Bank #2 */
 139 #define PHYS_SDRAM_2_SIZE       0x00400000 /* 4 MB */
 140 #define PHYS_SDRAM_3            0xd0000000 /* RAM Bank #3 */
 141 #define PHYS_SDRAM_3_SIZE       0x00400000 /* 4 MB */
 142 #define PHYS_SDRAM_4            0xd8000000 /* RAM Bank #4 */
 143 #define PHYS_SDRAM_4_SIZE       0x00400000 /* 4 MB */
 144
 145
 146 #define PHYS_FLASH_1            0x00000000 /* Flash Bank #1 */
 147 #define PHYS_FLASH_SIZE         0x00400000 /* 4 MB */
 148
 149 #define CFG_FLASH_BASE          PHYS_FLASH_1
 150
 151 /*-----------------------------------------------------------------------
 152  * FLASH and environment organization
 153  */
 154 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 155 #define CFG_MAX_FLASH_SECT      (31+4)  /* max number of sectors on one chip    */
 156
 157 /* timeout values are in ticks */
 158 #define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ) /* Timeout for Flash Erase */
 159 #define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ) /* Timeout for Flash Write */
 160
 161 #define CFG_ENV_IS_IN_FLASH     1
 162 #ifdef CONFIG_INFERNO
 163 /* we take the last sector, 128 KB in size, but we only use 4 KB of it for stack reasons */
 164 #define CFG_ENV_ADDR            (PHYS_FLASH_1 + 0x003E0000)     /* Addr of Environment Sector   */
 165 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 166 #else
 167 #define CFG_ENV_ADDR            (PHYS_FLASH_1 + 0x1C000)        /* Addr of Environment Sector   */
 168 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 169 #endif
 170
 171 /*-----------------------------------------------------------------------
 172  * PCMCIA stuff
 173  *-----------------------------------------------------------------------
 174  *
 175  */
 176
 177 /* we pick the upper one */
 178
 179 #define CONFIG_PCMCIA_SLOT_A
 180
 181 #define CFG_PCMCIA_IO_ADDR      (0x20000000)
 182 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 183 #define CFG_PCMCIA_DMA_ADDR     (0x24000000)
 184 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 185 #define CFG_PCMCIA_ATTRB_ADDR   (0x2C000000)
 186 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 187 #define CFG_PCMCIA_MEM_ADDR     (0x28000000)
 188 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 189
 190 /* in fact, MEM and ATTRB are swapped - has to be corrected soon in cmd_pcmcia or so */
 191
 192 /*-----------------------------------------------------------------------
 193  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 194  *-----------------------------------------------------------------------
 195  */
 196
 197 #define CONFIG_IDE_PCCARD       1       /* Use IDE with PC Card Adapter */
 198
 199 #undef  CONFIG_IDE_PCMCIA               /* Direct IDE    not supported  */
 200 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 201 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 202
 203 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 204 #define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
 205
 206 #define CFG_ATA_IDE0_OFFSET     0x0000
 207
 208 /* it's simple, all regs are in I/O space */
 209 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_ATTRB_ADDR
 210
 211 /* Offset for data I/O                  */
 212 #define CFG_ATA_DATA_OFFSET     0
 213
 214 /* Offset for normal register accesses  */
 215 #define CFG_ATA_REG_OFFSET      0
 216
 217 /* Offset for alternate registers       */
 218 #define CFG_ATA_ALT_OFFSET      0
 219
 220 /*-----------------------------------------------------------------------
 221  */
 222
 223 #endif  /* __CONFIG_H */