include/configs/scb9328.h

   1 /*
   2  * Copyright (C) 2003 ETC s.r.o.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation; either version 2 of
   7  * the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17  * MA 02111-1307 USA
  18  *
  19  * Written by Peter Figuli <peposh@etc.sk>, 2003.
  20  *
  21  * 2003/13/06 Initial MP10 Support copied from wepep250
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 #define CONFIG_ARM920T          1     /* this is an ARM920T CPU     */
  28 #define CONFIG_IMX              1     /* in a Motorola MC9328MXL Chip */
  29 #define CONFIG_SCB9328          1     /* on a scb9328tronix board */
  30 #undef  CONFIG_USE_IRQ                /* don't need use IRQ/FIQ    */
  31
  32 #define CONFIG_IMX_SERIAL1
  33 /*
  34  * Select serial console configuration
  35  */
  36
  37
  38 /*
  39  * BOOTP options
  40  */
  41 #define CONFIG_BOOTP_BOOTFILESIZE
  42 #define CONFIG_BOOTP_BOOTPATH
  43 #define CONFIG_BOOTP_GATEWAY
  44 #define CONFIG_BOOTP_HOSTNAME
  45
  46
  47 /*
  48  * Command line configuration.
  49  */
  50 #include <config_cmd_default.h>
  51
  52 #define CONFIG_CMD_NET
  53 #define CONFIG_CMD_PING
  54 #define CONFIG_CMD_DHCP
  55
  56 #undef CONFIG_CMD_LOADS
  57 #undef CONFIG_CMD_CONSOLE
  58 #undef CONFIG_CMD_AUTOSCRIPT
  59
  60
  61 /*
  62  * Boot options. Setting delay to -1 stops autostart count down.
  63  * NOTE: Sending parameters to kernel depends on kernel version and
  64  * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
  65  * parameters at all! Do not get confused by them so.
  66  */
  67 #define CONFIG_BOOTDELAY   -1
  68 #define CONFIG_BOOTARGS    "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328"
  69 #define CONFIG_BOOTCOMMAND "bootm 10040000"
  70 #define CONFIG_SHOW_BOOT_PROGRESS
  71 #define CONFIG_ETHADDR          80:81:82:83:84:85
  72 #define CONFIG_NETMASK          255.255.255.0
  73 #define CONFIG_IPADDR           10.10.10.9
  74 #define CONFIG_SERVERIP         10.10.10.10
  75
  76 /*
  77  * General options for u-boot. Modify to save memory foot print
  78  */
  79 #define CFG_LONGHELP                                  /* undef saves memory  */
  80 #define CFG_PROMPT              "scb9328> "           /* prompt string       */
  81 #define CFG_CBSIZE              256                   /* console I/O buffer  */
  82 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size   */
  83 #define CFG_MAXARGS             16                    /* max command args    */
  84 #define CFG_BARGSIZE            CFG_CBSIZE            /* boot args buf size  */
  85
  86 #define CFG_MEMTEST_START       0x08100000            /* memtest test area   */
  87 #define CFG_MEMTEST_END         0x08F00000
  88
  89 #undef  CFG_CLKS_IN_HZ                       /* use HZ for freq. display     */
  90
  91 #define CFG_HZ                  3686400      /* incrementer freq: 3.6864 MHz */
  92 #define CFG_CPUSPEED            0x141        /* core clock - register value  */
  93
  94 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
  95 #define CONFIG_BAUDRATE 115200
  96 /*
  97  * Definitions related to passing arguments to kernel.
  98  */
  99 #define CONFIG_CMDLINE_TAG           1   /* send commandline to Kernel       */
 100 #define CONFIG_SETUP_MEMORY_TAGS     1   /* send memory definition to kernel */
 101 #define CONFIG_INITRD_TAG            1   /* send initrd params               */
 102 #undef  CONFIG_VFD                       /* do not send framebuffer setup    */
 103
 104
 105 /*
 106  * Malloc pool need to host env + 128 Kb reserve for other allocations.
 107  */
 108 #define CFG_MALLOC_LEN          (CFG_ENV_SIZE + (128<<10) )
 109
 110
 111 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 112
 113 #define CONFIG_STACKSIZE        (120<<10)      /* stack size                 */
 114
 115 #ifdef CONFIG_USE_IRQ
 116 #define CONFIG_STACKSIZE_IRQ    (4<<10)        /* IRQ stack                  */
 117 #define CONFIG_STACKSIZE_FIQ    (4<<10)        /* FIQ stack                  */
 118 #endif
 119
 120 /* SDRAM Setup Values
 121 0x910a8300 Precharge Command CAS 3
 122 0x910a8200 Precharge Command CAS 2
 123
 124 0xa10a8300 AutoRefresh Command CAS 3
 125 0xa10a8200 Set AutoRefresh Command CAS 2 */
 126
 127 #define PRECHARGE_CMD 0x910a8200
 128 #define AUTOREFRESH_CMD 0xa10a8200
 129
 130 /*
 131  * SDRAM Memory Map
 132  */
 133 /* SH FIXME */
 134 #define CONFIG_NR_DRAM_BANKS    1               /* we have 1 bank of SDRAM */
 135 #define SCB9328_SDRAM_1         0x08000000      /* SDRAM bank #1           */
 136 #define SCB9328_SDRAM_1_SIZE    0x01000000      /* 16 MB                   */
 137
 138 /*
 139  * Flash Controller settings
 140  */
 141
 142 /*
 143  * Hardware drivers
 144  */
 145
 146
 147 /*
 148  * Configuration for FLASH memory for the Synertronixx board
 149  */
 150
 151 /* #define SCB9328_FLASH_32M */
 152
 153 /* 32MB */
 154 #ifdef SCB9328_FLASH_32M
 155 #define CFG_MAX_FLASH_BANKS             1       /* FLASH banks count (not chip count)*/
 156 #define CFG_MAX_FLASH_SECT              256     /* number of sector in FLASH bank    */
 157 #define SCB9328_FLASH_BUS_WIDTH         2       /* we use 16 bit FLASH memory...     */
 158 #define SCB9328_FLASH_INTERLEAVE        1       /* ... made of 1 chip                */
 159 #define SCB9328_FLASH_BANK_SIZE  0x02000000     /* size of one flash bank            */
 160 #define SCB9328_FLASH_SECT_SIZE  0x00020000     /* size of erase sector              */
 161 #define SCB9328_FLASH_BASE       0x10000000     /* location of flash memory          */
 162 #define SCB9328_FLASH_UNLOCK            1       /* perform hw unlock first           */
 163 #else
 164
 165 /* 16MB */
 166 #define CFG_MAX_FLASH_BANKS             1       /* FLASH banks count (not chip count)*/
 167 #define CFG_MAX_FLASH_SECT              128     /* number of sector in FLASH bank    */
 168 #define SCB9328_FLASH_BUS_WIDTH         2       /* we use 16 bit FLASH memory...     */
 169 #define SCB9328_FLASH_INTERLEAVE        1       /* ... made of 1 chip                */
 170 #define SCB9328_FLASH_BANK_SIZE  0x01000000     /* size of one flash bank            */
 171 #define SCB9328_FLASH_SECT_SIZE  0x00020000     /* size of erase sector              */
 172 #define SCB9328_FLASH_BASE       0x10000000     /* location of flash memory          */
 173 #define SCB9328_FLASH_UNLOCK            1       /* perform hw unlock first           */
 174 #endif /* SCB9328_FLASH_32M */
 175
 176 /* This should be defined if CFI FLASH device is present. Actually benefit
 177    is not so clear to me. In other words we can provide more informations
 178    to user, but this expects more complex flash handling we do not provide
 179    now.*/
 180 #undef  CFG_FLASH_CFI
 181
 182 #define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ)    /* timeout for Erase operation */
 183 #define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ)    /* timeout for Write operation */
 184
 185 #define CFG_FLASH_BASE          SCB9328_FLASH_BASE
 186
 187 /*
 188  * This is setting for JFFS2 support in u-boot.
 189  * Right now there is no gain for user, but later on booting kernel might be
 190  * possible. Consider using XIP kernel running from flash to save RAM
 191  * footprint.
 192  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 193  */
 194 #define CFG_JFFS2_FIRST_BANK            0
 195 #define CFG_JFFS2_FIRST_SECTOR          5
 196 #define CFG_JFFS2_NUM_BANKS             1
 197
 198 /*
 199  * Environment setup. Definitions of monitor location and size with
 200  * definition of environment setup ends up in 2 possibilities.
 201  * 1. Embeded environment - in u-boot code is space for environment
 202  * 2. Environment is read from predefined sector of flash
 203  * Right now we support 2. possiblity, but expecting no env placed
 204  * on mentioned address right now. This also needs to provide whole
 205  * sector for it - for us 256Kb is really waste of memory. U-boot uses
 206  * default env. and until kernel parameters could be sent to kernel
 207  * env. has no sense to us.
 208  */
 209
 210 /* Setup for PA23 which is Reset Default PA23 but has to become
 211    CS5 */
 212
 213 #define CFG_GPR_A_VAL           0x00800000
 214 #define CFG_GIUS_A_VAL          0x0043fffe
 215
 216 #define CFG_MONITOR_BASE        0x10000000
 217 #define CFG_MONITOR_LEN         0x20000         /* 128b ( 1 flash sector )  */
 218 #define CFG_ENV_IS_IN_FLASH     1
 219 #define CFG_ENV_ADDR            0x10020000      /* absolute address for now  */
 220 #define CFG_ENV_SIZE            0x20000
 221
 222 #define  CONFIG_ENV_OVERWRITE  1                /* env is not writable now   */
 223
 224 /*
 225  * CSxU_VAL:
 226  * 63| x        x x x | x x x x | x x  x    x | x x x x | x x x x | x x x x | x x x x | x x x x|32
 227  *   |DTACK_SEL|0|BCD |   BCS   | PSZ|PME|SYNC|  DOL    | CNC|    WSC       | 0| WWS  |   EDC  |
 228  *
 229  * CSxL_VAL:
 230  * 31| x x x x | x x x x | x x x x | x x x x | x x x x |  x x x x | x x  x x | x x  x    x| 0
 231  *   |   OEA   |   OEN   |   WEA   |   WEN   |   CSA   |EBC| DSZ  | 0|SP|0|WP| 0 0|PA|CSEN|
 232  */
 233
 234 #define CFG_CS0U_VAL 0x000F2000
 235 #define CFG_CS0L_VAL 0x11110d01
 236 #define CFG_CS1U_VAL 0x000F0a00
 237 #define CFG_CS1L_VAL 0x11110601
 238 #define CFG_CS2U_VAL 0x0
 239 #define CFG_CS2L_VAL 0x0
 240
 241 #define CFG_CS3U_VAL 0x000FFFFF
 242 #define CFG_CS3L_VAL 0x00000303
 243
 244 #define CFG_CS4U_VAL 0x000F0a00
 245 #define CFG_CS4L_VAL 0x11110301
 246
 247 /* CNC == 3 too long
 248    #define CFG_CS5U_VAL 0x0000C210 */
 249
 250 /* #define CFG_CS5U_VAL 0x00008400
 251    mal laenger mahcen, ob der bei 150MHz laenger haelt dann und
 252    kaum langsamer ist */
 253 /* #define CFG_CS5U_VAL 0x00009400
 254    #define CFG_CS5L_VAL 0x11010D03 */
 255
 256 #define CFG_CS5U_VAL 0x00008400
 257 #define CFG_CS5L_VAL 0x00000D03
 258
 259 #define CONFIG_DRIVER_DM9000            1
 260 #define CONFIG_DRIVER_DM9000            1
 261 #define CONFIG_DM9000_BASE              0x16000000
 262 #define DM9000_IO                       CONFIG_DM9000_BASE
 263 #define DM9000_DATA                     (CONFIG_DM9000_BASE+4)
 264 /* #define CONFIG_DM9000_USE_8BIT */
 265 #define CONFIG_DM9000_USE_16BIT
 266 /* #define CONFIG_DM9000_USE_32BIT */
 267
 268 /* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
 269    f_ref=16,777MHz
 270
 271    0x002a141f: 191,9944MHz
 272    0x040b2007: 144MHz
 273    0x042a141f: 96MHz
 274    0x0811140d: 64MHz
 275    0x040e200e: 150MHz
 276    0x00321431: 200MHz
 277
 278    0x08001800: 64MHz mit 16er Quarz
 279    0x04001800: 96MHz mit 16er Quarz
 280    0x04002400: 144MHz mit 16er Quarz
 281
 282    31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
 283       |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------|     */
 284
 285 #define CPU200
 286
 287 #ifdef CPU200
 288 #define CFG_MPCTL0_VAL 0x00321431
 289 #else
 290 #define CFG_MPCTL0_VAL 0x040e200e
 291 #endif
 292
 293 /* #define BUS64 */
 294 #define BUS72
 295
 296 #ifdef BUS72
 297 #define CFG_SPCTL0_VAL 0x04002400
 298 #endif
 299
 300 #ifdef BUS96
 301 #define CFG_SPCTL0_VAL 0x04001800
 302 #endif
 303
 304 #ifdef BUS64
 305 #define CFG_SPCTL0_VAL 0x08001800
 306 #endif
 307
 308 /* Das ist der BCLK Divider, der aus der System PLL
 309    BCLK und HCLK erzeugt:
 310    31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0
 311    0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2
 312    0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2
 313    0x2f001003 : 192MHz/5=38,4MHz
 314    0x2f000003 : 64MHz/1
 315    Bit 22: SPLL Restart
 316    Bit 21: MPLL Restart */
 317
 318 #ifdef BUS64
 319 #define CFG_CSCR_VAL 0x2f030003
 320 #endif
 321
 322 #ifdef BUS72
 323 #define CFG_CSCR_VAL 0x2f030403
 324 #endif
 325
 326 /*
 327  * Well this has to be defined, but on the other hand it is used differently
 328  * one may expect. For instance loadb command do not cares :-)
 329  * So advice is - do not relay on this...
 330  */
 331 #define CFG_LOAD_ADDR 0x08400000
 332
 333 #define MHZ16QUARZINUSE
 334
 335 #ifdef MHZ16QUARZINUSE
 336 #define CONFIG_SYSPLL_CLK_FREQ 16000000
 337 #else
 338 #define CONFIG_SYSPLL_CLK_FREQ 16780000
 339 #endif
 340
 341 #define CONFIG_SYS_CLK_FREQ 16780000
 342
 343 /* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */
 344 #define CFG_FMCR_VAL 0x00000001
 345
 346 /* Bit[0:3] contain PERCLK1DIV for UART 1
 347    0x000b00b ->b<- -> 192MHz/12=16MHz
 348    0x000b00b ->8<- -> 144MHz/09=16MHz
 349    0x000b00b ->3<- -> 64MHz/4=16MHz */
 350
 351 #ifdef BUS96
 352 #define CFG_PCDR_VAL 0x000b00b5
 353 #endif
 354
 355 #ifdef BUS64
 356 #define CFG_PCDR_VAL 0x000b00b3
 357 #endif
 358
 359 #ifdef BUS72
 360 #define CFG_PCDR_VAL 0x000b00b8
 361 #endif
 362
 363 #endif  /* __CONFIG_H */