include/configs/mgcoge.h

   1 /*
   2  * (C) Copyright 2007
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31
  32 #define CONFIG_MPC8247          1
  33 #define CONFIG_MPC8272_FAMILY   1
  34 #define CONFIG_MGCOGE           1
  35
  36 #define CONFIG_CPM2             1       /* Has a CPM2 */
  37
  38 /* Do boardspecific init */
  39 #define CONFIG_BOARD_EARLY_INIT_R       1
  40
  41 /*
  42  * Select serial console configuration
  43  *
  44  * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  45  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  46  * for SCC).
  47  */
  48 #define CONFIG_CONS_ON_SMC              /* Console is on SMC         */
  49 #undef  CONFIG_CONS_ON_SCC              /* It's not on SCC           */
  50 #undef  CONFIG_CONS_NONE                /* It's not on external UART */
  51 #define CONFIG_CONS_INDEX       2       /* SMC2 is used for console  */
  52
  53 /*
  54  * Select ethernet configuration
  55  *
  56  * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
  57  * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
  58  * SCC, 1-3 for FCC)
  59  *
  60  * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
  61  * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
  62  * must be unset.
  63  */
  64 #define CONFIG_ETHER_ON_SCC             /* Ethernet is on SCC */
  65 #undef  CONFIG_ETHER_ON_FCC             /* Ethernet is not on FCC     */
  66 #undef  CONFIG_ETHER_NONE               /* No external Ethernet   */
  67
  68 #define CONFIG_ETHER_INDEX      4
  69 #define CFG_SCC_TOUT_LOOP       10000000
  70
  71 # define CFG_CMXSCR_VALUE       (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
  72
  73 #ifndef CONFIG_8260_CLKIN
  74 #define CONFIG_8260_CLKIN       66000000        /* in Hz */
  75 #endif
  76
  77 #define CONFIG_BAUDRATE         115200
  78
  79 /*
  80  * Command line configuration.
  81  */
  82 #include <config_cmd_default.h>
  83
  84 #define CONFIG_CMD_ECHO
  85 #define CONFIG_CMD_IMMAP
  86 #define CONFIG_CMD_MII
  87 #define CONFIG_CMD_PING
  88
  89 /*
  90  * Default environment settings
  91  */
  92 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  93         "netdev=eth0\0"                                                 \
  94         "u-boot_addr=100000\0"                                          \
  95         "kernel_addr=200000\0"                                          \
  96         "fdt_addr=400000\0"                                             \
  97         "rootpath=/opt/eldk-4.2/ppc_82xx\0"                             \
  98         "u-boot=/tftpboot/mgcoge/u-boot.bin\0"                          \
  99         "bootfile=/tftpboot/mgcoge/uImage\0"                            \
 100         "fdt_file=/tftpboot/mgcoge/mgcoge.dtb\0"                        \
 101         "load=tftp ${u-boot_addr} ${u-boot}\0"                          \
 102         "update=prot off fe000000 fe03ffff; era fe000000 fe03ffff; "    \
 103                 "cp.b ${u-boot_addr} fe000000 ${filesize};"             \
 104                 "prot on fe000000 fe03ffff\0"                           \
 105         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 106         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 107                 "nfsroot=${serverip}:${rootpath}\0"                     \
 108         "addcon=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0"      \
 109         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
 110         "addip=setenv bootargs ${bootargs} "                            \
 111                 "ip=${ipaddr}:${serverip}:${gatewayip}:"                \
 112                 "${netmask}:${hostname}:${netdev}:off panic=1\0"        \
 113         "net_nfs=tftp ${kernel_addr} ${bootfile}; "                     \
 114                 "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcon;"\
 115                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 116         "net_self=tftp ${kernel_addr} ${bootfile}; "                    \
 117                 "tftp ${fdt_addr} ${fdt_file}; "                        \
 118                 "tftp ${ramdisk_addr} ${ramdisk_file}; "                \
 119                 "run ramargs addip; "                                   \
 120                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 121         ""
 122 #define CONFIG_BOOTCOMMAND      "run net_nfs"
 123 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 124
 125 #undef  CONFIG_WATCHDOG                 /* disable platform specific watchdog */
 126
 127 /*
 128  * Miscellaneous configurable options
 129  */
 130 #define CFG_HUSH_PARSER
 131 #define CFG_PROMPT_HUSH_PS2     "> "
 132 #define CFG_LONGHELP                    /* undef to save memory     */
 133 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt   */
 134 #if defined(CONFIG_CMD_KGDB)
 135 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size  */
 136 #else
 137 #define CFG_CBSIZE              256     /* Console I/O Buffer Size  */
 138 #endif
 139 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size  */
 140 #define CFG_MAXARGS             16              /* max number of command args */
 141 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size  */
 142
 143 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 144 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 145
 146 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 147
 148 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 149
 150 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
 151
 152 #define CFG_SDRAM_BASE          0x00000000
 153 #define CFG_FLASH_BASE          0xFE000000
 154 #define CFG_FLASH_SIZE          32
 155 #define CFG_FLASH_CFI
 156 #define CFG_FLASH_CFI_DRIVER
 157 #define CFG_MAX_FLASH_BANKS     2       /* max num of flash banks       */
 158 #define CFG_MAX_FLASH_SECT      512     /* max num of sects on one chip */
 159
 160 #define CFG_FLASH_BASE_1        0x50000000
 161 #define CFG_FLASH_SIZE_1        64
 162
 163 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE_1 }
 164
 165 #define CFG_MONITOR_BASE        TEXT_BASE
 166 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 167 #define CFG_RAMBOOT
 168 #endif
 169
 170 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256KB for Monitor */
 171
 172 #define CFG_ENV_IS_IN_FLASH
 173
 174 #ifdef CFG_ENV_IS_IN_FLASH
 175 #define CFG_ENV_SECT_SIZE       0x20000
 176 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 177 #endif /* CFG_ENV_IS_IN_FLASH */
 178
 179 #define CFG_IMMR                0xF0000000
 180
 181 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 182 #define CFG_INIT_RAM_END        0x2000  /* End of used area in DPRAM    */
 183 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 184 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 185 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 186
 187 /* Hard reset configuration word */
 188 #define CFG_HRCW_MASTER         0x0604b211
 189
 190 /* No slaves */
 191 #define CFG_HRCW_SLAVE1         0
 192 #define CFG_HRCW_SLAVE2         0
 193 #define CFG_HRCW_SLAVE3         0
 194 #define CFG_HRCW_SLAVE4         0
 195 #define CFG_HRCW_SLAVE5         0
 196 #define CFG_HRCW_SLAVE6         0
 197 #define CFG_HRCW_SLAVE7         0
 198
 199 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
 200 #define BOOTFLAG_WARM           0x02    /* Software reboot                  */
 201
 202 #define CFG_MALLOC_LEN          (4096 << 10)    /* Reserve 4 MB for malloc()    */
 203 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 204
 205 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPUs */
 206 #if defined(CONFIG_CMD_KGDB)
 207 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
 208 #endif
 209
 210 #define CFG_HID0_INIT           0
 211 #define CFG_HID0_FINAL          (HID0_ICE | HID0_IFEM | HID0_ABE)
 212
 213 #define CFG_HID2                0
 214
 215 #define CFG_SIUMCR              0x4020c200
 216 #define CFG_SYPCR               0xFFFFFFC3
 217 #define CFG_BCR                 0x10000000
 218 #define CFG_SCCR                (SCCR_PCI_MODE | SCCR_PCI_MODCK)
 219
 220 /*-----------------------------------------------------------------------
 221  * RMR - Reset Mode Register                                     5-5
 222  *-----------------------------------------------------------------------
 223  * turn on Checkstop Reset Enable
 224  */
 225 #define CFG_RMR         0
 226
 227 /*-----------------------------------------------------------------------
 228  * TMCNTSC - Time Counter Status and Control                     4-40
 229  *-----------------------------------------------------------------------
 230  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 231  * and enable Time Counter
 232  */
 233 #define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 234
 235 /*-----------------------------------------------------------------------
 236  * PISCR - Periodic Interrupt Status and Control                 4-42
 237  *-----------------------------------------------------------------------
 238  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 239  * Periodic timer
 240  */
 241 #define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 242
 243 /*-----------------------------------------------------------------------
 244  * RCCR - RISC Controller Configuration                         13-7
 245  *-----------------------------------------------------------------------
 246  */
 247 #define CFG_RCCR        0
 248
 249 /*
 250  * Init Memory Controller:
 251  *
 252  * Bank Bus     Machine PortSz  Device
 253  * ---- ---     ------- ------  ------
 254  *  0   60x     GPCM     8 bit  FLASH
 255  *  1   60x     SDRAM   32 bit  SDRAM
 256  *  3   60x     GPCM     8 bit  GPIO/PIGGY
 257  *  5   60x     GPCM    16 bit  CFG-Flash
 258  *
 259  */
 260 /* Bank 0 - FLASH
 261  */
 262 #define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
 263                          BRx_PS_8                       |\
 264                          BRx_MS_GPCM_P                  |\
 265                          BRx_V)
 266
 267 #define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)      |\
 268                          ORxG_CSNT                      |\
 269                          ORxG_ACS_DIV2                  |\
 270                          ORxG_SCY_5_CLK                 |\
 271                          ORxG_TRLX )
 272
 273
 274 /* Bank 1 - 60x bus SDRAM
 275  */
 276 #define SDRAM_MAX_SIZE  0x08000000      /* max. 128 MB          */
 277 #define CFG_GLOBAL_SDRAM_LIMIT  (256 << 20)     /* less than 256 MB */
 278
 279 #define CFG_MPTPR       0x1800
 280
 281 /*-----------------------------------------------------------------------------
 282  * Address for Mode Register Set (MRS) command
 283  *-----------------------------------------------------------------------------
 284  */
 285 #define CFG_MRS_OFFS    0x00000110
 286 #define CFG_PSRT        0x0e
 287
 288 #define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
 289                          BRx_PS_64                      |\
 290                          BRx_MS_SDRAM_P                 |\
 291                          BRx_V)
 292
 293 #define CFG_OR1_PRELIM  CFG_OR1
 294
 295 /* SDRAM initialization values
 296 */
 297
 298 #define CFG_OR1    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 299                          ORxS_BPD_8                     |\
 300                          ORxS_ROWST_PBI0_A7             |\
 301                          ORxS_NUMR_13)
 302
 303 #define CFG_PSDMR  (PSDMR_SDAM_A14_IS_A5 |\
 304                          PSDMR_BSMA_A14_A16           |\
 305                          PSDMR_SDA10_PBI0_A9            |\
 306                          PSDMR_RFRC_5_CLK               |\
 307                          PSDMR_PRETOACT_2W              |\
 308                          PSDMR_ACTTORW_2W               |\
 309                          PSDMR_LDOTOPRE_1C              |\
 310                          PSDMR_WRC_1C                   |\
 311                          PSDMR_CL_2)
 312
 313 /* GPIO/PIGGY on CS3 initialization values
 314 */
 315 #define CFG_PIGGY_BASE  0x30000000
 316 #define CFG_PIGGY_SIZE  128
 317
 318 #define CFG_BR3_PRELIM  ((CFG_PIGGY_BASE & BRx_BA_MSK) |\
 319                          BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
 320
 321 #define CFG_OR3_PRELIM  (MEG_TO_AM(CFG_PIGGY_SIZE) |\
 322                          ORxG_CSNT | ORxG_ACS_DIV2 |\
 323                          ORxG_SCY_3_CLK | ORxG_TRLX )
 324
 325 /* CFG-Flash on CS5 initialization values
 326 */
 327 #define CFG_BR5_PRELIM  ((CFG_FLASH_BASE_1 & BRx_BA_MSK) |\
 328                          BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
 329
 330 #define CFG_OR5_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE_1) |\
 331                          ORxG_CSNT | ORxG_ACS_DIV2 |\
 332                          ORxG_SCY_5_CLK | ORxG_TRLX )
 333
 334 #define CFG_RESET_ADDRESS 0xFDFFFFFC    /* "bad" address                */
 335
 336 /* pass open firmware flat tree */
 337 #define CONFIG_OF_LIBFDT        1
 338 #define CONFIG_OF_BOARD_SETUP   1
 339
 340 #define OF_CPU                  "PowerPC,8247@0"
 341 #define OF_SOC                  "soc@f0000000"
 342 #define OF_TBCLK                (bd->bi_busfreq / 4)
 343 #define OF_STDOUT_PATH          "/soc/cpm/serial@11a90"
 344
 345 #endif /* __CONFIG_H */