include/configs/kilauea.h

   1 /*
   2  * (C) Copyright 2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /************************************************************************
  25  * kilauea.h - configuration for AMCC Kilauea (405EX)
  26  ***********************************************************************/
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*-----------------------------------------------------------------------
  32  * High Level Configuration Options
  33  *----------------------------------------------------------------------*/
  34 #define CONFIG_KILAUEA          1               /* Board is Kilauea     */
  35 #define CONFIG_4xx              1               /* ... PPC4xx family    */
  36 #define CONFIG_405EX            1               /* Specifc 405EX support*/
  37 #define CONFIG_SYS_CLK_FREQ     33333333        /* ext frequency to pll */
  38
  39 #define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f */
  40 #define CONFIG_MISC_INIT_R      1               /* Call misc_init_r     */
  41 #define CONFIG_BOARD_EMAC_COUNT
  42
  43 /*-----------------------------------------------------------------------
  44  * Base addresses -- Note these are effective addresses where the
  45  * actual resources get mapped (not physical addresses)
  46  *----------------------------------------------------------------------*/
  47 #define CFG_SDRAM_BASE          0x00000000
  48 #define CFG_FLASH_BASE          0xFC000000
  49 #define CFG_NAND_ADDR           0xF8000000
  50 #define CFG_FPGA_BASE           0xF0000000
  51 #define CFG_PERIPHERAL_BASE     0xEF600000      /* internal peripherals*/
  52 #define CFG_MONITOR_LEN         (384 * 1024)    /* Reserve 384 kB for Monitor   */
  53 #define CFG_MALLOC_LEN          (512 * 1024)    /* Reserve 512 kB for malloc()  */
  54 #define CFG_MONITOR_BASE        (TEXT_BASE)
  55
  56 /*-----------------------------------------------------------------------
  57  * Initial RAM & stack pointer
  58  *----------------------------------------------------------------------*/
  59 #define CFG_INIT_RAM_ADDR       0x02000000      /* inside of SDRAM      */
  60 #define CFG_INIT_RAM_END        (4 << 10)
  61 #define CFG_GBL_DATA_SIZE       256             /* num bytes initial data */
  62 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  63 /* reserve some memory for POST and BOOT limit info */
  64 #define CFG_INIT_SP_OFFSET      (CFG_GBL_DATA_OFFSET - 16)
  65
  66 /* extra data in init-ram */
  67 #define CFG_POST_WORD_ADDR      (CFG_GBL_DATA_OFFSET - 4)
  68 #define CFG_POST_MAGIC          (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 8)
  69 #define CFG_POST_VAL            (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 12)
  70 #define CFG_OCM_DATA_ADDR       CFG_INIT_RAM_ADDR /* for commproc.c     */
  71
  72 /*-----------------------------------------------------------------------
  73  * Serial Port
  74  *----------------------------------------------------------------------*/
  75 #define CFG_EXT_SERIAL_CLOCK    11059200        /* ext. 11.059MHz clk   */
  76 #define CONFIG_BAUDRATE         115200
  77 #define CONFIG_SERIAL_MULTI     1
  78 /* define this if you want console on UART1 */
  79 #undef CONFIG_UART1_CONSOLE
  80
  81 #define CFG_BAUDRATE_TABLE                                              \
  82         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  83
  84 /*-----------------------------------------------------------------------
  85  * Environment
  86  *----------------------------------------------------------------------*/
  87 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  88 #define CFG_ENV_IS_IN_FLASH     1       /* use FLASH for environment vars       */
  89 #else
  90 #define CFG_ENV_IS_IN_NAND      1       /* use NAND for environment vars        */
  91 #define CFG_ENV_IS_EMBEDDED     1       /* use embedded environment */
  92 #endif
  93
  94 /*-----------------------------------------------------------------------
  95  * FLASH related
  96  *----------------------------------------------------------------------*/
  97 #define CFG_FLASH_CFI                   /* The flash is CFI compatible  */
  98 #define CFG_FLASH_CFI_DRIVER            /* Use common CFI driver        */
  99
 100 #define CFG_FLASH_BANKS_LIST    {CFG_FLASH_BASE}
 101 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 102 #define CFG_MAX_FLASH_SECT      512     /* max number of sectors on one chip    */
 103
 104 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 105 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 106
 107 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
 108 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 109
 110 #ifdef CFG_ENV_IS_IN_FLASH
 111 #define CFG_ENV_SECT_SIZE       0x20000         /* size of one complete sector  */
 112 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
 113 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 114
 115 /* Address and size of Redundant Environment Sector     */
 116 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
 117 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 118 #endif /* CFG_ENV_IS_IN_FLASH */
 119
 120 /*
 121  * IPL (Initial Program Loader, integrated inside CPU)
 122  * Will load first 4k from NAND (SPL) into cache and execute it from there.
 123  *
 124  * SPL (Secondary Program Loader)
 125  * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 126  * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 127  * controller and the NAND controller so that the special U-Boot image can be
 128  * loaded from NAND to SDRAM.
 129  *
 130  * NUB (NAND U-Boot)
 131  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 132  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 133  *
 134  * On 440EPx the SPL is copied to SDRAM before the NAND controller is
 135  * set up. While still running from cache, I experienced problems accessing
 136  * the NAND controller. sr - 2006-08-25
 137  */
 138 #define CFG_NAND_BOOT_SPL_SRC   0xfffff000      /* SPL location                 */
 139 #define CFG_NAND_BOOT_SPL_SIZE  (4 << 10)       /* SPL size                     */
 140 #define CFG_NAND_BOOT_SPL_DST   0x00800000      /* Copy SPL here                */
 141 #define CFG_NAND_U_BOOT_DST     0x01000000      /* Load NUB to this addr        */
 142 #define CFG_NAND_U_BOOT_START   CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
 143 #define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
 144
 145 /*
 146  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 147  */
 148 #define CFG_NAND_U_BOOT_OFFS    (16 << 10)      /* Offset to RAM U-Boot image   */
 149 #define CFG_NAND_U_BOOT_SIZE    (384 << 10)     /* Size of RAM U-Boot image     */
 150
 151 /*
 152  * Now the NAND chip has to be defined (no autodetection used!)
 153  */
 154 #define CFG_NAND_PAGE_SIZE      512             /* NAND chip page size          */
 155 #define CFG_NAND_BLOCK_SIZE     (16 << 10)      /* NAND chip block size         */
 156 #define CFG_NAND_PAGE_COUNT     32              /* NAND chip page count         */
 157 #define CFG_NAND_BAD_BLOCK_POS  5               /* Location of bad block marker */
 158 #define CFG_NAND_4_ADDR_CYCLE   1               /* Fourth addr used (>32MB)     */
 159
 160 #define CFG_NAND_ECCSIZE        256
 161 #define CFG_NAND_ECCBYTES       3
 162 #define CFG_NAND_ECCSTEPS       (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
 163 #define CFG_NAND_OOBSIZE        16
 164 #define CFG_NAND_ECCTOTAL       (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
 165 #define CFG_NAND_ECCPOS         {0, 1, 2, 3, 6, 7}
 166
 167 #ifdef CFG_ENV_IS_IN_NAND
 168 /*
 169  * For NAND booting the environment is embedded in the U-Boot image. Please take
 170  * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
 171  */
 172 #define CFG_ENV_SIZE            CFG_NAND_BLOCK_SIZE
 173 #define CFG_ENV_OFFSET          (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
 174 #define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET + CFG_ENV_SIZE)
 175 #endif
 176
 177 /*-----------------------------------------------------------------------
 178  * NAND FLASH
 179  *----------------------------------------------------------------------*/
 180 #define CFG_MAX_NAND_DEVICE     1
 181 #define NAND_MAX_CHIPS          1
 182 #define CFG_NAND_BASE           (CFG_NAND_ADDR + CFG_NAND_CS)
 183 #define CFG_NAND_SELECT_DEVICE  1       /* nand driver supports mutipl. chips   */
 184
 185 /*-----------------------------------------------------------------------
 186  * DDR SDRAM
 187  *----------------------------------------------------------------------*/
 188 #define CFG_MBYTES_SDRAM        (256)           /* 256MB                        */
 189
 190 /*-----------------------------------------------------------------------
 191  * I2C
 192  *----------------------------------------------------------------------*/
 193 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
 194 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 195 #define CFG_I2C_SLAVE           0x7F
 196
 197 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  6       /* 24C02 requires 5ms delay */
 198 #define CFG_I2C_EEPROM_ADDR     0x52    /* I2C boot EEPROM (24C02BN)    */
 199 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address             */
 200
 201 /* Standard DTT sensor configuration */
 202 #define CONFIG_DTT_DS1775       1
 203 #define CONFIG_DTT_SENSORS      { 0 }
 204 #define CFG_I2C_DTT_ADDR        0x48
 205
 206 /* RTC configuration */
 207 #define CONFIG_RTC_DS1338       1
 208 #define CFG_I2C_RTC_ADDR        0x68
 209
 210 /*-----------------------------------------------------------------------
 211  * Ethernet
 212  *----------------------------------------------------------------------*/
 213 #define CONFIG_M88E1111_PHY     1
 214 #define CONFIG_IBM_EMAC4_V4     1
 215 #define CONFIG_MII              1       /* MII PHY management           */
 216 #define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 217
 218 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 219 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 220
 221 #define CONFIG_HAS_ETH0         1
 222
 223 #define CONFIG_NET_MULTI        1
 224 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 225 #define CONFIG_PHY1_ADDR        2
 226
 227 #define CFG_RX_ETH_BUFFER       32      /* Number of ethernet rx buffers & descriptors */
 228
 229 #define CONFIG_PREBOOT  "echo;" \
 230         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 231         "echo"
 232
 233 #undef  CONFIG_BOOTARGS
 234
 235 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 236         "logversion=2\0"                                                \
 237         "netdev=eth0\0"                                                 \
 238         "hostname=kilauea\0"                                            \
 239         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 240                 "nfsroot=${serverip}:${rootpath}\0"                     \
 241         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 242         "addip=setenv bootargs ${bootargs} "                            \
 243                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 244                 ":${hostname}:${netdev}:off panic=1\0"                  \
 245         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 246         "net_nfs=tftp 200000 ${bootfile};"                              \
 247                 "run nfsargs addip addtty;"                             \
 248                 "bootm 200000\0"                                        \
 249         "net_nfs_fdt=tftp 200000 ${bootfile};"                          \
 250                 "tftp ${fdt_addr} ${fdt_file};"                         \
 251                 "run nfsargs addip addtty;"                             \
 252                 "bootm 200000 - ${fdt_addr}\0"                          \
 253         "flash_nfs=run nfsargs addip addtty;"                           \
 254                 "bootm ${kernel_addr}\0"                                \
 255         "flash_self=run ramargs addip addtty;"                          \
 256                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 257         "rootpath=/opt/eldk/ppc_4xx\0"                                  \
 258         "bootfile=kilauea/uImage\0"                                     \
 259         "fdt_file=kilauea/kilauea.dtb\0"                                \
 260         "fdt_addr=400000\0"                                             \
 261         "kernel_addr=fc000000\0"                                        \
 262         "ramdisk_addr=fc200000\0"                                       \
 263         "initrd_high=30000000\0"                                        \
 264         "load=tftp 200000 kilauea/u-boot.bin\0"                         \
 265         "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;"   \
 266                 "cp.b ${fileaddr} fffa0000 ${filesize};"                \
 267                 "setenv filesize;saveenv\0"                             \
 268         "upd=run load update\0"                                         \
 269         "nload=tftp 200000 kilauea/u-boot-nand.bin\0"                   \
 270         "nupdate=nand erase 0 60000;nand write 200000 0 60000;"         \
 271                 "setenv filesize;saveenv\0"                             \
 272         "nupd=run nload nupdate\0"                                      \
 273         "pciconfighost=1\0"                                             \
 274         "pcie_mode=RP:RP\0"                                             \
 275         ""
 276 #define CONFIG_BOOTCOMMAND      "run flash_self"
 277
 278 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 279
 280 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 281 #define CFG_LOADS_BAUD_CHANGE           /* allow baudrate change        */
 282
 283 /*
 284  * BOOTP options
 285  */
 286 #define CONFIG_BOOTP_BOOTFILESIZE
 287 #define CONFIG_BOOTP_BOOTPATH
 288 #define CONFIG_BOOTP_GATEWAY
 289 #define CONFIG_BOOTP_HOSTNAME
 290
 291 /*
 292  * Command line configuration.
 293  */
 294 #include <config_cmd_default.h>
 295
 296 #define CONFIG_CMD_ASKENV
 297 #define CONFIG_CMD_DATE
 298 #define CONFIG_CMD_DHCP
 299 #define CONFIG_CMD_DIAG
 300 #define CONFIG_CMD_DTT
 301 #define CONFIG_CMD_EEPROM
 302 #define CONFIG_CMD_ELF
 303 #define CONFIG_CMD_I2C
 304 #define CONFIG_CMD_IRQ
 305 #define CONFIG_CMD_LOG
 306 #define CONFIG_CMD_MII
 307 #define CONFIG_CMD_NAND
 308 #define CONFIG_CMD_NET
 309 #define CONFIG_CMD_NFS
 310 #define CONFIG_CMD_PCI
 311 #define CONFIG_CMD_PING
 312 #define CONFIG_CMD_REGINFO
 313 #define CONFIG_CMD_SNTP
 314
 315 /* POST support */
 316 #define CONFIG_POST             (CFG_POST_MEMORY        | \
 317                                  CFG_POST_CACHE         | \
 318                                  CFG_POST_CPU           | \
 319                                  CFG_POST_ETHER         | \
 320                                  CFG_POST_I2C           | \
 321                                  CFG_POST_MEMORY        | \
 322                                  CFG_POST_UART)
 323
 324 /* Define here the base-addresses of the UARTs to test in POST */
 325 #define CFG_POST_UART_TABLE     {UART0_BASE, UART1_BASE}
 326
 327 #define CONFIG_LOGBUFFER
 328 #define CFG_POST_CACHE_ADDR     0x00800000 /* free virtual address      */
 329
 330 #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
 331
 332 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 333
 334 /*-----------------------------------------------------------------------
 335  * Miscellaneous configurable options
 336  *----------------------------------------------------------------------*/
 337 #define CFG_LONGHELP                    /* undef to save memory         */
 338 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 339 #if defined(CONFIG_CMD_KGDB)
 340 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 341 #else
 342 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 343 #endif
 344 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 345 #define CFG_MAXARGS             16      /* max number of command args   */
 346 #define CFG_BARGSIZE            CFG_CBSIZE /* Boot Argument Buffer Size */
 347
 348 #define CFG_MEMTEST_START       0x0400000 /* memtest works on           */
 349 #define CFG_MEMTEST_END         0x0C00000 /* 4 ... 12 MB in DRAM        */
 350
 351 #define CFG_LOAD_ADDR           0x100000  /* default load address       */
 352 #define CFG_EXTBDINFO           1       /* To use extended board_into (bd_t) */
 353
 354 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 355
 356 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 357 #define CONFIG_LOOPW            1       /* enable loopw command         */
 358 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 359 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 360 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 361 #define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
 362
 363 /*-----------------------------------------------------------------------
 364  * PCI stuff
 365  *----------------------------------------------------------------------*/
 366 #define CONFIG_PCI                      /* include pci support          */
 367 #define CONFIG_PCI_PNP          1       /* do pci plug-and-play         */
 368 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 369 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
 370
 371 /*-----------------------------------------------------------------------
 372  * PCIe stuff
 373  *----------------------------------------------------------------------*/
 374 #define CFG_PCIE_MEMBASE        0x90000000      /* mapped PCIe memory   */
 375 #define CFG_PCIE_MEMSIZE        0x08000000      /* 128 Meg, smallest incr per port */
 376
 377 #define CFG_PCIE0_CFGBASE       0xa0000000      /* remote access */
 378 #define CFG_PCIE0_XCFGBASE      0xb0000000      /* local access */
 379 #define CFG_PCIE0_CFGMASK       0xe0000001      /* 512 Meg */
 380
 381 #define CFG_PCIE1_CFGBASE       0xc0000000      /* remote access */
 382 #define CFG_PCIE1_XCFGBASE      0xd0000000      /* local access */
 383 #define CFG_PCIE1_CFGMASK       0xe0000001      /* 512 Meg */
 384
 385 #define CFG_PCIE0_UTLBASE       0xef502000
 386 #define CFG_PCIE1_UTLBASE       0xef503000
 387
 388 /* base address of inbound PCIe window */
 389 #define CFG_PCIE_INBOUND_BASE   0x0000000000000000ULL
 390
 391 /*
 392  * For booting Linux, the board info and command line data
 393  * have to be in the first 8 MB of memory, since this is
 394  * the maximum mapped by the Linux kernel during initialization.
 395  */
 396 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 397
 398 /*-----------------------------------------------------------------------
 399  * External Bus Controller (EBC) Setup
 400  *----------------------------------------------------------------------*/
 401 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 402 /* booting from NAND, so NAND chips select has to be on CS 0 */
 403 #define CFG_NAND_CS             0               /* NAND chip connected to CSx   */
 404
 405 /* Memory Bank 1 (NOR-FLASH) initialization                                     */
 406 #define CFG_EBC_PB1AP           0x05806500
 407 #define CFG_EBC_PB1CR           0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
 408
 409 /* Memory Bank 0 (NAND-FLASH) initialization                                    */
 410 #define CFG_EBC_PB0AP           0x018003c0
 411 #define CFG_EBC_PB0CR           (CFG_NAND_ADDR | 0x1e000)
 412 #else
 413 #define CFG_NAND_CS             1               /* NAND chip connected to CSx   */
 414
 415 /* Memory Bank 0 (NOR-FLASH) initialization                                     */
 416 #define CFG_EBC_PB0AP           0x05806500
 417 #define CFG_EBC_PB0CR           0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
 418
 419 /* Memory Bank 1 (NAND-FLASH) initialization                                    */
 420 #define CFG_EBC_PB1AP           0x018003c0
 421 #define CFG_EBC_PB1CR           (CFG_NAND_ADDR | 0x1e000)
 422 #endif
 423
 424 /* Memory Bank 2 (FPGA) initialization                                          */
 425 #define CFG_EBC_PB2AP           0x9400C800
 426 #define CFG_EBC_PB2CR           0xF0018000 /*  BAS=0x800,BS=1MB,BU=R/W,BW=8bit  */
 427
 428 #define CFG_EBC_CFG             0x7FC00000 /*  EBC0_CFG */
 429
 430 /*-----------------------------------------------------------------------
 431  * GPIO Setup
 432  *----------------------------------------------------------------------*/
 433 #define CFG_4xx_GPIO_TABLE { /*   Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 434 {                                                                                       \
 435 /* GPIO Core 0 */                                                                       \
 436 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0)                 */      \
 437 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1)                 */      \
 438 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2)                 */      \
 439 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3)                 */      \
 440 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20)    USB2_DATA(4)    */      \
 441 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21)    USB2_DATA(5)    */      \
 442 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22)    USB2_DATA(6)    */      \
 443 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23)    USB2_DATA(7)    */      \
 444 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1)   IRQ(7)          */      \
 445 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2)   IRQ(8)          */      \
 446 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3)  IRQ(9)          */      \
 447 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 IRQ(6)                         */      \
 448 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16)   USB2_DATA(0)    */      \
 449 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17)   USB2_DATA(1)    */      \
 450 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18)   USB2_DATA(2)    */      \
 451 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19)   USB2_DATA(3)    */      \
 452 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD      UART1_CTS       */      \
 453 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR      UART1_RTS       */      \
 454 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS                      */      \
 455 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS                      */      \
 456 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 UART0_DTR      UART1_TX        */      \
 457 {GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 UART0_RI       UART1_RX        */      \
 458 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ   DMA_ACK2        */      \
 459 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK   DMA_REQ2        */      \
 460 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ    DMA_EOT2        IRQ(4) */ \
 461 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK    DMA_ACK3        IRQ(3) */ \
 462 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5)    DMA_EOT0        TS(3) */ \
 463 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ    DMA_EOT3        IRQ(5) */ \
 464 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO28                                */      \
 465 {GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO29 DMA_EOT1       IRQ(2)          */      \
 466 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO30 DMA_REQ1       IRQ(1)          */      \
 467 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO31 DMA_ACK1       IRQ(0)          */      \
 468 }                                                                                               \
 469 }
 470
 471 /*
 472  * Internal Definitions
 473  *
 474  * Boot Flags
 475  */
 476 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 477 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 478
 479 #if defined(CONFIG_CMD_KGDB)
 480 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 481 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 482 #endif
 483
 484 /*-----------------------------------------------------------------------
 485  * Some Kilauea stuff..., mainly fpga registers
 486  */
 487 #define CFG_FPGA_REG_BASE               CFG_FPGA_BASE
 488 #define CFG_FPGA_FIFO_BASE              (in32(CFG_FPGA_BASE) | (1 << 11))
 489
 490 /* interrupt */
 491 #define CFG_FPGA_SLIC0_R_DPRAM_INT      0x80000000
 492 #define CFG_FPGA_SLIC0_W_DPRAM_INT      0x40000000
 493 #define CFG_FPGA_SLIC1_R_DPRAM_INT      0x20000000
 494 #define CFG_FPGA_SLIC1_W_DPRAM_INT      0x10000000
 495 #define CFG_FPGA_PHY0_INT               0x08000000
 496 #define CFG_FPGA_PHY1_INT               0x04000000
 497 #define CFG_FPGA_SLIC0_INT              0x02000000
 498 #define CFG_FPGA_SLIC1_INT              0x01000000
 499
 500 /* DPRAM setting */
 501 /* 00: 32B; 01: 64B; 10: 128B; 11: 256B  */
 502 #define CFG_FPGA_DPRAM_R_INT_LINE       0x00400000      /* 64 B */
 503 #define CFG_FPGA_DPRAM_W_INT_LINE       0x00100000      /* 64 B */
 504 #define CFG_FPGA_DPRAM_RW_TYPE          0x00080000
 505 #define CFG_FPGA_DPRAM_RST              0x00040000
 506 #define CFG_FPGA_UART0_FO               0x00020000
 507 #define CFG_FPGA_UART1_FO               0x00010000
 508
 509 /* loopback */
 510 #define CFG_FPGA_CHIPSIDE_LOOPBACK      0x00004000
 511 #define CFG_FPGA_LINESIDE_LOOPBACK      0x00008000
 512 #define CFG_FPGA_SLIC0_ENABLE           0x00002000
 513 #define CFG_FPGA_SLIC1_ENABLE           0x00001000
 514 #define CFG_FPGA_SLIC0_CS               0x00000800
 515 #define CFG_FPGA_SLIC1_CS               0x00000400
 516 #define CFG_FPGA_USER_LED0              0x00000200
 517 #define CFG_FPGA_USER_LED1              0x00000100
 518
 519 /* pass open firmware flat tree */
 520 #define CONFIG_OF_LIBFDT        1
 521 #define CONFIG_OF_BOARD_SETUP   1
 522
 523 #endif  /* __CONFIG_H */