include/configs/hymod.h

   1 /*
   2  * (C) Copyright 2000
   3  * Murray Jensen <Murray.Jensen@cmst.csiro.au>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * Config header file for Hymod board
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU       */
  37 #define CONFIG_HYMOD            1       /* ...on a Hymod board          */
  38 #define CONFIG_CPM2             1       /* Has a CPM2 */
  39
  40 #define CONFIG_MISC_INIT_F      1       /* Use misc_init_f()            */
  41
  42 #define CONFIG_BOARD_POSTCLK_INIT       /* have board_postclk_init() function */
  43
  44 /*
  45  * select serial console configuration
  46  *
  47  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  48  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  49  * for SCC).
  50  *
  51  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  52  * defined elsewhere (for example, on the cogent platform, there are serial
  53  * ports on the motherboard which are used for the serial console - see
  54  * cogent/cma101/serial.[ch]).
  55  */
  56 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
  57 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
  58 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
  59 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  60 #define CONFIG_CONS_USE_EXTC            /* SMC/SCC use ext clock not brg_clk */
  61 #define CONFIG_CONS_EXTC_RATE   3686400 /* SMC/SCC ext clk rate in Hz */
  62 #define CONFIG_CONS_EXTC_PINSEL 0       /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
  63
  64 /*
  65  * select ethernet configuration
  66  *
  67  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  68  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  69  * for FCC)
  70  *
  71  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  72  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
  73  */
  74 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
  75 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
  76 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
  77 #define CONFIG_ETHER_INDEX      1       /* which channel for ether      */
  78 #define CONFIG_ETHER_LOOPBACK_TEST      /* add ether external loopback test */
  79
  80 #ifdef CONFIG_ETHER_ON_FCC
  81
  82 #if (CONFIG_ETHER_INDEX == 1)
  83
  84 /*
  85  * - Rx-CLK is CLK10
  86  * - Tx-CLK is CLK11
  87  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  88  * - Enable Full Duplex in FSMR
  89  */
  90 # define CFG_CMXFCR_MASK        (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
  91 # define CFG_CMXFCR_VALUE       (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11)
  92 # define CFG_CPMFCR_RAMTYPE     0
  93 # define CFG_FCC_PSMR           (FCC_PSMR_FDE|FCC_PSMR_LPB)
  94
  95 # define MDIO_PORT              0               /* Port A */
  96 # define MDIO_DATA_PINMASK      0x00040000      /* Pin 13 */
  97 # define MDIO_CLCK_PINMASK      0x00080000      /* Pin 12 */
  98
  99 #elif (CONFIG_ETHER_INDEX == 2)
 100
 101 /*
 102  * - Rx-CLK is CLK13
 103  * - Tx-CLK is CLK14
 104  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 105  * - Enable Full Duplex in FSMR
 106  */
 107 # define CFG_CMXFCR_MASK        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 108 # define CFG_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 109 # define CFG_CPMFCR_RAMTYPE     0
 110 # define CFG_FCC_PSMR           (FCC_PSMR_FDE|FCC_PSMR_LPB)
 111
 112 # define MDIO_PORT              0               /* Port A */
 113 # define MDIO_DATA_PINMASK      0x00000040      /* Pin 25 */
 114 # define MDIO_CLCK_PINMASK      0x00000080      /* Pin 24 */
 115
 116 #elif (CONFIG_ETHER_INDEX == 3)
 117
 118 /*
 119  * - Rx-CLK is CLK15
 120  * - Tx-CLK is CLK16
 121  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 122  * - Enable Full Duplex in FSMR
 123  */
 124 # define CFG_CMXFCR_MASK        (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
 125 # define CFG_CMXFCR_VALUE       (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
 126 # define CFG_CPMFCR_RAMTYPE     0
 127 # define CFG_FCC_PSMR           (FCC_PSMR_FDE|FCC_PSMR_LPB)
 128
 129 # define MDIO_PORT              0               /* Port A */
 130 # define MDIO_DATA_PINMASK      0x00000100      /* Pin 23 */
 131 # define MDIO_CLCK_PINMASK      0x00000200      /* Pin 22 */
 132
 133 #endif  /* CONFIG_ETHER_INDEX */
 134
 135 #define CONFIG_MII                      /* MII PHY management   */
 136 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management  */
 137
 138 #define MDIO_ACTIVE     (iop->pdir |=  MDIO_DATA_PINMASK)
 139 #define MDIO_TRISTATE   (iop->pdir &= ~MDIO_DATA_PINMASK)
 140 #define MDIO_READ       ((iop->pdat &  MDIO_DATA_PINMASK) != 0)
 141
 142 #define MDIO(bit)       if(bit) iop->pdat |=  MDIO_DATA_PINMASK; \
 143                         else    iop->pdat &= ~MDIO_DATA_PINMASK
 144
 145 #define MDC(bit)        if(bit) iop->pdat |=  MDIO_CLCK_PINMASK; \
 146                         else    iop->pdat &= ~MDIO_CLCK_PINMASK
 147
 148 #define MIIDELAY        udelay(1)
 149
 150 #endif  /* CONFIG_ETHER_ON_FCC */
 151
 152
 153 /* other options */
 154 #define CONFIG_HARD_I2C         1       /* To enable I2C hardware support       */
 155 #define CONFIG_DTT_ADM1021      1       /* ADM1021 temp sensor support */
 156
 157 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 158 #ifdef DEBUG
 159 #define CONFIG_8260_CLKIN       33333333        /* in Hz */
 160 #else
 161 #define CONFIG_8260_CLKIN       66666666        /* in Hz */
 162 #endif
 163
 164 #if defined(CONFIG_CONS_USE_EXTC)
 165 #define CONFIG_BAUDRATE         115200
 166 #else
 167 #define CONFIG_BAUDRATE         9600
 168 #endif
 169
 170 /* default ip addresses - these will be overridden */
 171 #define CONFIG_IPADDR           192.168.1.1     /* hymod "boot" address */
 172 #define CONFIG_SERVERIP         192.168.1.254   /* hymod "server" address */
 173
 174 #define CONFIG_LAST_STAGE_INIT
 175
 176 /*
 177  * BOOTP options
 178  */
 179 #define CONFIG_BOOTP_BOOTFILESIZE
 180 #define CONFIG_BOOTP_BOOTPATH
 181 #define CONFIG_BOOTP_GATEWAY
 182 #define CONFIG_BOOTP_HOSTNAME
 183
 184
 185 /*
 186  * Command line configuration.
 187  */
 188 #include <config_cmd_default.h>
 189
 190 #define CONFIG_CMD_ASKENV
 191 #define CONFIG_CMD_BSP
 192 #define CONFIG_CMD_CACHE
 193 #define CONFIG_CMD_CDP
 194 #define CONFIG_CMD_DATE
 195 #define CONFIG_CMD_DHCP
 196 #define CONFIG_CMD_DIAG
 197 #define CONFIG_CMD_DTT
 198 #define CONFIG_CMD_EEPROM
 199 #define CONFIG_CMD_ELF
 200 #define CONFIG_CMD_FAT
 201 #define CONFIG_CMD_I2C
 202 #define CONFIG_CMD_IMMAP
 203 #define CONFIG_CMD_IRQ
 204 #define CONFIG_CMD_KGDB
 205 #define CONFIG_CMD_MII
 206 #define CONFIG_CMD_PING
 207 #define CONFIG_CMD_PORTIO
 208 #define CONFIG_CMD_REGINFO
 209 #define CONFIG_CMD_SAVES
 210 #define CONFIG_CMD_SDRAM
 211 #define CONFIG_CMD_SNTP
 212
 213 #undef CONFIG_CMD_FPGA
 214 #undef CONFIG_CMD_XIMG
 215
 216 #ifdef DEBUG
 217 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
 218 #else
 219 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 220 #define CONFIG_BOOT_RETRY_TIME 30       /* retry autoboot after 30 secs */
 221 #define CONFIG_BOOT_RETRY_MIN   1       /* can go down to 1 second timeout */
 222 /* Be selective on what keys can delay or stop the autoboot process
 223  *      To stop use: " "
 224  */
 225 #define CONFIG_AUTOBOOT_KEYED
 226 #define CONFIG_AUTOBOOT_PROMPT          "Autobooting in %d seconds, " \
 227                                         "press <SPACE> to stop\n"
 228 #define CONFIG_AUTOBOOT_STOP_STR        " "
 229 #undef CONFIG_AUTOBOOT_DELAY_STR
 230 #define DEBUG_BOOTKEYS          0
 231 #endif
 232
 233 #if defined(CONFIG_CMD_KGDB)
 234 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 235 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 236 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 237 #define CONFIG_KGDB_INDEX       2       /* which serial channel for kgdb */
 238 #define CONFIG_KGDB_USE_EXTC            /* SMC/SCC use ext clock not brg_clk */
 239 #define CONFIG_KGDB_EXTC_RATE   3686400 /* serial ext clk rate in Hz */
 240 #define CONFIG_KGDB_EXTC_PINSEL 0       /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
 241 # if defined(CONFIG_KGDB_USE_EXTC)
 242 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 243 # else
 244 #define CONFIG_KGDB_BAUDRATE    9600    /* speed to run kgdb serial port at */
 245 # endif
 246 #endif
 247
 248 #undef  CONFIG_WATCHDOG                 /* disable platform specific watchdog */
 249
 250 #define CONFIG_RTC_PCF8563              /* use Philips PCF8563 RTC      */
 251
 252 /*
 253  * Hymod specific configurable options
 254  */
 255 #undef  CFG_HYMOD_DBLEDS                        /* walk mezz board LEDs */
 256
 257 /*
 258  * Miscellaneous configurable options
 259  */
 260 #define CFG_LONGHELP                    /* undef to save memory         */
 261 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 262 #if defined(CONFIG_CMD_KGDB)
 263 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 264 #else
 265 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 266 #endif
 267 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 268 #define CFG_MAXARGS     16              /* max number of command args   */
 269 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 270
 271 #define CFG_MEMTEST_START       0x00400000      /* memtest works on     */
 272 #define CFG_MEMTEST_END         0x03c00000      /* 4 ... 60 MB in DRAM  */
 273
 274 #define CFG_CLKS_IN_HZ          1       /* everything, incl board info, in Hz */
 275
 276 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 277
 278 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 279
 280 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
 281
 282 #define CFG_I2C_SPEED           50000
 283 #define CFG_I2C_SLAVE           0x7e
 284
 285 /* these are for the ST M24C02 2kbit serial i2c eeprom */
 286 #define CFG_I2C_EEPROM_ADDR     0x50            /* base address */
 287 #define CFG_I2C_EEPROM_ADDR_LEN 1               /* bytes of address */
 288 /* mask of address bits that overflow into the "EEPROM chip address"    */
 289 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x07
 290
 291 #define CFG_EEPROM_PAGE_WRITE_ENABLE    1       /* write eeprom in pages */
 292 #define CFG_EEPROM_PAGE_WRITE_BITS      4       /* 16 byte write page size */
 293 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* and takes up to 10 msec */
 294
 295 #define CFG_I2C_MULTI_EEPROMS   1               /* hymod has two eeproms */
 296
 297 #define CFG_I2C_RTC_ADDR        0x51    /* philips PCF8563 RTC address */
 298
 299 /*
 300  * standard dtt sensor configuration - bottom bit will determine local or
 301  * remote sensor of the ADM1021, the rest determines index into
 302  * CFG_DTT_ADM1021 array below.
 303  *
 304  * On HYMOD board, the remote sensor should be connected to the MPC8260
 305  * temperature diode thingy, but an errata said this didn't work and
 306  * should be disabled - so it isn't connected.
 307  */
 308 #if 0
 309 #define CONFIG_DTT_SENSORS              { 0, 1 }
 310 #else
 311 #define CONFIG_DTT_SENSORS              { 0 }
 312 #endif
 313
 314 /*
 315  * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
 316  * there will be one entry in this array for each two (dummy) sensors in
 317  * CONFIG_DTT_SENSORS.
 318  *
 319  * For HYMOD board:
 320  * - only one ADM1021
 321  * - i2c addr 0x2a (both ADD0 and ADD1 are N/C)
 322  * - conversion rate 0x02 = 0.25 conversions/second
 323  * - ALERT ouput disabled
 324  * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
 325  * - remote temp sensor disabled (see comment for CONFIG_DTT_SENSORS above)
 326  */
 327 #define CFG_DTT_ADM1021         { { 0x2a, 0x02, 0, 1, 0, 85, 0, } }
 328
 329 /*
 330  * Low Level Configuration Settings
 331  * (address mappings, register initial values, etc.)
 332  * You should know what you are doing if you make changes here.
 333  */
 334
 335 /*-----------------------------------------------------------------------
 336  * Hard Reset Configuration Words
 337  *
 338  * if you change bits in the HRCW, you must also change the CFG_*
 339  * defines for the various registers affected by the HRCW e.g. changing
 340  * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
 341  */
 342 #ifdef DEBUG
 343 #define CFG_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
 344                          HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
 345                          HRCW_MODCK_H0010)
 346 #else
 347 #define CFG_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
 348                          HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
 349                          HRCW_MODCK_H0101)
 350 #endif
 351 /* no slaves so just duplicate the master hrcw */
 352 #define CFG_HRCW_SLAVE1 CFG_HRCW_MASTER
 353 #define CFG_HRCW_SLAVE2 CFG_HRCW_MASTER
 354 #define CFG_HRCW_SLAVE3 CFG_HRCW_MASTER
 355 #define CFG_HRCW_SLAVE4 CFG_HRCW_MASTER
 356 #define CFG_HRCW_SLAVE5 CFG_HRCW_MASTER
 357 #define CFG_HRCW_SLAVE6 CFG_HRCW_MASTER
 358 #define CFG_HRCW_SLAVE7 CFG_HRCW_MASTER
 359
 360 /*-----------------------------------------------------------------------
 361  * Internal Memory Mapped Register
 362  */
 363 #define CFG_IMMR                0xF0000000
 364
 365 /*-----------------------------------------------------------------------
 366  * Definitions for initial stack pointer and data area (in DPRAM)
 367  */
 368 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 369 #define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
 370 #define CFG_GBL_DATA_SIZE       128  /* size in bytes reserved for initial data */
 371 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 372 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 373
 374 /*-----------------------------------------------------------------------
 375  * Start addresses for the final memory configuration
 376  * (Set up by the startup code)
 377  * Please note that CFG_SDRAM_BASE _must_ start at 0
 378  */
 379 #define CFG_SDRAM_BASE          0x00000000
 380 #define CFG_FLASH_BASE          TEXT_BASE
 381 #define CFG_MONITOR_BASE        TEXT_BASE
 382 #define CFG_FPGA_BASE           0x80000000
 383 /*
 384  * unfortunately, CFG_MONITOR_LEN must include the
 385  * (very large i.e. 256kB) environment flash sector
 386  */
 387 #define CFG_MONITOR_LEN         (512 << 10)     /* Reserve 512 kB for Monitor*/
 388 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()*/
 389
 390 /*
 391  * For booting Linux, the board info and command line data
 392  * have to be in the first 8 MB of memory, since this is
 393  * the maximum mapped by the Linux kernel during initialization.
 394  */
 395 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Mem map for Linux*/
 396
 397 /*-----------------------------------------------------------------------
 398  * FLASH organization
 399  */
 400 #define CFG_MAX_FLASH_BANKS     2       /* max num of memory banks      */
 401 #define CFG_MAX_FLASH_SECT      67      /* max num of sects on one chip */
 402
 403 #define CFG_FLASH_ERASE_TOUT    120000  /* Flash Erase Timeout (in ms)  */
 404 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 405
 406 #define CFG_ENV_IS_IN_FLASH     1
 407 #define CFG_ENV_SIZE            0x40000 /* Total Size of Environment Sector */
 408 #define CFG_ENV_SECT_SIZE       0x40000 /* see README - env sect real size */
 409 #define CFG_ENV_ADDR    (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE)
 410 #define CFG_USE_PPCENV                  /* Environment embedded in sect .ppcenv */
 411
 412 /*-----------------------------------------------------------------------
 413  * Cache Configuration
 414  */
 415 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 416 #if defined(CONFIG_CMD_KGDB)
 417 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value*/
 418 #endif
 419
 420 /*-----------------------------------------------------------------------
 421  * HIDx - Hardware Implementation-dependent Registers                    2-11
 422  *-----------------------------------------------------------------------
 423  * HID0 also contains cache control - initially enable both caches and
 424  * invalidate contents, then the final state leaves only the instruction
 425  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 426  * but Soft reset does not.
 427  *
 428  * HID1 has only read-only information - nothing to set.
 429  */
 430 #define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 431                                 HID0_IFEM|HID0_ABE)
 432 #ifdef DEBUG
 433 #define CFG_HID0_FINAL  0
 434 #else
 435 #define CFG_HID0_FINAL  (HID0_ICE|HID0_IFEM|HID0_ABE)
 436 #endif
 437 #define CFG_HID2        0
 438
 439 /*-----------------------------------------------------------------------
 440  * RMR - Reset Mode Register                                     5-5
 441  *-----------------------------------------------------------------------
 442  * turn on Checkstop Reset Enable
 443  */
 444 #ifdef DEBUG
 445 #define CFG_RMR         0
 446 #else
 447 #define CFG_RMR         RMR_CSRE
 448 #endif
 449
 450 /*-----------------------------------------------------------------------
 451  * BCR - Bus Configuration                                       4-25
 452  *-----------------------------------------------------------------------
 453  */
 454 #define CFG_BCR         (BCR_ETM)
 455
 456 /*-----------------------------------------------------------------------
 457  * SIUMCR - SIU Module Configuration                             4-31
 458  *-----------------------------------------------------------------------
 459  */
 460 #define CFG_SIUMCR      (SIUMCR_DPPC10|SIUMCR_L2CPC01|\
 461                          SIUMCR_APPC10|SIUMCR_MMR11)
 462
 463 /*-----------------------------------------------------------------------
 464  * SYPCR - System Protection Control                             4-35
 465  * SYPCR can only be written once after reset!
 466  *-----------------------------------------------------------------------
 467  * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable
 468  */
 469 #if defined(CONFIG_WATCHDOG)
 470 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 471                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 472 #else
 473 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 474                          SYPCR_SWRI|SYPCR_SWP)
 475 #endif /* CONFIG_WATCHDOG */
 476
 477 /*-----------------------------------------------------------------------
 478  * TMCNTSC - Time Counter Status and Control                     4-40
 479  *-----------------------------------------------------------------------
 480  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 481  * and enable Time Counter
 482  */
 483 #define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 484
 485 /*-----------------------------------------------------------------------
 486  * PISCR - Periodic Interrupt Status and Control                 4-42
 487  *-----------------------------------------------------------------------
 488  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 489  * Periodic timer
 490  */
 491 #define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 492
 493 /*-----------------------------------------------------------------------
 494  * SCCR - System Clock Control                                   9-8
 495  *-----------------------------------------------------------------------
 496  * Ensure DFBRG is Divide by 16
 497  */
 498 #define CFG_SCCR        (SCCR_DFBRG01)
 499
 500 /*-----------------------------------------------------------------------
 501  * RCCR - RISC Controller Configuration                         13-7
 502  *-----------------------------------------------------------------------
 503  */
 504 #define CFG_RCCR        0
 505
 506 /*
 507  * Init Memory Controller:
 508  *
 509  * Bank Bus     Machine PortSz  Device
 510  * ---- ---     ------- ------  ------
 511  *  0   60x     GPCM    32 bit  FLASH
 512  *  1   60x     GPCM    32 bit  FLASH (same as 0 - unused for now)
 513  *  2   60x     SDRAM   64 bit  SDRAM
 514  *  3   Local   UPMC     8 bit  Main Xilinx configuration
 515  *  4   Local   GPCM    32 bit  Main Xilinx register mode
 516  *  5   Local   UPMB    32 bit  Main Xilinx port mode
 517  *  6   Local   UPMC     8 bit  Mezz Xilinx configuration
 518  */
 519
 520 /*
 521  * Bank 0 - FLASH
 522  *
 523  * Quotes from the HYMOD IO Board Reference manual:
 524  *
 525  * "The flash memory is two Intel StrataFlash chips, each configured for
 526  *  16 bit operation and connected to give a 32 bit wide port."
 527  *
 528  * "The chip select logic is configured to respond to both *CS0 and *CS1.
 529  *  Therefore the FLASH memory will be mapped to both bank 0 and bank 1.
 530  *  It is suggested that bank 0 be read-only and bank 1 be read/write. The
 531  *  FLASH will then appear as ROM during boot."
 532  *
 533  * Initially, we are only going to use bank 0 in read/write mode.
 534  */
 535
 536 /* 32 bit, read-write, GPCM on 60x bus */
 537 #define CFG_BR0_PRELIM  ((CFG_FLASH_BASE&BRx_BA_MSK)|\
 538                                 BRx_PS_32|BRx_MS_GPCM_P|BRx_V)
 539 /* up to 32 Mb */
 540 #define CFG_OR0_PRELIM  (MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
 541
 542 /*
 543  * Bank 2 - SDRAM
 544  *
 545  * Quotes from the HYMOD IO Board Reference manual:
 546  *
 547  * "The main memory is implemented using TC59SM716FTL-10 SDRAM and has a
 548  *  fixed size of 64 Mbytes. The Toshiba TC59SM716FTL-10 is a CMOS synchronous
 549  *  dynamic random access memory organised as 4 banks by 4096 rows by 512
 550  *  columns by 16 bits. Four chips provide a 64-bit port on the 60x bus."
 551  *
 552  * "The locations in SDRAM are accessed using multiplexed address pins to
 553  *  specify row and column. The pins also act to specify commands. The state
 554  *  of the inputs *RAS, *CAS and *WE defines the required action. The a10/AP
 555  *  pin may function as a row address or as the AUTO PRECHARGE control line,
 556  *  depending on the cycle type. The 60x bus SDRAM machine allows the MPC8260
 557  *  address lines to be configured to the required multiplexing scheme."
 558  */
 559
 560 #define CFG_SDRAM_SIZE  64
 561
 562 /* 64 bit, read-write, SDRAM on 60x bus */
 563 #define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE&BRx_BA_MSK)|\
 564                                 BRx_PS_64|BRx_MS_SDRAM_P|BRx_V)
 565 /* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */
 566 #define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM_SIZE)|\
 567                                 ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12)
 568
 569 /*
 570  * The 60x Bus SDRAM Mode Register (PDSMR) is set as follows:
 571  *
 572  * Page Based Interleaving, Refresh Enable, Address Multiplexing where A5
 573  * is output on A16 pin (A6 on A17, and so on), use address pins A14-A16
 574  * as bank select, A7 is output on SDA10 during an ACTIVATE command,
 575  * earliest timing for ACTIVATE command after REFRESH command is 6 clocks,
 576  * earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
 577  * is 2 clocks, earliest timing for READ/WRITE command after ACTIVATE
 578  * command is 2 clocks, earliest timing for PRECHARGE after last data
 579  * was read is 1 clock, earliest timing for PRECHARGE after last data
 580  * was written is 1 clock, CAS Latency is 2.
 581  */
 582
 583 #define CFG_PSDMR       (PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\
 584                                 PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\
 585                                 PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\
 586                                 PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\
 587                                 PSDMR_WRC_1C|PSDMR_CL_2)
 588
 589 /*
 590  * The 60x bus-assigned SDRAM Refresh Timer (PSRT) (10-31) and the Refresh
 591  * Timers Prescale (PTP) value in the Memory Refresh Timer Prescaler Register
 592  * (MPTPR) (10-32) must also be set up (it used to be called the Periodic Timer
 593  * Prescaler, hence the P instead of the R). The refresh timer period is given
 594  * by (note that there was a change in the 8260 UM Errata):
 595  *
 596  *      TimerPeriod = (PSRT + 1) / Fmptc
 597  *
 598  * where Fmptc is the BusClock divided by PTP. i.e.
 599  *
 600  *      TimerPeriod = (PSRT + 1) / (BusClock / PTP)
 601  *
 602  * or
 603  *
 604  *      TImerPeriod = (PTP * (PSRT + 1)) / BusClock
 605  *
 606  * The requirement for the Toshiba TC59SM716FTL-10 is that there must be
 607  * 4K refresh cycles every 64 ms. i.e. one refresh cycle every 64000/4096
 608  * = 15.625 usecs.
 609  *
 610  * So PTP * (PSRT + 1) <= 15.625 * BusClock. At 66.666MHz, PSRT=31 and PTP=32
 611  * appear to be reasonable.
 612  */
 613
 614 #ifdef DEBUG
 615 #define CFG_PSRT        39
 616 #define CFG_MPTPR       MPTPR_PTP_DIV8
 617 #else
 618 #define CFG_PSRT        31
 619 #define CFG_MPTPR       MPTPR_PTP_DIV32
 620 #endif
 621
 622 /*
 623  * Banks 3,4,5 and 6 - FPGA access
 624  *
 625  * Quotes from the HYMOD IO Board Reference manual:
 626  *
 627  * "The IO Board is fitted with a Xilinx XCV300E main FPGA. Provision is made
 628  *  for configuring an optional FPGA on the mezzanine interface.
 629  *
 630  *  Access to the FPGAs may be divided into several catagories:
 631  *
 632  *  1. Configuration
 633  *  2. Register mode access
 634  *  3. Port mode access
 635  *
 636  *  The main FPGA is supported for modes 1, 2 and 3. The mezzanine FPGA can be
 637  *  configured only (mode 1). Consequently there are four access types.
 638  *
 639  *  To improve interface performance and simplify software design, the four
 640  *  possible access types are separately mapped to different memory banks.
 641  *
 642  *  All are accessed using the local bus."
 643  *
 644  *       Device             Mode      Memory Bank Machine Port Size    Access
 645  *
 646  *        Main          Configuration      3       UPMC      8bit       R/W
 647  *        Main            Register         4       GPCM     32bit       R/W
 648  *        Main              Port           5       UPMB     32bit       R/W
 649  *      Mezzanine       Configuration      6       UPMC      8bit       W/O
 650  *
 651  * "Note that mezzanine mode 1 access is write-only."
 652  */
 653
 654 /* all the bank sizes must be a power of two, greater or equal to 32768 */
 655 #define FPGA_MAIN_CFG_BASE      (CFG_FPGA_BASE)
 656 #define FPGA_MAIN_CFG_SIZE      32768
 657 #define FPGA_MAIN_REG_BASE      (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE)
 658 #define FPGA_MAIN_REG_SIZE      32768
 659 #define FPGA_MAIN_PORT_BASE     (FPGA_MAIN_REG_BASE + FPGA_MAIN_REG_SIZE)
 660 #define FPGA_MAIN_PORT_SIZE     32768
 661 #define FPGA_MEZZ_CFG_BASE      (FPGA_MAIN_PORT_BASE + FPGA_MAIN_PORT_SIZE)
 662 #define FPGA_MEZZ_CFG_SIZE      32768
 663
 664 /* 8 bit, read-write, UPMC */
 665 #define CFG_BR3_PRELIM  (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
 666 /* up to 32Kbyte, burst inhibit */
 667 #define CFG_OR3_PRELIM  (P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI)
 668
 669 /* 32 bit, read-write, GPCM */
 670 #define CFG_BR4_PRELIM  (FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V)
 671 /* up to 32Kbyte */
 672 #define CFG_OR4_PRELIM  (P2SZ_TO_AM(FPGA_MAIN_REG_SIZE))
 673
 674 /* 32 bit, read-write, UPMB */
 675 #define CFG_BR5_PRELIM  (FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V)
 676 /* up to 32Kbyte */
 677 #define CFG_OR5_PRELIM  (P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI)
 678
 679 /* 8 bit, write-only, UPMC */
 680 #define CFG_BR6_PRELIM  (FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
 681 /* up to 32Kbyte, burst inhibit */
 682 #define CFG_OR6_PRELIM  (P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI)
 683
 684 /*-----------------------------------------------------------------------
 685  * MBMR - Machine B Mode                                        10-27
 686  *-----------------------------------------------------------------------
 687  */
 688 #define CFG_MBMR        (MxMR_BSEL|MxMR_OP_NORM)        /* XXX - needs more */
 689
 690 /*-----------------------------------------------------------------------
 691  * MCMR - Machine C Mode                                        10-27
 692  *-----------------------------------------------------------------------
 693  */
 694 #define CFG_MCMR        (MxMR_BSEL|MxMR_DSx_2_CYCL)     /* XXX - needs more */
 695
 696 /*
 697  * FPGA I/O Port/Bit information
 698  */
 699
 700 #define FPGA_MAIN_PROG_PORT     IOPIN_PORTA
 701 #define FPGA_MAIN_PROG_PIN      4       /* PA4 */
 702 #define FPGA_MAIN_INIT_PORT     IOPIN_PORTA
 703 #define FPGA_MAIN_INIT_PIN      5       /* PA5 */
 704 #define FPGA_MAIN_DONE_PORT     IOPIN_PORTA
 705 #define FPGA_MAIN_DONE_PIN      6       /* PA6 */
 706
 707 #define FPGA_MEZZ_PROG_PORT     IOPIN_PORTA
 708 #define FPGA_MEZZ_PROG_PIN      0       /* PA0 */
 709 #define FPGA_MEZZ_INIT_PORT     IOPIN_PORTA
 710 #define FPGA_MEZZ_INIT_PIN      1       /* PA1 */
 711 #define FPGA_MEZZ_DONE_PORT     IOPIN_PORTA
 712 #define FPGA_MEZZ_DONE_PIN      2       /* PA2 */
 713 #define FPGA_MEZZ_ENABLE_PORT   IOPIN_PORTA
 714 #define FPGA_MEZZ_ENABLE_PIN    3       /* PA3 */
 715
 716 /*
 717  * FPGA Interrupt configuration
 718  */
 719 #define FPGA_MAIN_IRQ           SIU_INT_IRQ2
 720
 721 /*
 722  * Internal Definitions
 723  *
 724  * Boot Flags
 725  */
 726 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH*/
 727 #define BOOTFLAG_WARM   0x02            /* Software reboot              */
 728
 729 /*
 730  * JFFS2 partitions
 731  *
 732  */
 733 /* No command line, one static partition, whole device */
 734 #undef CONFIG_JFFS2_CMDLINE
 735 #define CONFIG_JFFS2_DEV                "nor0"
 736 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 737 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 738
 739 /* mtdparts command line support */
 740 /*
 741 #define CONFIG_JFFS2_CMDLINE
 742 #define MTDIDS_DEFAULT          ""
 743 #define MTDPARTS_DEFAULT        ""
 744 */
 745
 746 #endif  /* __CONFIG_H */