include/configs/csb637.h

   1 /*
   2  * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
   3  * Anders Larsen <alarsen@rea.de>
   4  *
   5  * Configuation settings for the Cogent CSB637 board.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 /* ARM asynchronous clock */
  30 #define AT91C_MAIN_CLOCK        184320000       /* from 3.6864 MHz crystal (3686400 * 50) */
  31 #define AT91C_MASTER_CLOCK      46080000        /* (AT91C_MAIN_CLOCK/4) peripheral clock */
  32
  33 #define AT91_SLOW_CLOCK         32768   /* slow clock */
  34
  35 #define CONFIG_ARM920T          1       /* This is an ARM920T Core      */
  36 #define CONFIG_AT91RM9200       1       /* It's an Atmel AT91RM9200 SoC */
  37 #define CONFIG_CSB637           1       /* on a CSB637 board            */
  38 #undef  CONFIG_USE_IRQ                  /* we don't need IRQ/FIQ stuff  */
  39 #define USE_920T_MMU            1
  40
  41 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs      */
  42 #define CONFIG_SETUP_MEMORY_TAGS 1
  43 #define CONFIG_INITRD_TAG       1
  44
  45 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  46 #define CFG_USE_MAIN_OSCILLATOR         1
  47 /* flash */
  48 #define MC_PUIA_VAL     0x00000000
  49 #define MC_PUP_VAL      0x00000000
  50 #define MC_PUER_VAL     0x00000000
  51 #define MC_ASR_VAL      0x00000000
  52 #define MC_AASR_VAL     0x00000000
  53 #define EBI_CFGR_VAL    0x00000000
  54 #define SMC_CSR0_VAL    0x00003284 /* 16bit, 2 TDF, 4 WS */
  55
  56 /* clocks */
  57 #define PLLAR_VAL       0x2031BE01 /* 184.320000 MHz for PCK */
  58 #define PLLBR_VAL       0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */
  59 #define MCKR_VAL        0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */
  60
  61 /* sdram */
  62 #define PIOC_ASR_VAL    0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
  63 #define PIOC_BSR_VAL    0x00000000
  64 #define PIOC_PDR_VAL    0xFFFF0000
  65 #define EBI_CSA_VAL     0x00000002 /* CS1=SDRAM */
  66 #define SDRC_CR_VAL     0x21914159 /* set up the SDRAM */
  67 #define SDRAM           0x20000000 /* address of the SDRAM */
  68 #define SDRAM1          0x20000080 /* address of the SDRAM */
  69 #define SDRAM_VAL       0x00000000 /* value written to SDRAM */
  70 #define SDRC_MR_VAL     0x00000002 /* Precharge All */
  71 #define SDRC_MR_VAL1    0x00000004 /* refresh */
  72 #define SDRC_MR_VAL2    0x00000003 /* Load Mode Register */
  73 #define SDRC_MR_VAL3    0x00000000 /* Normal Mode */
  74 #define SDRC_TR_VAL     0x000002E0 /* Write refresh rate */
  75 #endif  /* CONFIG_SKIP_LOWLEVEL_INIT */
  76 /*
  77  * Size of malloc() pool
  78  */
  79 #define CFG_MALLOC_LEN  (CFG_ENV_SIZE + 128*1024)
  80 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
  81
  82 #define CONFIG_BAUDRATE 115200
  83
  84 #define CFG_AT91C_BRGR_DIVISOR  75      /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
  85
  86 /*
  87  * Hardware drivers
  88  */
  89
  90 /* define one of these to choose the DBGU, USART0  or USART1 as console */
  91 #define CONFIG_DBGU
  92 #undef CONFIG_USART0
  93 #undef CONFIG_USART1
  94
  95 #undef  CONFIG_HWFLOW                   /* don't include RTS/CTS flow control support   */
  96
  97 #undef  CONFIG_MODEM_SUPPORT            /* disable modem initialization stuff */
  98
  99 #define CONFIG_BOOTDELAY      3
 100 /* #define CONFIG_ENV_OVERWRITE 1 */
 101
 102
 103 /*
 104  * BOOTP options
 105  */
 106 #define CONFIG_BOOTP_BOOTFILESIZE
 107 #define CONFIG_BOOTP_BOOTPATH
 108 #define CONFIG_BOOTP_GATEWAY
 109 #define CONFIG_BOOTP_HOSTNAME
 110
 111
 112 /*
 113  * Command line configuration.
 114  */
 115 #include <config_cmd_default.h>
 116
 117 #define CONFIG_CMD_JFFS2
 118 #define CONFIG_CMD_DHCP
 119 #define CONFIG_CMD_PING
 120
 121 #undef CONFIG_CMD_BDI
 122 #undef CONFIG_CMD_IMI
 123 #undef CONFIG_CMD_AUTOSCRIPT
 124 #undef CONFIG_CMD_FPGA
 125 #undef CONFIG_CMD_MISC
 126 #undef CONFIG_CMD_LOADS
 127
 128
 129 #define CFG_MAX_NAND_DEVICE     1       /* Max number of NAND devices           */
 130 #define SECTORSIZE 512
 131
 132 #define ADDR_COLUMN 1
 133 #define ADDR_PAGE 2
 134 #define ADDR_COLUMN_PAGE 3
 135
 136 #define NAND_ChipID_UNKNOWN     0x00
 137 #define NAND_MAX_FLOORS 1
 138 #define NAND_MAX_CHIPS 1
 139
 140 #define AT91_SMART_MEDIA_ALE (1 << 22)  /* our ALE is AD22 */
 141 #define AT91_SMART_MEDIA_CLE (1 << 21)  /* our CLE is AD21 */
 142
 143 #define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
 144 #define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
 145
 146 #define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
 147
 148 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
 149 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
 150 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
 151 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
 152 /* the following are NOP's in our implementation */
 153 #define NAND_CTL_CLRALE(nandptr)
 154 #define NAND_CTL_SETALE(nandptr)
 155 #define NAND_CTL_CLRCLE(nandptr)
 156 #define NAND_CTL_SETCLE(nandptr)
 157
 158 #define CONFIG_NR_DRAM_BANKS 1
 159 #define PHYS_SDRAM                      0x20000000
 160 #define PHYS_SDRAM_SIZE                 0x4000000  /* 64 megs */
 161
 162 #define CFG_MEMTEST_START               PHYS_SDRAM
 163 #define CFG_MEMTEST_END                 CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 512*1024 - 4
 164 #define CFG_ALT_MEMTEST                 1
 165 #define CFG_MEMTEST_SCRATCH             CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 4
 166
 167 #define CONFIG_DRIVER_ETHER
 168 #define CONFIG_NET_RETRY_COUNT          20
 169 #undef CONFIG_AT91C_USE_RMII
 170
 171 #undef CONFIG_HAS_DATAFLASH
 172 #define CFG_SPI_WRITE_TOUT              (5*CFG_HZ)
 173 #define CFG_MAX_DATAFLASH_BANKS         0
 174 #define CFG_MAX_DATAFLASH_PAGES         16384
 175 #define CFG_DATAFLASH_LOGIC_ADDR_CS0    0xC0000000      /* Logical adress for CS0 */
 176 #define CFG_DATAFLASH_LOGIC_ADDR_CS3    0xD0000000      /* Logical adress for CS3 */
 177
 178 /*
 179  * FLASH Device configuration
 180  */
 181 #define PHYS_FLASH_1                    0x10000000
 182 #define PHYS_FLASH_SIZE                 0x800000  /* 8 megs main flash */
 183 #define CFG_FLASH_BASE                  PHYS_FLASH_1
 184 #define CFG_FLASH_CFI           1       /* flash is CFI conformant      */
 185 #define CFG_FLASH_CFI_DRIVER    1       /* use common cfi driver        */
 186 #define CFG_FLASH_EMPTY_INFO
 187 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster) */
 188 #define CFG_MAX_FLASH_BANKS     1       /* max # of memory banks        */
 189 #define CFG_FLASH_INCREMENT     0       /* there is only one bank       */
 190 #define CFG_FLASH_PROTECTION    1       /* hardware flash protection    */
 191 #define CFG_MAX_FLASH_SECT              64
 192
 193 #define CFG_JFFS2_FIRST_BANK    0
 194 #define CFG_JFFS2_FIRST_SECTOR  3
 195 #define CFG_JFFS2_NUM_BANKS     1
 196
 197 #undef  CFG_ENV_IS_IN_DATAFLASH
 198
 199 #ifdef CFG_ENV_IS_IN_DATAFLASH
 200 #define CFG_ENV_OFFSET                  0x20000
 201 #define CFG_ENV_ADDR                    (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
 202 #define CFG_ENV_SIZE                    0x2000  /* 0x8000 */
 203 #else
 204 #define CFG_ENV_IS_IN_FLASH             1
 205 #define CFG_ENV_ADDR                    (PHYS_FLASH_1 + 0x20000)  /* after u-boot.bin */
 206 #define CFG_ENV_SIZE                    0x20000 /* sectors are 128K here */
 207 #endif  /* CFG_ENV_IS_IN_DATAFLASH */
 208
 209
 210 #define CFG_LOAD_ADDR           0x21000000  /* default load address */
 211
 212 #define CFG_BAUDRATE_TABLE      { 115200, 57600, 38400, 19200, 9600 }
 213
 214 #define CFG_PROMPT              "U-Boot> "      /* Monitor Command Prompt */
 215 #define CFG_CBSIZE              256             /* Console I/O Buffer Size */
 216 #define CFG_MAXARGS             16              /* max number of command args */
 217 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 218
 219 #define CFG_HZ 1000
 220 #define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2       /* AT91C_TC0_CMR is implicitly set to */
 221                                                 /* AT91C_TC_TIMER_DIV1_CLOCK */
 222
 223 #define CONFIG_STACKSIZE        (32*1024)       /* regular stack */
 224
 225 #ifdef CONFIG_USE_IRQ
 226 #error CONFIG_USE_IRQ not supported
 227 #endif
 228
 229 #endif