include/configs/csb472.h

   1 /*
   2  * (C) Copyright 2004
   3  * Tolunay Orkun, Nextio Inc., torkun@nextio.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_405GP            1       /* This is a PPC405GP CPU       */
  37 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  38 #define CONFIG_CSB472           1       /* on a Cogent CSB472 board     */
  39 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f()    */
  40 #define CONFIG_LAST_STAGE_INIT  1       /* Call last_stage_init()       */
  41 #define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
  42
  43 /*
  44  * OS Bootstrap configuration
  45  *
  46  */
  47
  48 #if 0
  49 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled */
  50 #else
  51 #define CONFIG_BOOTDELAY        3       /* autoboot after X seconds     */
  52 #endif
  53
  54 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check keypress when bootdelay = 0 */
  55
  56 #if 1
  57 #undef  CONFIG_BOOTARGS
  58 #define CONFIG_BOOTCOMMAND \
  59         "setenv bootargs console=ttyS0,38400 debug " \
  60         "root=/dev/ram rw ramdisk_size=4096 " \
  61         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
  62         "bootm ff800000 ff900000"
  63 #endif
  64
  65 #if 0
  66 #undef  CONFIG_BOOTARGS
  67 #define CONFIG_BOOTCOMMAND \
  68         "bootp; " \
  69         "setenv bootargs console=ttyS0,38400 debug " \
  70         "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
  71         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
  72         "bootm"
  73 #endif
  74
  75 /*
  76  * BOOTP options
  77  */
  78 #define CONFIG_BOOTP_SUBNETMASK
  79 #define CONFIG_BOOTP_GATEWAY
  80 #define CONFIG_BOOTP_HOSTNAME
  81 #define CONFIG_BOOTP_BOOTPATH
  82 #define CONFIG_BOOTP_BOOTFILESIZE
  83 #define CONFIG_BOOTP_DNS2
  84
  85
  86 /*
  87  * Command line configuration.
  88  */
  89 #include <config_cmd_default.h>
  90
  91 #define CONFIG_CMD_ASKENV
  92 #define CONFIG_CMD_BEDBUG
  93 #define CONFIG_CMD_ELF
  94 #define CONFIG_CMD_IRQ
  95 #define CONFIG_CMD_I2C
  96 #define CONFIG_CMD_PCI
  97 #define CONFIG_CMD_DATE
  98 #define CONFIG_CMD_MII
  99 #define CONFIG_CMD_PING
 100 #define CONFIG_CMD_DHCP
 101
 102 /*
 103  * Serial download configuration
 104  *
 105  */
 106 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 107 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 108
 109 /*
 110  * KGDB Configuration
 111  *
 112  */
 113 #if defined(CONFIG_CMD_KGDB)
 114 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 115 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 116 #endif
 117
 118 /*
 119  * Miscellaneous configurable options
 120  *
 121  */
 122 #undef  CFG_HUSH_PARSER                 /* use "hush" command parser */
 123 #ifdef  CFG_HUSH_PARSER
 124 #define CFG_PROMPT_HUSH_PS2     "> "    /* hush shell secondary prompt */
 125 #endif
 126
 127 #define CFG_LONGHELP                    /* undef to save memory */
 128 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt */
 129 #if defined(CONFIG_CMD_KGDB)
 130 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size */
 131 #else
 132 #define CFG_CBSIZE              256     /* Console I/O Buffer Size */
 133 #endif
 134 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 135 #define CFG_MAXARGS             16      /* max number of command args */
 136 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 137
 138 #define CFG_MEMTEST_START       0x0400000 /* memtest works on */
 139 #define CFG_MEMTEST_END         0x0C00000 /* 4 ... 12 MB in DRAM */
 140
 141 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 142 #define CFG_CLKS_IN_HZ          1       /* everything, incl board info, in Hz */
 143 #define CFG_EXTBDINFO           1       /* To use extended board_info (bd_t) */
 144 #define CFG_LOAD_ADDR           0x100000 /* default load address */
 145
 146 /*
 147  * For booting Linux, the board info and command line data
 148  * have to be in the first 8 MB of memory, since this is
 149  * the maximum mapped by the Linux kernel during initialization.
 150  */
 151 #define CFG_BOOTMAPSZ           (8 << 20) /* Initial Memory map for Linux */
 152
 153 /*
 154  * watchdog configuration
 155  *
 156  */
 157 #undef  CONFIG_WATCHDOG                 /* watchdog disabled */
 158
 159 /*
 160  * UART configuration
 161  *
 162  */
 163 #undef CFG_EXT_SERIAL_CLOCK             /* use internal serial clock */
 164 #undef  CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59 */
 165 #define CFG_BASE_BAUD           691200
 166 #define CONFIG_BAUDRATE         38400   /* Default baud rate */
 167 #define CFG_BAUDRATE_TABLE      \
 168     { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
 169
 170 /*
 171  * I2C configuration
 172  *
 173  */
 174 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
 175 #define CFG_I2C_SPEED           100000  /* I2C speed                    */
 176 #define CFG_I2C_SLAVE           0x7F    /* I2C slave address            */
 177
 178 /*
 179  * MII PHY configuration
 180  *
 181  */
 182 #define CONFIG_MII              1       /* MII PHY management           */
 183 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
 184 #define CONFIG_PHY_CMD_DELAY    40      /* PHY COMMAND delay            */
 185                                         /* 32usec min. for LXT971A      */
 186 #define CONFIG_PHY_RESET_DELAY  300     /* PHY RESET recovery delay     */
 187
 188 /*
 189  * RTC configuration
 190  *
 191  * Note that DS1307 RTC is limited to 100Khz I2C bus.
 192  *
 193  */
 194 #define CONFIG_RTC_DS1307               /* Use Dallas 1307 RTC          */
 195
 196 /*
 197  * PCI stuff
 198  *
 199  */
 200 #define CONFIG_PCI                      /* include pci support          */
 201 #define PCI_HOST_ADAPTER        0       /* configure ar pci adapter     */
 202 #define PCI_HOST_FORCE          1       /* configure as pci host        */
 203 #define PCI_HOST_AUTO           2       /* detected via arbiter enable  */
 204
 205 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 206 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 207                                         /* resource configuration       */
 208 #undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 209 #define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 210
 211 #define CFG_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
 212 #define CFG_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
 213 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
 214 #define CFG_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
 215 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 216 #define CFG_PCI_PTM2LA  0x00000000      /* disabled                     */
 217 #define CFG_PCI_PTM2MS  0x00000000      /* disabled                     */
 218 #define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 219
 220 /*
 221  * IDE stuff
 222  *
 223  */
 224 #undef  CONFIG_IDE_PCMCIA               /* no pcmcia interface required */
 225 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 226 #undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
 227
 228 /*
 229  * Environment configuration
 230  *
 231  */
 232 #define CFG_ENV_IS_IN_FLASH     1       /* environment is in FLASH      */
 233 #undef CFG_ENV_IS_IN_NVRAM
 234 #undef CFG_ENV_IS_IN_EEPROM
 235
 236 /*
 237  * General Memory organization
 238  *
 239  * Start addresses for the final memory configuration
 240  * (Set up by the startup code)
 241  * Please note that CFG_SDRAM_BASE _must_ start at 0
 242  */
 243 #define CFG_SDRAM_BASE          0x00000000
 244 #define CFG_FLASH_BASE          0xFF800000
 245 #define CFG_FLASH_SIZE          0x00800000
 246 #define CFG_MONITOR_BASE        TEXT_BASE
 247 #define CFG_MONITOR_LEN         (256 * 1024) /* Reserve 256 KB for Monitor */
 248 #define CFG_MALLOC_LEN          (128 * 1024) /* Reserve 128 KB for malloc() */
 249
 250 #if CFG_MONITOR_BASE < CFG_FLASH_BASE
 251 #define CFG_RAMSTART
 252 #endif
 253
 254 #if defined(CFG_ENV_IS_IN_FLASH)
 255 #define CFG_ENV_IN_OWN_SECTOR   1          /* Give Environment own sector */
 256 #define CFG_ENV_ADDR            0xFFF00000 /* Address of Environment Sector */
 257 #define CFG_ENV_SIZE            0x00001000 /* Size of Environment */
 258 #define CFG_ENV_SECT_SIZE       0x00040000 /* Size of Environment Sector */
 259 #endif
 260
 261 /*
 262  * FLASH Device configuration
 263  *
 264  */
 265 #define CFG_FLASH_CFI           1       /* flash is CFI conformant      */
 266 #define CFG_FLASH_CFI_DRIVER    1       /* use common cfi driver        */
 267 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster) */
 268 #define CFG_MAX_FLASH_BANKS     1       /* max # of memory banks        */
 269 #define CFG_FLASH_INCREMENT     0       /* there is only one bank       */
 270 #define CFG_MAX_FLASH_SECT      64      /* max # of sectors on one chip */
 271 #define CFG_FLASH_PROTECTION    1       /* hardware flash protection    */
 272 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE }
 273
 274 /*
 275  * On Chip Memory location/size
 276  *
 277  */
 278 #define CFG_OCM_DATA_ADDR       0xF8000000
 279 #define CFG_OCM_DATA_SIZE       0x1000
 280
 281 /*
 282  * Global info and initial stack
 283  *
 284  */
 285 #define CFG_INIT_RAM_ADDR       CFG_OCM_DATA_ADDR /* inside of on-chip SRAM */
 286 #define CFG_INIT_RAM_END        CFG_OCM_DATA_SIZE /* End of used area in RAM */
 287 #define CFG_GBL_DATA_SIZE       128 /* byte size reserved for initial data */
 288 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 289 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 290
 291 /*
 292  * Miscellaneous board specific definitions
 293  *
 294  */
 295 #define CONFIG_I2CFAST          1       /* enable "i2cfast" env. setting     */
 296
 297 /*
 298  * Internal Definitions
 299  *
 300  * Boot Flags
 301  *
 302  */
 303 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
 304 #define BOOTFLAG_WARM           0x02    /* Software reboot */
 305
 306 #endif  /* __CONFIG_H */