include/configs/csb226.h

   1 /*
   2  * (C) Copyright 2000, 2001, 2002
   3  * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
   4  *
   5  * Configuration for the Cogent CSB226 board. For details see
   6  * http://www.cogcomp.com/csb_csb226.htm
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * include/configs/csb226.h - configuration options, board specific
  29  */
  30
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 #define DEBUG 1
  35
  36 /*
  37  * High Level Configuration Options
  38  * (easy to change)
  39  */
  40 #define CONFIG_PXA250           1       /* This is an PXA250 CPU            */
  41 #define CONFIG_CSB226           1       /* on a CSB226 board                */
  42
  43 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff      */
  44                                         /* for timer/console/ethernet       */
  45 /*
  46  * Hardware drivers
  47  */
  48
  49 /*
  50  * select serial console configuration
  51  */
  52 #define CONFIG_FFUART           1       /* we use FFUART on CSB226          */
  53
  54 /* allow to overwrite serial and ethaddr */
  55 #define CONFIG_ENV_OVERWRITE
  56
  57 #define CONFIG_BAUDRATE         19200
  58 #undef  CONFIG_MISC_INIT_R              /* not used yet                     */
  59
  60
  61 /*
  62  * BOOTP options
  63  */
  64 #define CONFIG_BOOTP_BOOTFILESIZE
  65 #define CONFIG_BOOTP_BOOTPATH
  66 #define CONFIG_BOOTP_GATEWAY
  67 #define CONFIG_BOOTP_HOSTNAME
  68
  69
  70 /*
  71  * Command line configuration.
  72  */
  73 #include <config_cmd_default.h>
  74
  75 #define CONFIG_CMD_BDI
  76 #define CONFIG_CMD_LOADB
  77 #define CONFIG_CMD_IMI
  78 #define CONFIG_CMD_FLASH
  79 #define CONFIG_CMD_MEMORY
  80 #define CONFIG_CMD_NET
  81 #define CONFIG_CMD_ENV
  82 #define CONFIG_CMD_RUN
  83 #define CONFIG_CMD_ASKENV
  84 #define CONFIG_CMD_ECHO
  85 #define CONFIG_CMD_DHCP
  86 #define CONFIG_CMD_CACHE
  87
  88
  89 #define CONFIG_BOOTDELAY        3
  90 #define CONFIG_BOOTARGS         "console=ttyS0,19200 ip=192.168.1.10,192.168.1.5,,255,255,255,0,csb root=/dev/nfs, ether=0,0x08000000,eth0"
  91 #define CONFIG_ETHADDR          FF:FF:FF:FF:FF:FF
  92 #define CONFIG_NETMASK          255.255.255.0
  93 #define CONFIG_IPADDR           192.168.1.56
  94 #define CONFIG_SERVERIP         192.168.1.5
  95 #define CONFIG_BOOTCOMMAND      "bootm 0x40000"
  96 #define CONFIG_SHOW_BOOT_PROGRESS
  97
  98 #define CONFIG_CMDLINE_TAG      1
  99
 100 #if defined(CONFIG_CMD_KGDB)
 101 #define CONFIG_KGDB_BAUDRATE    19200           /* speed to run kgdb serial port */
 102 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
 103 #endif
 104
 105 /*
 106  * Miscellaneous configurable options
 107  */
 108
 109 /*
 110  * Size of malloc() pool; this lives below the uppermost 128 KiB which are
 111  * used for the RAM copy of the uboot code
 112  *
 113  */
 114 #define CFG_MALLOC_LEN          (128*1024)
 115 #define CFG_GBL_DATA_SIZE       128             /* size in bytes reserved for initial data */
 116
 117 #define CFG_LONGHELP                            /* undef to save memory         */
 118 #define CFG_PROMPT              "uboot> "       /* Monitor Command Prompt       */
 119 #define CFG_CBSIZE              128             /* Console I/O Buffer Size      */
 120 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 121 #define CFG_MAXARGS             16              /* max number of command args   */
 122 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 123
 124 #define CFG_MEMTEST_START       0xa0400000      /* memtest works on     */
 125 #define CFG_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
 126
 127 #undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
 128
 129 #define CFG_LOAD_ADDR           0xa3000000      /* default load address */
 130                                                 /* RS: where is this documented? */
 131                                                 /* RS: is this where U-Boot is  */
 132                                                 /* RS: relocated to in RAM?      */
 133
 134 #define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
 135                                                 /* RS: the oscillator is actually 3680130?? */
 136 #define CFG_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
 137                                                 /* 0101000001 */
 138                                                 /*      ^^^^^ Memory Speed 99.53 MHz         */
 139                                                 /*    ^^      Run Mode Speed = 2x Mem Speed  */
 140                                                 /* ^^         Turbo Mode Sp. = 1x Run M. Sp. */
 141
 142 #define CFG_MONITOR_LEN         0x20000         /* 128 KiB */
 143
 144                                                 /* valid baudrates */
 145 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 146
 147 /*
 148  * Network chip
 149  */
 150 #define CONFIG_DRIVER_CS8900    1
 151 #define CS8900_BUS32            1
 152 #define CS8900_BASE             0x08000000
 153
 154 /*
 155  * Stack sizes
 156  *
 157  * The stack sizes are set up in start.S using the settings below
 158  */
 159 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 160 #ifdef  CONFIG_USE_IRQ
 161 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
 162 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 163 #endif
 164
 165 /*
 166  * Physical Memory Map
 167  */
 168 #define CONFIG_NR_DRAM_BANKS    1               /* we have 1 bank of DRAM   */
 169 #define PHYS_SDRAM_1            0xa0000000      /* SDRAM Bank #1            */
 170 #define PHYS_SDRAM_1_SIZE       0x02000000      /* 32 MB                    */
 171
 172 #define PHYS_FLASH_1            0x00000000      /* Flash Bank #1            */
 173 #define PHYS_FLASH_SIZE         0x02000000      /* 32 MB                    */
 174
 175 #define CFG_DRAM_BASE           0xa0000000      /* RAM starts here          */
 176 #define CFG_DRAM_SIZE           0x02000000
 177
 178 #define CFG_FLASH_BASE          PHYS_FLASH_1
 179
 180 # if 0
 181 /* FIXME: switch to _documented_ registers */
 182 /*
 183  * GPIO settings
 184  *
 185  * GP15 == nCS1      is 1
 186  * GP24 == SFRM      is 1
 187  * GP25 == TXD       is 1
 188  * GP33 == nCS5      is 1
 189  * GP39 == FFTXD     is 1
 190  * GP41 == RTS       is 1
 191  * GP47 == TXD       is 1
 192  * GP49 == nPWE      is 1
 193  * GP62 == LED_B     is 1
 194  * GP63 == TDM_OE    is 1
 195  * GP78 == nCS2      is 1
 196  * GP79 == nCS3      is 1
 197  * GP80 == nCS4      is 1
 198  */
 199 #define CFG_GPSR0_VAL       0x03008000
 200 #define CFG_GPSR1_VAL       0xC0028282
 201 #define CFG_GPSR2_VAL       0x0001C000
 202
 203 /* GP02 == DON_RST   is 0
 204  * GP23 == SCLK      is 0
 205  * GP45 == USB_ACT   is 0
 206  * GP60 == PLLEN     is 0
 207  * GP61 == LED_A     is 0
 208  * GP73 == SWUPD_LED is 0
 209  */
 210 #define CFG_GPCR0_VAL       0x00800004
 211 #define CFG_GPCR1_VAL       0x30002000
 212 #define CFG_GPCR2_VAL       0x00000100
 213
 214 /* GP00 == DON_READY is input
 215  * GP01 == DON_OK    is input
 216  * GP02 == DON_RST   is output
 217  * GP03 == RESET_IND is input
 218  * GP07 == RES11     is input
 219  * GP09 == RES12     is input
 220  * GP11 == SWUPDATE  is input
 221  * GP14 == nPOWEROK  is input
 222  * GP15 == nCS1      is output
 223  * GP17 == RES22     is input
 224  * GP18 == RDY       is input
 225  * GP23 == SCLK      is output
 226  * GP24 == SFRM      is output
 227  * GP25 == TXD       is output
 228  * GP26 == RXD       is input
 229  * GP32 == RES21     is input
 230  * GP33 == nCS5      is output
 231  * GP34 == FFRXD     is input
 232  * GP35 == CTS       is input
 233  * GP39 == FFTXD     is output
 234  * GP41 == RTS       is output
 235  * GP42 == USB_OK    is input
 236  * GP45 == USB_ACT   is output
 237  * GP46 == RXD       is input
 238  * GP47 == TXD       is output
 239  * GP49 == nPWE      is output
 240  * GP58 == nCPUBUSINT is input
 241  * GP59 == LANINT    is input
 242  * GP60 == PLLEN     is output
 243  * GP61 == LED_A     is output
 244  * GP62 == LED_B     is output
 245  * GP63 == TDM_OE    is output
 246  * GP64 == nDSPINT   is input
 247  * GP65 == STRAP0    is input
 248  * GP67 == STRAP1    is input
 249  * GP69 == STRAP2    is input
 250  * GP70 == STRAP3    is input
 251  * GP71 == STRAP4    is input
 252  * GP73 == SWUPD_LED is output
 253  * GP78 == nCS2      is output
 254  * GP79 == nCS3      is output
 255  * GP80 == nCS4      is output
 256  */
 257 #define CFG_GPDR0_VAL       0x03808004
 258 #define CFG_GPDR1_VAL       0xF002A282
 259 #define CFG_GPDR2_VAL       0x0001C200
 260
 261 /* GP15 == nCS1  is AF10
 262  * GP18 == RDY   is AF01
 263  * GP23 == SCLK  is AF10
 264  * GP24 == SFRM  is AF10
 265  * GP25 == TXD   is AF10
 266  * GP26 == RXD   is AF01
 267  * GP33 == nCS5  is AF10
 268  * GP34 == FFRXD is AF01
 269  * GP35 == CTS   is AF01
 270  * GP39 == FFTXD is AF10
 271  * GP41 == RTS   is AF10
 272  * GP46 == RXD   is AF10
 273  * GP47 == TXD   is AF01
 274  * GP49 == nPWE  is AF10
 275  * GP78 == nCS2  is AF10
 276  * GP79 == nCS3  is AF10
 277  * GP80 == nCS4  is AF10
 278  */
 279 #define CFG_GAFR0_L_VAL     0x80000000
 280 #define CFG_GAFR0_U_VAL     0x001A8010
 281 #define CFG_GAFR1_L_VAL     0x60088058
 282 #define CFG_GAFR1_U_VAL     0x00000008
 283 #define CFG_GAFR2_L_VAL     0xA0000000
 284 #define CFG_GAFR2_U_VAL     0x00000002
 285
 286
 287 /* FIXME: set GPIO_RER/FER */
 288
 289 /* RDH = 1
 290  * PH  = 1
 291  * VFS = 1
 292  * BFS = 1
 293  * SSS = 1
 294  */
 295 #define CFG_PSSR_VAL            0x37
 296
 297 /*
 298  * Memory settings
 299  *
 300  * This is the configuration for nCS0/1 -> flash banks
 301  * configuration for nCS1:
 302  * [31]    0    - Slower Device
 303  * [30:28] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
 304  * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
 305  * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
 306  * [19]    1    - 16 Bit bus width
 307  * [18:16] 000  - nonburst RAM or FLASH
 308  * configuration for nCS0:
 309  * [15]    0    - Slower Device
 310  * [14:12] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
 311  * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
 312  * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
 313  * [03]    1    - 16 Bit bus width
 314  * [02:00] 000  - nonburst RAM or FLASH
 315  */
 316 #define CFG_MSC0_VAL            0x25b825b8 /* flash banks                   */
 317
 318 /* This is the configuration for nCS2/3 -> TDM-Switch, DSP
 319  * configuration for nCS3: DSP
 320  * [31]    0    - Slower Device
 321  * [30:28] 001  - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
 322  * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
 323  * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
 324  * [19]    1    - 16 Bit bus width
 325  * [18:16] 100  - variable latency I/O
 326  * configuration for nCS2: TDM-Switch
 327  * [15]    0    - Slower Device
 328  * [14:12] 101  - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
 329  * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
 330  * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
 331  * [03]    1    - 16 Bit bus width
 332  * [02:00] 100  - variable latency I/O
 333  */
 334 #define CFG_MSC1_VAL            0x123C593C /* TDM switch, DSP               */
 335
 336 /* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
 337  *
 338  * configuration for nCS5: LAN Controller
 339  * [31]    0    - Slower Device
 340  * [30:28] 001  - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
 341  * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
 342  * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
 343  * [19]    1    - 16 Bit bus width
 344  * [18:16] 100  - variable latency I/O
 345  * configuration for nCS4: ExtBus
 346  * [15]    0    - Slower Device
 347  * [14:12] 110  - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
 348  * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
 349  * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
 350  * [03]    1    - 16 Bit bus width
 351  * [02:00] 100  - variable latency I/O
 352  */
 353 #define CFG_MSC2_VAL            0x123C6CDC /* extra bus, LAN controller     */
 354
 355 /* MDCNFG: SDRAM Configuration Register
 356  *
 357  * [31:29]   000 - reserved
 358  * [28]      0   - no SA1111 compatiblity mode
 359  * [27]      0   - latch return data with return clock
 360  * [26]      0   - alternate addressing for pair 2/3
 361  * [25:24]   00  - timings
 362  * [23]      0   - internal banks in lower partition 2/3 (not used)
 363  * [22:21]   00  - row address bits for partition 2/3 (not used)
 364  * [20:19]   00  - column address bits for partition 2/3 (not used)
 365  * [18]      0   - SDRAM partition 2/3 width is 32 bit
 366  * [17]      0   - SDRAM partition 3 disabled
 367  * [16]      0   - SDRAM partition 2 disabled
 368  * [15:13]   000 - reserved
 369  * [12]      1   - SA1111 compatiblity mode
 370  * [11]      1   - latch return data with return clock
 371  * [10]      0   - no alternate addressing for pair 0/1
 372  * [09:08]   01  - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
 373  * [7]       1   - 4 internal banks in lower partition pair
 374  * [06:05]   10  - 13 row address bits for partition 0/1
 375  * [04:03]   01  - 9 column address bits for partition 0/1
 376  * [02]      0   - SDRAM partition 0/1 width is 32 bit
 377  * [01]      0   - disable SDRAM partition 1
 378  * [00]      1   - enable  SDRAM partition 0
 379  */
 380 /* use the configuration above but disable partition 0 */
 381 #define CFG_MDCNFG_VAL          0x000019c8
 382
 383 /* MDREFR: SDRAM Refresh Control Register
 384  *
 385  * [32:26] 0     - reserved
 386  * [25]    0     - K2FREE: not free running
 387  * [24]    0     - K1FREE: not free running
 388  * [23]    1     - K0FREE: not free running
 389  * [22]    0     - SLFRSH: self refresh disabled
 390  * [21]    0     - reserved
 391  * [20]    0     - APD: no auto power down
 392  * [19]    0     - K2DB2: SDCLK2 is MemClk
 393  * [18]    0     - K2RUN: disable SDCLK2
 394  * [17]    0     - K1DB2: SDCLK1 is MemClk
 395  * [16]    1     - K1RUN: enable SDCLK1
 396  * [15]    1     - E1PIN: SDRAM clock enable
 397  * [14]    1     - K0DB2: SDCLK0 is MemClk
 398  * [13]    0     - K0RUN: disable SDCLK0
 399  * [12]    1     - E0PIN: disable SDCKE0
 400  * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
 401  */
 402 #define CFG_MDREFR_VAL          0x0081D018
 403
 404 /* MDMRS: Mode Register Set Configuration Register
 405  *
 406  * [31]      0       - reserved
 407  * [30:23]   00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
 408  * [22:20]   000     - MDCL2:  SDRAM2/3 Cas Latency.  (not used)
 409  * [19]      0       - MDADD2: SDRAM2/3 burst Type. Fixed to sequential.  (not used)
 410  * [18:16]   010     - MDBL2:  SDRAM2/3 burst Length. Fixed to 4.  (not used)
 411  * [15]      0       - reserved
 412  * [14:07]   00000000- MDMRS0: SDRAM0/1 MRS Value.
 413  * [06:04]   010     - MDCL0:  SDRAM0/1 Cas Latency.
 414  * [03]      0       - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
 415  * [02:00]   010     - MDBL0:  SDRAM0/1 burst Length. Fixed to 4.
 416  */
 417 #define CFG_MDMRS_VAL           0x00020022
 418
 419 /*
 420  * PCMCIA and CF Interfaces
 421  */
 422 #define CFG_MECR_VAL            0x00000000
 423 #define CFG_MCMEM0_VAL          0x00000000
 424 #define CFG_MCMEM1_VAL          0x00000000
 425 #define CFG_MCATT0_VAL          0x00000000
 426 #define CFG_MCATT1_VAL          0x00000000
 427 #define CFG_MCIO0_VAL           0x00000000
 428 #define CFG_MCIO1_VAL           0x00000000
 429 #endif
 430
 431 /*
 432  * GPIO settings
 433  */
 434 #define CFG_GPSR0_VAL           0xFFFFFFFF
 435 #define CFG_GPSR1_VAL           0xFFFFFFFF
 436 #define CFG_GPSR2_VAL           0xFFFFFFFF
 437 #define CFG_GPCR0_VAL           0x08022080
 438 #define CFG_GPCR1_VAL           0x00000000
 439 #define CFG_GPCR2_VAL           0x00000000
 440 #define CFG_GPDR0_VAL           0xCD82A878
 441 #define CFG_GPDR1_VAL           0xFCFFAB80
 442 #define CFG_GPDR2_VAL           0x0001FFFF
 443 #define CFG_GAFR0_L_VAL         0x80000000
 444 #define CFG_GAFR0_U_VAL         0xA5254010
 445 #define CFG_GAFR1_L_VAL         0x599A9550
 446 #define CFG_GAFR1_U_VAL         0xAAA5AAAA
 447 #define CFG_GAFR2_L_VAL         0xAAAAAAAA
 448 #define CFG_GAFR2_U_VAL         0x00000002
 449
 450 /* FIXME: set GPIO_RER/FER */
 451
 452 #define CFG_PSSR_VAL        0x20
 453
 454 /*
 455  * Memory settings
 456  */
 457
 458 #define CFG_MSC0_VAL            0x2ef15af0
 459 #define CFG_MSC1_VAL            0x00003ff4
 460 #define CFG_MSC2_VAL            0x7ff07ff0
 461 #define CFG_MDCNFG_VAL          0x09a909a9
 462 #define CFG_MDREFR_VAL          0x038ff030
 463 #define CFG_MDMRS_VAL           0x00220022
 464
 465 /*
 466  * PCMCIA and CF Interfaces
 467  */
 468 #define CFG_MECR_VAL        0x00000000
 469 #define CFG_MCMEM0_VAL      0x00000000
 470 #define CFG_MCMEM1_VAL      0x00000000
 471 #define CFG_MCATT0_VAL      0x00000000
 472 #define CFG_MCATT1_VAL      0x00000000
 473 #define CFG_MCIO0_VAL       0x00000000
 474 #define CFG_MCIO1_VAL       0x00000000
 475
 476 #define CSB226_USER_LED0        0x00000008
 477 #define CSB226_USER_LED1        0x00000010
 478 #define CSB226_USER_LED2        0x00000020
 479
 480
 481 /*
 482  * FLASH and environment organization
 483  */
 484 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks       */
 485 #define CFG_MAX_FLASH_SECT      128     /* max number of sect. on one chip  */
 486
 487 /* timeout values are in ticks */
 488 #define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ) /* Timeout for Flash Erase       */
 489 #define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ) /* Timeout for Flash Write       */
 490
 491 #define CFG_ENV_IS_IN_FLASH     1
 492 #define CFG_ENV_ADDR            (PHYS_FLASH_1 + 0x1C000)
 493                                         /* Addr of Environment Sector       */
 494 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector */
 495
 496 #endif  /* __CONFIG_H */