include/configs/alpr.h

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*-----------------------------------------------------------------------
  28  * High Level Configuration Options
  29  *----------------------------------------------------------------------*/
  30 #define CONFIG_ALPR             1           /* Board is ebony           */
  31 #define CONFIG_440GX            1           /* Specifc GX support       */
  32 #define CONFIG_440              1           /* ... PPC440 family        */
  33 #define CONFIG_4xx              1           /* ... PPC4xx family        */
  34 #define CONFIG_BOARD_EARLY_INIT_F 1         /* Call board_pre_init      */
  35 #define CONFIG_LAST_STAGE_INIT  1           /* call last_stage_init()   */
  36 #undef  CFG_DRAM_TEST                       /* Disable-takes long time! */
  37 #define CONFIG_SYS_CLK_FREQ     33333333    /* external freq to pll     */
  38 #define CONFIG_4xx_DCACHE               /* Enable i- and d-cache        */
  39
  40 /*-----------------------------------------------------------------------
  41  * Base addresses -- Note these are effective addresses where the
  42  * actual resources get mapped (not physical addresses)
  43  *----------------------------------------------------------------------*/
  44 #define CFG_SDRAM_BASE          0x00000000      /* _must_ be 0                  */
  45 #define CFG_FLASH_BASE          0xffe00000      /* start of FLASH               */
  46 #define CFG_MONITOR_BASE        0xfffc0000      /* start of monitor             */
  47 #define CFG_PCI_MEMBASE         0x80000000      /* mapped pci memory            */
  48 #define CFG_PCI_MEMSIZE         0x40000000      /* size of mapped pci memory    */
  49 #define CFG_PERIPHERAL_BASE     0xe0000000      /* internal peripherals         */
  50 #define CFG_ISRAM_BASE          0xc0000000      /* internal SRAM                */
  51 #define CFG_PCI_BASE            0xd0000000      /* internal PCI regs            */
  52 #define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
  53 #define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
  54 #define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000
  55
  56
  57 #define CFG_FPGA_BASE       (CFG_PERIPHERAL_BASE + 0x08300000)
  58 #define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
  59
  60 /*-----------------------------------------------------------------------
  61  * Initial RAM & stack pointer (placed in internal SRAM)
  62  *----------------------------------------------------------------------*/
  63 #define CFG_TEMP_STACK_OCM  1
  64 #define CFG_OCM_DATA_ADDR   CFG_ISRAM_BASE
  65 #define CFG_INIT_RAM_ADDR   CFG_ISRAM_BASE  /* Initial RAM address      */
  66 #define CFG_INIT_RAM_END    0x2000          /* End of used area in RAM  */
  67 #define CFG_GBL_DATA_SIZE   128             /* num bytes initial data   */
  68
  69 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  70 #define CFG_POST_WORD_ADDR      (CFG_GBL_DATA_OFFSET - 0x4)
  71 #define CFG_INIT_SP_OFFSET      CFG_POST_WORD_ADDR
  72
  73 #define CFG_MONITOR_LEN     (256 * 1024)    /* Reserve 256 kB for Mon   */
  74 #define CFG_MALLOC_LEN      (128 * 1024)    /* Reserve 128 kB for malloc*/
  75
  76 /*-----------------------------------------------------------------------
  77  * Serial Port
  78  *----------------------------------------------------------------------*/
  79 #undef  CFG_EXT_SERIAL_CLOCK
  80 #define CONFIG_BAUDRATE         115200
  81 #define CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
  82
  83 #define CFG_BAUDRATE_TABLE  \
  84     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  85
  86 /*-----------------------------------------------------------------------
  87  * FLASH related
  88  *----------------------------------------------------------------------*/
  89 #define CFG_FLASH_CFI           1       /* The flash is CFI compatible          */
  90 #define CFG_FLASH_CFI_DRIVER    1       /* Use common CFI driver                */
  91 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
  92 #define CFG_MAX_FLASH_SECT      512     /* max number of sectors on one chip    */
  93 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
  94 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
  95 #define CFG_FLASH_QUIET_TEST    1       /* don't warn upon unknown flash        */
  96
  97 #define CFG_ENV_IS_IN_FLASH     1       /* use FLASH for environment vars       */
  98
  99 #define CFG_ENV_SECT_SIZE       0x10000 /* size of one complete sector          */
 100 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
 101 #define CFG_ENV_SIZE            0x2000  /* Total Size of Environment Sector     */
 102
 103 /* Address and size of Redundant Environment Sector     */
 104 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
 105 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 106
 107 /*-----------------------------------------------------------------------
 108  * DDR SDRAM
 109  *----------------------------------------------------------------------*/
 110 #undef CONFIG_SPD_EEPROM                /* Don't use SPD EEPROM for setup       */
 111 #define CONFIG_SDRAM_BANK0      1       /* init onboard DDR SDRAM bank 0        */
 112 #undef CONFIG_SDRAM_ECC                 /* enable ECC support                   */
 113 #define CFG_SDRAM_TABLE { \
 114                 {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
 115                 {(64 << 20),  12, 0x00082001}} /* 64MB mode 2, 12x9(4)  */
 116
 117 /*-----------------------------------------------------------------------
 118  * I2C
 119  *----------------------------------------------------------------------*/
 120 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
 121 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 122 #define CFG_I2C_SPEED           100000  /* I2C speed and slave address  */
 123 #define CFG_I2C_SLAVE           0x7F
 124 #define CFG_I2C_NOPROBES        {0x69}  /* Don't probe these addrs      */
 125
 126 /*-----------------------------------------------------------------------
 127  * I2C EEPROM (PCF8594C)
 128  *----------------------------------------------------------------------*/
 129 #define CFG_I2C_EEPROM_ADDR     0x54    /* EEPROM PCF8594C              */
 130 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address             */
 131 /* mask of address bits that overflow into the "EEPROM chip address"    */
 132 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x07
 133 #define CFG_EEPROM_PAGE_WRITE_BITS 3    /* The Philips PCF8594C has     */
 134                                         /* 8 byte page write mode using */
 135                                         /* last 3 bits of the address   */
 136 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  40   /* and takes up to 40 msec */
 137 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 138
 139 #define CONFIG_PREBOOT  "echo;" \
 140         "echo Type \"run kernelx\" to boot the system;"                 \
 141         "echo"
 142
 143 #undef  CONFIG_BOOTARGS
 144
 145 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 146         "netdev=eth3\0"                                                 \
 147         "hostname=alpr\0"                                               \
 148         "fdt_file=alpr/alpr.dtb\0"                                      \
 149         "fdt_addr=400000\0"                                             \
 150         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 151                 "nfsroot=${serverip}:${rootpath} ${init}\0"             \
 152         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 153         "addip=setenv bootargs ${bootargs} "                            \
 154                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 155                 ":${hostname}:${netdev}:off panic=1\0"                  \
 156         "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \
 157                 "mem=193M\0"                                            \
 158         "flash_nfs=run nfsargs addip addtty;"                           \
 159                 "bootm ${kernel_addr}\0"                                \
 160         "flash_self=run ramargs addip addtty;"                          \
 161                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 162         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 163                 "bootm\0"                                               \
 164         "net_nfs_fdt=tftp 200000 ${bootfile};"                          \
 165                 "tftp ${fdt_addr} ${fdt_file};"                         \
 166                 "run nfsargs addip addtty;"                             \
 167                 "bootm 200000 - ${fdt_addr}\0"                          \
 168         "rootpath=/opt/projects/alpr/nfs_root\0"                        \
 169         "bootfile=/alpr/uImage\0"                                       \
 170         "kernel_addr=fff00000\0"                                        \
 171         "ramdisk_addr=fff10000\0"                                       \
 172         "load=tftp 100000 /alpr/u-boot/u-boot.bin\0"                    \
 173         "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"   \
 174                 "cp.b 100000 fffc0000 40000;"                           \
 175                 "setenv filesize;saveenv\0"                             \
 176         "upd=run load update\0"                                         \
 177         "ethprime=ppc_4xx_eth3\0"                                       \
 178         "ethact=ppc_4xx_eth3\0"                                         \
 179         "autoload=no\0"                                                 \
 180         "ipconfig=dhcp;setenv serverip 11.0.0.152\0"                    \
 181         "load_fpga=fpga load 0 ffe00000 10dd9a\0"                       \
 182         "mtdargs=setenv bootargs root=/dev/mtdblock6 rw "               \
 183                 "rootfstype=jffs2 init=/sbin/init\0"                    \
 184         "kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\
 185                 ";bootm 200000\0"                                       \
 186         "kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip " \
 187                 "addtty;bootm 200000\0"                                 \
 188         "kernel1=setenv actkernel 'kernel1';run load_fpga "             \
 189                 "kernel1_mtd\0"                                         \
 190         "kernel2=setenv actkernel 'kernel2';run load_fpga "             \
 191                 "kernel2_mtd\0"                                         \
 192         ""
 193
 194 #define CONFIG_BOOTCOMMAND      "run kernel2"
 195
 196 #define CONFIG_BOOTDELAY        2       /* autoboot after 5 seconds     */
 197
 198 #define CONFIG_BAUDRATE         115200
 199
 200 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 201 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 202
 203 #define CONFIG_MII              1       /* MII PHY management           */
 204 #define CONFIG_NET_MULTI        1
 205 #define CONFIG_PHY_ADDR         0x02    /* dummy setting, no EMAC0 used */
 206 #define CONFIG_PHY1_ADDR        0x03    /* dummy setting, no EMAC1 used */
 207 #define CONFIG_PHY2_ADDR        0x01    /* PHY address for EMAC2        */
 208 #define CONFIG_PHY3_ADDR        0x02    /* PHY address for EMAC3        */
 209 #define CONFIG_HAS_ETH0
 210 #define CONFIG_HAS_ETH1
 211 #define CONFIG_HAS_ETH2
 212 #define CONFIG_HAS_ETH3
 213 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 214 #define CONFIG_M88E1111_PHY     1       /* needed for PHY specific setup*/
 215 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 216 #define CFG_RX_ETH_BUFFER       32      /* Number of ethernet rx buffers & descriptors */
 217
 218 #define CONFIG_NETCONSOLE               /* include NetConsole support   */
 219
 220
 221 /*
 222  * BOOTP options
 223  */
 224 #define CONFIG_BOOTP_BOOTFILESIZE
 225 #define CONFIG_BOOTP_BOOTPATH
 226 #define CONFIG_BOOTP_GATEWAY
 227 #define CONFIG_BOOTP_HOSTNAME
 228
 229
 230 /*
 231  * Command line configuration.
 232  */
 233 #include <config_cmd_default.h>
 234
 235 #define CONFIG_CMD_ASKENV
 236 #define CONFIG_CMD_DHCP
 237 #define CONFIG_CMD_DIAG
 238 #define CONFIG_CMD_EEPROM
 239 #define CONFIG_CMD_ELF
 240 #define CONFIG_CMD_FPGA
 241 #define CONFIG_CMD_I2C
 242 #define CONFIG_CMD_IRQ
 243 #define CONFIG_CMD_MII
 244 #define CONFIG_CMD_NAND
 245 #define CONFIG_CMD_NET
 246 #define CONFIG_CMD_NFS
 247 #define CONFIG_CMD_PCI
 248 #define CONFIG_CMD_PING
 249 #define CONFIG_CMD_REGINFO
 250
 251
 252 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 253
 254 /*
 255  * Miscellaneous configurable options
 256  */
 257 #define CFG_LONGHELP                    /* undef to save memory         */
 258 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 259 #if defined(CONFIG_CMD_KGDB)
 260 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 261 #else
 262 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 263 #endif
 264 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 265 #define CFG_MAXARGS     16              /* max number of command args   */
 266 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 267
 268 #define CFG_ALT_MEMTEST         1       /* Enable more extensive memtest*/
 269 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 270 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 271
 272 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 273 #define CFG_EXTBDINFO           1       /* To use extended board_into (bd_t) */
 274
 275 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 276
 277 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 278 #define CONFIG_LOOPW            1       /* enable loopw command         */
 279 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 280 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 281 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 282
 283 #define CFG_4xx_RESET_TYPE      0x2     /* use chip reset on this board */
 284
 285 /*-----------------------------------------------------------------------
 286  * PCI stuff
 287  *-----------------------------------------------------------------------
 288  */
 289 /* General PCI */
 290 #define CONFIG_PCI                      /* include pci support          */
 291 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 292 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 293 #define CFG_PCI_TARGBASE    0x80000000  /* PCIaddr mapped to CFG_PCI_MEMBASE */
 294 #define CONFIG_PCI_BOOTDELAY    1       /* enable pci bootdelay variable*/
 295
 296 /* Board-specific PCI */
 297 #define CFG_PCI_TARGET_INIT             /* let board init pci target    */
 298 #define CFG_PCI_MASTER_INIT
 299
 300 #define CFG_PCI_SUBSYS_VENDORID 0x10e8  /* AMCC */
 301 #define CFG_PCI_SUBSYS_DEVICEID 0xcafe  /* Whatever */
 302
 303 /*-----------------------------------------------------------------------
 304  * FPGA stuff
 305  *-----------------------------------------------------------------------*/
 306 #define CONFIG_FPGA
 307 #define CONFIG_FPGA_ALTERA
 308 #define CONFIG_FPGA_CYCLON2
 309 #define CFG_FPGA_CHECK_CTRLC
 310 #define CFG_FPGA_PROG_FEEDBACK
 311 #define CONFIG_FPGA_COUNT       1               /* Ich habe 2 ... aber in
 312                                         Reihe geschaltet -> sollte gehen,
 313                                         aufpassen mit Datasize ist jetzt
 314                                         halt doppelt so gross ... Seite 306
 315                                         ist das mit den multiple Device in PS
 316                                         Mode erklaert ...*/
 317
 318 /* FPGA program pin configuration */
 319 #define CFG_GPIO_CLK            18      /* FPGA clk pin (cpu output)            */
 320 #define CFG_GPIO_DATA           19      /* FPGA data pin (cpu output)           */
 321 #define CFG_GPIO_STATUS         20      /* FPGA status pin (cpu input)          */
 322 #define CFG_GPIO_CONFIG         21      /* FPGA CONFIG pin (cpu output)         */
 323 #define CFG_GPIO_CON_DON        22      /* FPGA CONFIG_DONE pin (cpu input)     */
 324
 325 #define CFG_GPIO_SEL_DPR        14      /* cpu output */
 326 #define CFG_GPIO_SEL_AVR        15      /* cpu output */
 327 #define CFG_GPIO_PROG_EN        23      /* cpu output */
 328
 329 /*-----------------------------------------------------------------------
 330  * Definitions for GPIO setup
 331  *-----------------------------------------------------------------------*/
 332 #define CFG_GPIO_SHUTDOWN       (0x80000000 >> 6)
 333 #define CFG_GPIO_SSD_EMPTY      (0x80000000 >> 9)
 334 #define CFG_GPIO_EREADY         (0x80000000 >> 26)
 335 #define CFG_GPIO_REV0           (0x80000000 >> 14)
 336 #define CFG_GPIO_REV1           (0x80000000 >> 15)
 337
 338 /*-----------------------------------------------------------------------
 339  * NAND-FLASH stuff
 340  *-----------------------------------------------------------------------*/
 341 #define CFG_MAX_NAND_DEVICE     4
 342 #define NAND_MAX_CHIPS          CFG_MAX_NAND_DEVICE
 343 #define CFG_NAND_BASE           0xF0000000      /* NAND FLASH Base Address      */
 344 #define CFG_NAND_BASE_LIST      { CFG_NAND_BASE + 0, CFG_NAND_BASE + 2, \
 345                                   CFG_NAND_BASE + 4, CFG_NAND_BASE + 6 }
 346 #define CFG_NAND_QUIET_TEST     1       /* don't warn upon unknown NAND flash   */
 347
 348 /*-----------------------------------------------------------------------
 349  * External Bus Controller (EBC) Setup
 350  *----------------------------------------------------------------------*/
 351 #define CFG_FLASH               CFG_FLASH_BASE
 352
 353 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 354 #define CFG_EBC_PB0AP           0x92015480
 355 #define CFG_EBC_PB0CR           (CFG_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */
 356
 357 /* Memory Bank 1 (NAND-FLASH) initialization                                    */
 358 #define CFG_EBC_PB1AP           0x01840380      /* TWT=3                        */
 359 #define CFG_EBC_PB1CR           (CFG_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
 360
 361 /*
 362  * For booting Linux, the board info and command line data
 363  * have to be in the first 8 MB of memory, since this is
 364  * the maximum mapped by the Linux kernel during initialization.
 365  */
 366 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 367
 368 /*
 369  * Internal Definitions
 370  *
 371  * Boot Flags
 372  */
 373 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 374 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 375
 376 #if defined(CONFIG_CMD_KGDB)
 377 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 378 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 379 #endif
 380
 381 /* pass open firmware flat tree */
 382 #define CONFIG_OF_LIBFDT        1
 383 #define CONFIG_OF_BOARD_SETUP   1
 384
 385 #endif  /* __CONFIG_H */