include/configs/ads5121.h

   1 /*
   2  * (C) Copyright 2007 DENX Software Engineering
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * ADS5121 board configuration file
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*
  31  * Memory map for the ADS5121 board:
  32  *
  33  * 0x0000_0000 - 0x0FFF_FFFF    DDR RAM (256 MB)
  34  * 0x3000_0000 - 0x3001_FFFF    SRAM (128 KB)
  35  * 0x8000_0000 - 0x803F_FFFF    IMMR (4 MB)
  36  * 0x8200_0000 - 0x8200_001F    CPLD (32 B)
  37  * 0x8400_0000 - 0x82FF_FFFF    PCI I/O space (16 MB)
  38  * 0xA000_0000 - 0xAFFF_FFFF    PCI memory space (256 MB)
  39  * 0xB000_0000 - 0xBFFF_FFFF    PCI memory mapped I/O space (256 MB)
  40  * 0xFC00_0000 - 0xFFFF_FFFF    NOR Boot FLASH (64 MB)
  41  */
  42
  43 /*
  44  * High Level Configuration Options
  45  */
  46 #define CONFIG_E300             1       /* E300 Family */
  47 #define CONFIG_MPC512X          1       /* MPC512X family */
  48
  49 /* CONFIG_PCI is defined at config time */
  50
  51 #define CFG_MPC512X_CLKIN       66000000        /* in Hz */
  52
  53 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_early_init_f() */
  54
  55 #define CFG_IMMR                0x80000000
  56
  57 #define CFG_MEMTEST_START       0x00200000      /* memtest region */
  58 #define CFG_MEMTEST_END         0x00400000
  59
  60 /*
  61  * DDR Setup - manually set all parameters as there's no SPD etc.
  62  */
  63 #define CFG_DDR_SIZE            256             /* MB */
  64 #define CFG_DDR_BASE            0x00000000      /* DDR is system memory*/
  65 #define CFG_SDRAM_BASE          CFG_DDR_BASE
  66
  67 /* DDR Controller Configuration
  68  *
  69  * SYS_CFG:
  70  *      [31:31] MDDRC Soft Reset:       Diabled
  71  *      [30:30] DRAM CKE pin:           Enabled
  72  *      [29:29] DRAM CLK:               Enabled
  73  *      [28:28] Command Mode:           Enabled (For initialization only)
  74  *      [27:25] DRAM Row Select:        dram_row[15:0] = magenta_address[25:10]
  75  *      [24:21] DRAM Bank Select:       dram_bank[1:0] = magenta_address[11:10]
  76  *      [20:19] Read Test:              DON'T USE
  77  *      [18:18] Self Refresh:           Enabled
  78  *      [17:17] 16bit Mode:             Disabled
  79  *      [16:13] Ready Delay:            2
  80  *      [12:12] Half DQS Delay:         Disabled
  81  *      [11:11] Quarter DQS Delay:      Disabled
  82  *      [10:08] Write Delay:            2
  83  *      [07:07] Early ODT:              Disabled
  84  *      [06:06] On DIE Termination:     Disabled
  85  *      [05:05] FIFO Overflow Clear:    DON'T USE here
  86  *      [04:04] FIFO Underflow Clear:   DON'T USE here
  87  *      [03:03] FIFO Overflow Pending:  DON'T USE here
  88  *      [02:02] FIFO Underlfow Pending: DON'T USE here
  89  *      [01:01] FIFO Overlfow Enabled:  Enabled
  90  *      [00:00] FIFO Underflow Enabled: Enabled
  91  * TIME_CFG0
  92  *      [31:16] DRAM Refresh Time:      0 CSB clocks
  93  *      [15:8]  DRAM Command Time:      0 CSB clocks
  94  *      [07:00] DRAM Precharge Time:    0 CSB clocks
  95  * TIME_CFG1
  96  *      [31:26] DRAM tRFC:
  97  *      [25:21] DRAM tWR1:
  98  *      [20:17] DRAM tWRT1:
  99  *      [16:11] DRAM tDRR:
 100  *      [10:05] DRAM tRC:
 101  *      [04:00] DRAM tRAS:
 102  * TIME_CFG2
 103  *      [31:28] DRAM tRCD:
 104  *      [27:23] DRAM tFAW:
 105  *      [22:19] DRAM tRTW1:
 106  *      [18:15] DRAM tCCD:
 107  *      [14:10] DRAM tRTP:
 108  *      [09:05] DRAM tRP:
 109  *      [04:00] DRAM tRPA
 110  */
 111
 112 #define CFG_MDDRC_SYS_CFG       0xF8604A00
 113 #define CFG_MDDRC_SYS_CFG_RUN   0xE8604A00
 114 #define CFG_MDDRC_SYS_CFG_EN    0xF0000000
 115 #define CFG_MDDRC_TIME_CFG0     0x00003D2E
 116 #define CFG_MDDRC_TIME_CFG0_RUN 0x06183D2E
 117 #define CFG_MDDRC_TIME_CFG1     0x54EC1168
 118 #define CFG_MDDRC_TIME_CFG2     0x35210864
 119
 120 #define CFG_MICRON_NOP          0x01380000
 121 #define CFG_MICRON_PCHG_ALL     0x01100400
 122 #define CFG_MICRON_EM2          0x01020000
 123 #define CFG_MICRON_EM3          0x01030000
 124 #define CFG_MICRON_EN_DLL       0x01010000
 125 #define CFG_MICRON_RFSH         0x01080000
 126 #define CFG_MICRON_INIT_DEV_OP  0x01000432
 127 #define CFG_MICRON_OCD_DEFAULT  0x01010780
 128
 129 /* DDR Priority Manager Configuration */
 130 #define CFG_MDDRCGRP_PM_CFG1    0x000777AA
 131 #define CFG_MDDRCGRP_PM_CFG2    0x00000055
 132 #define CFG_MDDRCGRP_HIPRIO_CFG 0x00000000
 133 #define CFG_MDDRCGRP_LUT0_MU    0x11111117
 134 #define CFG_MDDRCGRP_LUT0_ML    0x7777777A
 135 #define CFG_MDDRCGRP_LUT1_MU    0x4444EEEE
 136 #define CFG_MDDRCGRP_LUT1_ML    0xEEEEEEEE
 137 #define CFG_MDDRCGRP_LUT2_MU    0x44444444
 138 #define CFG_MDDRCGRP_LUT2_ML    0x44444444
 139 #define CFG_MDDRCGRP_LUT3_MU    0x55555555
 140 #define CFG_MDDRCGRP_LUT3_ML    0x55555558
 141 #define CFG_MDDRCGRP_LUT4_MU    0x11111111
 142 #define CFG_MDDRCGRP_LUT4_ML    0x1111117C
 143 #define CFG_MDDRCGRP_LUT0_AU    0x33333377
 144 #define CFG_MDDRCGRP_LUT0_AL    0x7777EEEE
 145 #define CFG_MDDRCGRP_LUT1_AU    0x11111111
 146 #define CFG_MDDRCGRP_LUT1_AL    0x11111111
 147 #define CFG_MDDRCGRP_LUT2_AU    0x11111111
 148 #define CFG_MDDRCGRP_LUT2_AL    0x11111111
 149 #define CFG_MDDRCGRP_LUT3_AU    0x11111111
 150 #define CFG_MDDRCGRP_LUT3_AL    0x11111111
 151 #define CFG_MDDRCGRP_LUT4_AU    0x11111111
 152 #define CFG_MDDRCGRP_LUT4_AL    0x11111111
 153
 154 /*
 155  * NOR FLASH on the Local Bus
 156  */
 157 #define CFG_FLASH_CFI                           /* use the Common Flash Interface */
 158 #define CFG_FLASH_CFI_DRIVER                    /* use the CFI driver */
 159 #define CFG_FLASH_BASE          0xFC000000      /* start of FLASH   */
 160 #define CFG_FLASH_SIZE          0x04000000      /* max flash size in bytes */
 161 #define CFG_FLASH_USE_BUFFER_WRITE
 162
 163 #define CFG_MAX_FLASH_BANKS     1               /* number of banks */
 164 #define CFG_FLASH_BANKS_LIST    {CFG_FLASH_BASE}
 165 #define CFG_MAX_FLASH_SECT      256             /* max sectors per device */
 166
 167 #undef CFG_FLASH_CHECKSUM
 168
 169 /*
 170  * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
 171  * window is 64KB
 172  */
 173 #define CFG_CPLD_BASE           0x82000000
 174 #define CFG_CPLD_SIZE           0x00010000      /* 64 KB */
 175
 176 #define CFG_SRAM_BASE           0x30000000
 177 #define CFG_SRAM_SIZE           0x00020000      /* 128 KB */
 178
 179 #define CFG_CS0_CFG             0x05059310      /* ALE active low, data size 4bytes */
 180 #define CFG_CS2_CFG             0x05059010      /* ALE active low, data size 1byte */
 181
 182 /* Use SRAM for initial stack */
 183 #define CFG_INIT_RAM_ADDR       CFG_SRAM_BASE           /* Initial RAM address */
 184 #define CFG_INIT_RAM_END        CFG_SRAM_SIZE           /* End of used area in RAM */
 185
 186 #define CFG_GBL_DATA_SIZE       0x100                   /* num bytes initial data */
 187 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 188 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 189
 190 #define CFG_MONITOR_BASE        TEXT_BASE               /* Start of monitor */
 191 #define CFG_MONITOR_LEN         (256 * 1024)            /* Reserve 256 kB for Mon */
 192 #define CFG_MALLOC_LEN          (512 * 1024)            /* Reserved for malloc */
 193
 194 /*
 195  * Serial Port
 196  */
 197 #define CONFIG_CONS_INDEX     1
 198 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 199
 200 /*
 201  * Serial console configuration
 202  */
 203 #define CONFIG_PSC_CONSOLE      3       /* console is on PSC3 */
 204 #if CONFIG_PSC_CONSOLE != 3
 205 #error CONFIG_PSC_CONSOLE must be 3
 206 #endif
 207 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
 208 #define CFG_BAUDRATE_TABLE  \
 209         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 210
 211 #define CONSOLE_FIFO_TX_SIZE    FIFOC_PSC3_TX_SIZE
 212 #define CONSOLE_FIFO_TX_ADDR    FIFOC_PSC3_TX_ADDR
 213 #define CONSOLE_FIFO_RX_SIZE    FIFOC_PSC3_RX_SIZE
 214 #define CONSOLE_FIFO_RX_ADDR    FIFOC_PSC3_RX_ADDR
 215
 216 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 217 /* Use the HUSH parser */
 218 #define CFG_HUSH_PARSER
 219 #ifdef  CFG_HUSH_PARSER
 220 #define CFG_PROMPT_HUSH_PS2 "> "
 221 #endif
 222
 223 /*
 224  * PCI
 225  */
 226 #ifdef CONFIG_PCI
 227
 228 /*
 229  * General PCI
 230  */
 231 #define CFG_PCI_MEM_BASE        0xA0000000
 232 #define CFG_PCI_MEM_PHYS        CFG_PCI_MEM_BASE
 233 #define CFG_PCI_MEM_SIZE        0x10000000      /* 256M */
 234 #define CFG_PCI_MMIO_BASE       (CFG_PCI_MEM_BASE + CFG_PCI_MEM_SIZE)
 235 #define CFG_PCI_MMIO_PHYS       CFG_PCI_MMIO_BASE
 236 #define CFG_PCI_MMIO_SIZE       0x10000000      /* 256M */
 237 #define CFG_PCI_IO_BASE         0x00000000
 238 #define CFG_PCI_IO_PHYS         0x84000000
 239 #define CFG_PCI_IO_SIZE         0x01000000      /* 16M */
 240
 241
 242 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 243
 244 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 245
 246 #endif
 247
 248 /* I2C */
 249 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
 250 #undef CONFIG_SOFT_I2C                  /* so disable bit-banged I2C */
 251 #define CONFIG_I2C_MULTI_BUS
 252 #define CONFIG_I2C_CMD_TREE
 253 #define CFG_I2C_SPEED           100000  /* I2C speed and slave address */
 254 #define CFG_I2C_SLAVE           0x7F
 255 #if 0
 256 #define CFG_I2C_NOPROBES        {{0,0x69}}      /* Don't probe these addrs */
 257 #endif
 258
 259 /*
 260  * EEPROM configuration
 261  */
 262 #define CFG_I2C_EEPROM_ADDR_LEN         2       /* 16-bit EEPROM address */
 263 #define CFG_I2C_EEPROM_ADDR             0x50    /* Atmel: AT24C32A-10TQ-2.7 */
 264 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* 10ms of delay */
 265 #define CFG_EEPROM_PAGE_WRITE_BITS      5       /* 32-Byte Page Write Mode */
 266
 267 /*
 268  * Ethernet configuration
 269  */
 270 #define CONFIG_MPC512x_FEC      1
 271 #define CONFIG_NET_MULTI
 272 #define CONFIG_PHY_ADDR         0x1
 273 #define CONFIG_MII              1       /* MII PHY management           */
 274
 275 #if 0
 276 /*
 277  * Configure on-board RTC
 278  */
 279 #define CONFIG_RTC_DS1374                       /* use ds1374 rtc via i2c       */
 280 #define CFG_I2C_RTC_ADDR                0x68    /* at address 0x68              */
 281 #endif
 282
 283 /*
 284  * Environment
 285  */
 286 #define CFG_ENV_IS_IN_FLASH     1
 287 /* This has to be a multiple of the Flash sector size */
 288 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 289 #define CFG_ENV_SIZE            0x2000
 290 #define CFG_ENV_SECT_SIZE       0x40000 /* one sector (256K) for env */
 291
 292 /* Address and size of Redundant Environment Sector     */
 293 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
 294 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 295
 296 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 297 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 298
 299 #include <config_cmd_default.h>
 300
 301 #define CONFIG_CMD_ASKENV
 302 #define CONFIG_CMD_DHCP
 303 #define CONFIG_CMD_I2C
 304 #define CONFIG_CMD_MII
 305 #define CONFIG_CMD_NFS
 306 #define CONFIG_CMD_PING
 307 #define CONFIG_CMD_REGINFO
 308 #define CONFIG_CMD_EEPROM
 309
 310 #if defined(CONFIG_PCI)
 311 #define CONFIG_CMD_PCI
 312 #endif
 313
 314 /*
 315  * Watchdog timeout = CFG_WATCHDOG_VALUE * 65536 / IPS clock.
 316  * For example, when IPS is set to 66MHz and CFG_WATCHDOG_VALUE is set
 317  * to 0xFFFF, watchdog timeouts after about 64s. For details refer
 318  * to chapter 36 of the MPC5121e Reference Manual.
 319  */
 320 /* #define CONFIG_WATCHDOG */           /* enable watchdog */
 321 #define CFG_WATCHDOG_VALUE 0xFFFF
 322
 323  /*
 324  * Miscellaneous configurable options
 325  */
 326 #define CFG_LONGHELP                    /* undef to save memory */
 327 #define CFG_LOAD_ADDR   0x2000000       /* default load address */
 328 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt */
 329
 330 #ifdef CONFIG_CMD_KGDB
 331         #define CFG_CBSIZE      1024    /* Console I/O Buffer Size */
 332 #else
 333         #define CFG_CBSIZE      256     /* Console I/O Buffer Size */
 334 #endif
 335
 336
 337 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
 338 #define CFG_MAXARGS     16              /* max number of command args */
 339 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 340 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 341
 342 /*
 343  * For booting Linux, the board info and command line data
 344  * have to be in the first 8 MB of memory, since this is
 345  * the maximum mapped by the Linux kernel during initialization.
 346  */
 347 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux*/
 348
 349 /* Cache Configuration */
 350 #define CFG_DCACHE_SIZE         32768
 351 #define CFG_CACHELINE_SIZE      32
 352 #ifdef CONFIG_CMD_KGDB
 353 #define CFG_CACHELINE_SHIFT     5       /*log base 2 of the above value*/
 354 #endif
 355
 356 #define CFG_HID0_INIT   0x000000000
 357 #define CFG_HID0_FINAL  HID0_ENABLE_MACHINE_CHECK
 358 #define CFG_HID2        HID2_HBE
 359
 360 /*
 361  * Internal Definitions
 362  *
 363  * Boot Flags
 364  */
 365 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
 366 #define BOOTFLAG_WARM           0x02    /* Software reboot */
 367
 368 #ifdef CONFIG_CMD_KGDB
 369 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 370 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 371 #endif
 372
 373 /*
 374  * Environment Configuration
 375  */
 376 #define CONFIG_TIMESTAMP
 377
 378 #define CONFIG_HOSTNAME         ads5121
 379 #define CONFIG_BOOTFILE         ads5121/uImage
 380 #define CONFIG_ROOTPATH         /opt/eldk/pcc_6xx
 381
 382 #define CONFIG_LOADADDR         400000  /* default location for tftp and bootm */
 383
 384 #define CONFIG_BOOTDELAY        5       /* -1 disables auto-boot */
 385 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
 386
 387 #define CONFIG_BAUDRATE         115200
 388
 389 #define CONFIG_PREBOOT  "echo;" \
 390         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 391         "echo"
 392
 393 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 394         "u-boot_addr_r=200000\0"                                        \
 395         "kernel_addr_r=300000\0"                                        \
 396         "fdt_addr_r=400000\0"                                           \
 397         "ramdisk_addr_r=500000\0"                                       \
 398         "u-boot_addr=FFF00000\0"                                        \
 399         "kernel_addr=FC040000\0"                                        \
 400         "fdt_addr=FC2C0000\0"                                           \
 401         "ramdisk_addr=FC300000\0"                                       \
 402         "ramdiskfile=ads5121/uRamdisk\0"                                \
 403         "fdtfile=ads5121/ads5121.dtb\0"                                 \
 404         "u-boot=ads5121/u-boot.bin\0"                                   \
 405         "netdev=eth0\0"                                                 \
 406         "consdev=ttyPSC0\0"                                             \
 407         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 408                 "nfsroot=${serverip}:${rootpath}\0"                     \
 409         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 410         "addip=setenv bootargs ${bootargs} "                            \
 411                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 412                 ":${hostname}:${netdev}:off panic=1\0"                  \
 413         "addtty=setenv bootargs ${bootargs} "                           \
 414                 "console=${consdev},${baudrate}\0"                      \
 415         "flash_nfs=run nfsargs addip addtty;"                           \
 416                 "bootm ${kernel_addr} - ${fdt_addr}\0"          \
 417         "flash_self=run ramargs addip addtty;"                          \
 418                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 419         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 420                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 421                 "run nfsargs addip addtty;"                             \
 422                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 423         "net_self=tftp ${kernel_addr_r} ${bootfile};"                   \
 424                 "tftp ${ramdisk_addr_r} ${ramdiskfile};"                \
 425                 "tftp ${fdt_addr_r} ${fdtfile};"                                \
 426                 "run ramargs addip addtty;"                             \
 427                 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
 428         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                                \
 429         "update=protect off ${u-boot_addr} +${filesize};"               \
 430                 "era ${u-boot_addr} +${filesize};"                      \
 431                 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"    \
 432         "upd=run load update\0"                                         \
 433         ""
 434
 435 #define CONFIG_BOOTCOMMAND      "run flash_self"
 436
 437 #define CONFIG_OF_LIBFDT        1
 438 #define CONFIG_OF_BOARD_SETUP   1
 439
 440 #define OF_CPU                  "PowerPC,5121@0"
 441 #define OF_SOC                  "soc@80000000"
 442 #define OF_SOC_OLD              "soc5121@80000000"
 443 #define OF_TBCLK                (bd->bi_busfreq / 4)
 444 #define OF_STDOUT_PATH          "/soc@80000000/serial@11300"
 445
 446 #endif  /* __CONFIG_H */