include/configs/TQM885D.h

   1 /*
   2  * (C) Copyright 2000-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2006
   6  * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * board/config.h - configuration options, board specific
  29  */
  30
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 /*
  35  * High Level Configuration Options
  36  * (easy to change)
  37  */
  38
  39 #define CONFIG_MPC885           1       /* This is a MPC885 CPU         */
  40 #define CONFIG_TQM885D          1       /* ...on a TQM88D module        */
  41
  42 #define CONFIG_8xx_OSCLK                10000000        /*  10 MHz - PLL input clock    */
  43 #define CFG_8xx_CPUCLK_MIN              15000000        /*  15 MHz - CPU minimum clock  */
  44 #define CFG_8xx_CPUCLK_MAX              133000000       /* 133 MHz - CPU maximum clock  */
  45 #define CONFIG_8xx_CPUCLK_DEFAULT       66000000        /*  66 MHz - CPU default clock  */
  46                                                 /* (it will be used if there is no      */
  47                                                 /* 'cpuclk' variable with valid value)  */
  48
  49 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  50
  51 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  52
  53 #define CONFIG_BOOTCOUNT_LIMIT
  54
  55 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  56
  57 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  58
  59 #define CONFIG_PREBOOT  "echo;" \
  60         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  61         "echo"
  62
  63 #undef  CONFIG_BOOTARGS
  64
  65 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  66         "netdev=eth0\0"                                                 \
  67         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  68                 "nfsroot=${serverip}:${rootpath}\0"                     \
  69         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  70         "addip=setenv bootargs ${bootargs} "                            \
  71                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  72                 ":${hostname}:${netdev}:off panic=1\0"                  \
  73         "flash_nfs=run nfsargs addip;"                                  \
  74                 "bootm ${kernel_addr}\0"                                \
  75         "flash_self=run ramargs addip;"                                 \
  76                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  77         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  78         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  79         "bootfile=/tftpboot/TQM885D/uImage\0"                           \
  80         "fdt_addr=400C0000\0"                                           \
  81         "kernel_addr=40100000\0"                                        \
  82         "ramdisk_addr=40280000\0"                                       \
  83         "load=tftp 200000 ${u-boot}\0"                                  \
  84         "update=protect off 40000000 +${filesize};"                     \
  85                 "erase 40000000 +${filesize};"                          \
  86                 "cp.b 200000 40000000 ${filesize};"                     \
  87                 "protect on 40000000 +${filesize}\0"                    \
  88         ""
  89 #define CONFIG_BOOTCOMMAND      "run flash_self"
  90
  91 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  92 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  93
  94 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  95
  96 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  97
  98 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  99
 100 /* enable I2C and select the hardware/software driver */
 101 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 102 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 103
 104 #define CFG_I2C_SPEED           93000   /* 93 kHz is supposed to work   */
 105 #define CFG_I2C_SLAVE           0xFE
 106
 107 #ifdef CONFIG_SOFT_I2C
 108 /*
 109  * Software (bit-bang) I2C driver configuration
 110  */
 111 #define PB_SCL          0x00000020      /* PB 26 */
 112 #define PB_SDA          0x00000010      /* PB 27 */
 113
 114 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 115 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 116 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 117 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 118 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 119                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 120 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 121                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 122 #define I2C_DELAY       udelay(2)       /* 1/4 I2C clock duration */
 123 #endif  /* CONFIG_SOFT_I2C */
 124
 125 #define CFG_I2C_EEPROM_ADDR     0x50            /* EEPROM AT24C??       */
 126 #define CFG_I2C_EEPROM_ADDR_LEN 2               /* two byte address     */
 127 #define CFG_EEPROM_PAGE_WRITE_BITS      4
 128 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* and takes up to 10 msec */
 129
 130 # define CONFIG_RTC_DS1337 1
 131 # define CFG_I2C_RTC_ADDR 0x68
 132
 133 /*
 134  * BOOTP options
 135  */
 136 #define CONFIG_BOOTP_SUBNETMASK
 137 #define CONFIG_BOOTP_GATEWAY
 138 #define CONFIG_BOOTP_HOSTNAME
 139 #define CONFIG_BOOTP_BOOTPATH
 140 #define CONFIG_BOOTP_BOOTFILESIZE
 141
 142
 143 #define CONFIG_MAC_PARTITION
 144 #define CONFIG_DOS_PARTITION
 145
 146 #undef CONFIG_RTC_MPC8xx                /* MPC885 does not support RTC  */
 147
 148 #define CONFIG_TIMESTAMP                /* but print image timestmps    */
 149
 150
 151 /*
 152  * Command line configuration.
 153  */
 154 #include <config_cmd_default.h>
 155
 156 #define CONFIG_CMD_ASKENV
 157 #define CONFIG_CMD_DATE
 158 #define CONFIG_CMD_DHCP
 159 #define CONFIG_CMD_EEPROM
 160 #define CONFIG_CMD_I2C
 161 #define CONFIG_CMD_IDE
 162 #define CONFIG_CMD_MII
 163 #define CONFIG_CMD_NFS
 164 #define CONFIG_CMD_PING
 165
 166
 167 /*
 168  * Miscellaneous configurable options
 169  */
 170 #define CFG_LONGHELP                    /* undef to save memory         */
 171 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 172
 173 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 174 #define CFG_HUSH_PARSER         1       /* Use the HUSH parser          */
 175 #ifdef  CFG_HUSH_PARSER
 176 #define CFG_PROMPT_HUSH_PS2     "> "
 177 #endif
 178
 179 #if defined(CONFIG_CMD_KGDB)
 180 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 181 #else
 182 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 183 #endif
 184 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 185 #define CFG_MAXARGS             16      /* max number of command args   */
 186 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 187
 188 #define CFG_MEMTEST_START       0x0100000       /* memtest works on     */
 189 #define CFG_MEMTEST_END         0x0300000       /* 1 ... 3 MB in DRAM   */
 190 #define CFG_ALT_MEMTEST                         /* alternate, more extensive
 191                                                    memory test.*/
 192
 193 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 194
 195 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 196
 197 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 198
 199 /*
 200  * Enable loopw command.
 201  */
 202 #define CONFIG_LOOPW
 203
 204 /*
 205  * Low Level Configuration Settings
 206  * (address mappings, register initial values, etc.)
 207  * You should know what you are doing if you make changes here.
 208  */
 209 /*-----------------------------------------------------------------------
 210  * Internal Memory Mapped Register
 211  */
 212 #define CFG_IMMR                0xFFF00000
 213
 214 /*-----------------------------------------------------------------------
 215  * Definitions for initial stack pointer and data area (in DPRAM)
 216  */
 217 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 218 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 219 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 220 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 221 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 222
 223 /*-----------------------------------------------------------------------
 224  * Start addresses for the final memory configuration
 225  * (Set up by the startup code)
 226  * Please note that CFG_SDRAM_BASE _must_ start at 0
 227  */
 228 #define CFG_SDRAM_BASE          0x00000000
 229 #define CFG_FLASH_BASE          0x40000000
 230 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 231 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 232 #define CFG_MALLOC_LEN          (256 << 10)     /* Reserve 128 kB for malloc()  */
 233
 234 /*
 235  * For booting Linux, the board info and command line data
 236  * have to be in the first 8 MB of memory, since this is
 237  * the maximum mapped by the Linux kernel during initialization.
 238  */
 239 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 240
 241 /*-----------------------------------------------------------------------
 242  * FLASH organization
 243  */
 244
 245 /* use CFI flash driver */
 246 #define CFG_FLASH_CFI           1       /* Flash is CFI conformant */
 247 #define CFG_FLASH_CFI_DRIVER    1       /* Use the common driver */
 248 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE }
 249 #define CFG_FLASH_EMPTY_INFO
 250 #define CFG_FLASH_USE_BUFFER_WRITE      1
 251 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks */
 252 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip */
 253
 254 #define CFG_ENV_IS_IN_FLASH     1
 255 #define CFG_ENV_OFFSET          0x40000 /*   Offset   of Environment Sector     */
 256 #define CFG_ENV_SIZE            0x08000 /* Total Size of Environment            */
 257 #define CFG_ENV_SECT_SIZE       0x40000 /* Total Size of Environment Sector     */
 258
 259 /* Address and size of Redundant Environment Sector     */
 260 #define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
 261 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 262
 263 /*-----------------------------------------------------------------------
 264  * Hardware Information Block
 265  */
 266 #define CFG_HWINFO_OFFSET       0x0003FFC0      /* offset of HW Info block */
 267 #define CFG_HWINFO_SIZE         0x00000040      /* size   of HW Info block */
 268 #define CFG_HWINFO_MAGIC        0x54514D38      /* 'TQM8' */
 269
 270 /*-----------------------------------------------------------------------
 271  * Cache Configuration
 272  */
 273 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 274 #if defined(CONFIG_CMD_KGDB)
 275 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 276 #endif
 277
 278 /*-----------------------------------------------------------------------
 279  * SYPCR - System Protection Control                            11-9
 280  * SYPCR can only be written once after reset!
 281  *-----------------------------------------------------------------------
 282  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 283  */
 284 #if defined(CONFIG_WATCHDOG)
 285 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 286                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 287 #else
 288 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 289 #endif
 290
 291 /*-----------------------------------------------------------------------
 292  * SIUMCR - SIU Module Configuration                            11-6
 293  *-----------------------------------------------------------------------
 294  * PCMCIA config., multi-function pin tri-state
 295  */
 296 #ifndef CONFIG_CAN_DRIVER
 297 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 298 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 299 #define CFG_SIUMCR      (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 300 #endif  /* CONFIG_CAN_DRIVER */
 301
 302 /*-----------------------------------------------------------------------
 303  * TBSCR - Time Base Status and Control                         11-26
 304  *-----------------------------------------------------------------------
 305  * Clear Reference Interrupt Status, Timebase freezing enabled
 306  */
 307 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 308
 309 /*-----------------------------------------------------------------------
 310  * PISCR - Periodic Interrupt Status and Control                11-31
 311  *-----------------------------------------------------------------------
 312  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 313  */
 314 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 315
 316 /*-----------------------------------------------------------------------
 317  * SCCR - System Clock and reset Control Register               15-27
 318  *-----------------------------------------------------------------------
 319  * Set clock output, timebase and RTC source and divider,
 320  * power management and some other internal clocks
 321  */
 322 #define SCCR_MASK       SCCR_EBDF11
 323 #define CFG_SCCR        (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 324                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 325                          SCCR_DFALCD00)
 326
 327 /*-----------------------------------------------------------------------
 328  * PCMCIA stuff
 329  *-----------------------------------------------------------------------
 330  *
 331  */
 332 #define CFG_PCMCIA_MEM_ADDR     (0xE0000000)
 333 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 334 #define CFG_PCMCIA_DMA_ADDR     (0xE4000000)
 335 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 336 #define CFG_PCMCIA_ATTRB_ADDR   (0xE8000000)
 337 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 338 #define CFG_PCMCIA_IO_ADDR      (0xEC000000)
 339 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 340
 341 /*-----------------------------------------------------------------------
 342  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 343  *-----------------------------------------------------------------------
 344  */
 345
 346 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 347
 348 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 349 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 350 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 351
 352 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 353 #define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
 354
 355 #define CFG_ATA_IDE0_OFFSET     0x0000
 356
 357 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
 358
 359 /* Offset for data I/O                  */
 360 #define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
 361
 362 /* Offset for normal register accesses  */
 363 #define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
 364
 365 /* Offset for alternate registers       */
 366 #define CFG_ATA_ALT_OFFSET      0x0100
 367
 368 /*-----------------------------------------------------------------------
 369  *
 370  *-----------------------------------------------------------------------
 371  *
 372  */
 373 #define CFG_DER 0
 374
 375 /*
 376  * Init Memory Controller:
 377  *
 378  * BR0/1 and OR0/1 (FLASH)
 379  */
 380
 381 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 382 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 383
 384 /* used to re-map FLASH both when starting from SRAM or FLASH:
 385  * restrict access enough to keep SRAM working (if any)
 386  * but not too much to meddle with FLASH accesses
 387  */
 388 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 389 #define CFG_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
 390
 391 /*
 392  * FLASH timing: Default value of OR0 after reset
 393  */
 394 #define CFG_OR_TIMING_FLASH     (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
 395                                  OR_SCY_6_CLK | OR_TRLX)
 396
 397 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 398 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 399 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 400
 401 #define CFG_OR1_REMAP   CFG_OR0_REMAP
 402 #define CFG_OR1_PRELIM  CFG_OR0_PRELIM
 403 #define CFG_BR1_PRELIM  ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 404
 405 /*
 406  * BR2/3 and OR2/3 (SDRAM)
 407  *
 408  */
 409 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 410 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 411 #define SDRAM_MAX_SIZE          (256 << 20)     /* max 256 MB per bank  */
 412
 413 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 414 #define CFG_OR_TIMING_SDRAM     0x00000A00
 415
 416 #define CFG_OR2_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
 417 #define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 418
 419 #ifndef CONFIG_CAN_DRIVER
 420 #define CFG_OR3_PRELIM  CFG_OR2_PRELIM
 421 #define CFG_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 422 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 423 #define CFG_CAN_BASE            0xC0000000      /* CAN mapped at 0xC0000000     */
 424 #define CFG_CAN_OR_AM           0xFFFF8000      /* 32 kB address mask           */
 425 #define CFG_OR3_CAN             (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
 426 #define CFG_BR3_CAN             ((CFG_CAN_BASE & BR_BA_MSK) | \
 427                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 428 #endif  /* CONFIG_CAN_DRIVER */
 429
 430 /*
 431  * 4096 Rows from SDRAM example configuration
 432  * 1000 factor s -> ms
 433  * 64   PTP (pre-divider from MPTPR) from SDRAM example configuration
 434  * 4    Number of refresh cycles per period
 435  * 64   Refresh cycle in ms per number of rows
 436  */
 437 #define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
 438
 439 /*
 440  * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
 441  *
 442  *                        CPUclock(MHz) * 31.2
 443  * CFG_MAMR_PTA = -----------------------------------     with DFBRG = 0
 444  *                2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
 445  *
 446  * CPU clock =  15 MHz:  CFG_MAMR_PTA =  29   ->  4 * 7.73 us
 447  * CPU clock =  50 MHz:  CFG_MAMR_PTA =  97   ->  4 * 7.76 us
 448  * CPU clock =  66 MHz:  CFG_MAMR_PTA = 128   ->  4 * 7.75 us
 449  * CPU clock = 133 MHz:  CFG_MAMR_PTA = 255   ->  4 * 7.67 us
 450  *
 451  * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
 452  * be met also in the default configuration, i.e. if environment variable
 453  * 'cpuclk' is not set.
 454  */
 455 #define CFG_MAMR_PTA            128
 456
 457 /*
 458  * Memory Periodic Timer Prescaler Register (MPTPR) values.
 459  */
 460 /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
 461 #define CFG_MPTPR_2BK_4K        MPTPR_PTP_DIV16
 462 /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
 463 #define CFG_MPTPR_2BK_8K        MPTPR_PTP_DIV8
 464
 465 /*
 466  * MAMR settings for SDRAM
 467  */
 468
 469 /* 8 column SDRAM */
 470 #define CFG_MAMR_8COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 471                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 472                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 473 /* 9 column SDRAM */
 474 #define CFG_MAMR_9COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 475                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 476                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 477 /* 10 column SDRAM */
 478 #define CFG_MAMR_10COL  ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 479                          MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9  |   \
 480                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 481
 482 /*
 483  * Internal Definitions
 484  *
 485  * Boot Flags
 486  */
 487 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 488 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 489
 490 /*
 491  * Network configuration
 492  */
 493 #define CONFIG_SCC2_ENET                /* enable ethernet on SCC2 */
 494 #define CONFIG_FEC_ENET                 /* enable ethernet on FEC */
 495 #define CONFIG_ETHER_ON_FEC1            /* ... for FEC1 */
 496 #define CONFIG_ETHER_ON_FEC2            /* ... for FEC2 */
 497
 498 #if defined(CONFIG_CMD_MII)
 499 #define CFG_DISCOVER_PHY
 500 #endif
 501
 502 #define CONFIG_NET_RETRY_COUNT 1        /* reduce max. timeout before
 503                                            switching to another netwok (if the
 504                                            tried network is unreachable) */
 505
 506 #define CONFIG_ETHPRIME         "SCC ETHERNET"
 507
 508 #endif  /* __CONFIG_H */