include/configs/RPXlite_DW.h

   1 /*
   2  * (C) Copyright 2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * board/config.h - configuration options, board specific
  27  */
  28
  29 /* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
  30  * U-BOOT port on RPXlite board
  31  */
  32
  33 /*
  34  * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
  35  * U-BOOT port on RPXlite DW version board--RPXlite_DW
  36  * June 8 ,2004
  37  */
  38
  39 #ifndef __CONFIG_H
  40 #define __CONFIG_H
  41
  42 /*
  43  * High Level Configuration Options
  44  * (easy to change)
  45  */
  46
  47 /* #define DEBUG        1 */
  48 /* #define DEPLOYMENT   1 */
  49
  50 #undef  CONFIG_MPC860
  51 #define CONFIG_MPC823           1       /* This is a MPC823e CPU. */
  52 #define CONFIG_RPXLITE          1       /* RPXlite DW version board */
  53
  54 #ifdef  CONFIG_LCD                      /* with LCD controller ?        */
  55 #define CONFIG_SPLASH_SCREEN            /* ... with splashscreen support*/
  56 #endif
  57
  58 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  59 #undef  CONFIG_8xx_CONS_SMC2
  60 #undef  CONFIG_8xx_CONS_NONE
  61 #define CONFIG_BAUDRATE         9600    /* console default baudrate = 9600bps   */
  62
  63 #ifdef DEBUG
  64 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  65 #else
  66 #define CONFIG_BOOTDELAY        6       /* autoboot after 6 seconds     */
  67
  68 #ifdef DEPLOYMENT
  69 #define CONFIG_BOOT_RETRY_TIME          -1
  70 #define CONFIG_AUTOBOOT_KEYED
  71 #define CONFIG_AUTOBOOT_PROMPT          "autoboot in %d seconds (stop with 'st')...\n"
  72 #define CONFIG_AUTOBOOT_STOP_STR        "st"
  73 #define CONFIG_ZERO_BOOTDELAY_CHECK
  74 #define CONFIG_RESET_TO_RETRY           1
  75 #define CONFIG_BOOT_RETRY_MIN           1
  76 #endif  /* DEPLOYMENT */
  77 #endif  /* DEBUG */
  78
  79 /* pre-boot commands */
  80 #define CONFIG_PREBOOT          "setenv stdout serial;setenv stdin serial"
  81
  82 #undef  CONFIG_BOOTARGS
  83 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  84         "netdev=eth0\0"                                                 \
  85         "nfsargs=setenv bootargs console=tty0 console=ttyS0,9600 "      \
  86                 "root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0"    \
  87         "ramargs=setenv bootargs console=tty0 root=/dev/ram rw\0"       \
  88         "addip=setenv bootargs ${bootargs} "                            \
  89                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  90                 ":${hostname}:${netdev}:off panic=1\0"                  \
  91         "flash_nfs=run nfsargs addip;"                                  \
  92                 "bootm ${kernel_addr}\0"                                \
  93         "flash_self=run ramargs addip;"                                 \
  94                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  95         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  96         "gatewayip=172.16.115.254\0"                                    \
  97         "netmask=255.255.255.0\0"                                       \
  98         "kernel_addr=ff040000\0"                                        \
  99         "ramdisk_addr=ff200000\0"                                       \
 100         "ku=era ${kernel_addr} ff1fffff;cp.b 100000 ${kernel_addr} "    \
 101                 "${filesize};md ${kernel_addr};"                        \
 102                 "echo kernel updating finished\0"                       \
 103         "uu=protect off 1:0-4;era 1:0-4;cp.b 100000 ff000000 "          \
 104                 "${filesize};md ff000000;"                              \
 105                 "echo u-boot updating finished\0"                       \
 106         "eu=protect off 1:6;era 1:6;reset\0"                            \
 107         "lcd=setenv stdout lcd;setenv stdin lcd\0"                      \
 108         "ser=setenv stdout serial;setenv stdin serial\0"                \
 109         "verify=no"
 110
 111 #define CONFIG_BOOTCOMMAND      "run flash_self"
 112
 113 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 114 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
 115 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 116 #undef  CONFIG_STATUS_LED               /* disturbs display. Status LED disabled. */
 117
 118 /*
 119  * BOOTP options
 120  */
 121 #define CONFIG_BOOTP_SUBNETMASK
 122 #define CONFIG_BOOTP_GATEWAY
 123 #define CONFIG_BOOTP_HOSTNAME
 124 #define CONFIG_BOOTP_BOOTPATH
 125 #define CONFIG_BOOTP_BOOTFILESIZE
 126
 127
 128 #if 1          /* Enable this stuff could make image enlarge about 25KB. Mask it if you
 129                   don't want the advanced function */
 130
 131
 132 /*
 133  * Command line configuration.
 134  */
 135 #include <config_cmd_default.h>
 136
 137 #define CONFIG_CMD_ASKENV
 138 #define CONFIG_CMD_JFFS2
 139 #define CONFIG_CMD_PING
 140 #define CONFIG_CMD_ELF
 141 #define CONFIG_CMD_REGINFO
 142 #define CONFIG_CMD_DHCP
 143
 144 #ifdef  CONFIG_SPLASH_SCREEN
 145 #define CONFIG_CMD_BMP
 146 #endif
 147
 148
 149 /* test-only */
 150 #define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
 151 #define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */
 152
 153 #define CONFIG_NETCONSOLE
 154
 155 #endif  /* 1 */
 156
 157 /*
 158  * Miscellaneous configurable options
 159  */
 160 #define CFG_LONGHELP                    /* undef to save memory         */
 161 #define CFG_PROMPT      "u-boot>"       /* Monitor Command Prompt   */
 162
 163 #if defined(CONFIG_CMD_KGDB)
 164 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 165 #else
 166 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 167 #endif
 168
 169 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 170 #define CFG_MAXARGS     16              /* max number of command args   */
 171 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 172
 173 #define CFG_MEMTEST_START       0x0040000       /* memtest works on     */
 174 #define CFG_MEMTEST_END         0x00C0000       /* 4 ... 12 MB in DRAM  */
 175 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 176
 177 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 178 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 179
 180 /*
 181  * Low Level Configuration Settings
 182  * (address mappings, register initial values, etc.)
 183  * You should know what you are doing if you make changes here.
 184  */
 185 /*-----------------------------------------------------------------------
 186  * Internal Memory Mapped Register
 187  */
 188 #define CFG_IMMR                0xFA200000
 189
 190 /*-----------------------------------------------------------------------
 191  * Definitions for initial stack pointer and data area (in DPRAM)
 192  */
 193 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 194 #define CFG_INIT_RAM_END        0x2F00          /* End of used area in DPRAM    */
 195 #define CFG_GBL_DATA_SIZE       64              /* size in bytes reserved for initial data */
 196 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 197 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 198
 199 /*-----------------------------------------------------------------------
 200  * Start addresses for the final memory configuration
 201  * (Set up by the startup code)
 202  * Please note that CFG_SDRAM_BASE _must_ start at 0
 203  */
 204 #define CFG_SDRAM_BASE          0x00000000
 205 #define CFG_FLASH_BASE          0xFF000000
 206
 207 #if defined(DEBUG) || defined(CONFIG_CMD_IDE)
 208 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 209 #else
 210 #define CFG_MONITOR_LEN         (128 << 10)     /* Reserve 128 kB for Monitor */
 211 #endif
 212
 213 #define CFG_MONITOR_BASE        0xFF000000
 214 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 215
 216 /*
 217  * For booting Linux, the board info and command line data
 218  * have to be in the first 8 MB of memory, since this is
 219  * the maximum mapped by the Linux kernel during initialization.
 220  */
 221 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 222
 223 /*-----------------------------------------------------------------------
 224  * FLASH organization
 225  */
 226 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 227 #define CFG_MAX_FLASH_SECT      71      /* max number of sectors on one chip    */
 228 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 229 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 230
 231 #ifdef  CFG_ENV_IS_IN_NVRAM
 232 #define CFG_ENV_ADDR            0xFA000100
 233 #define CFG_ENV_SIZE            0x1000
 234 #else
 235 #define CFG_ENV_IS_IN_FLASH
 236 #define CFG_ENV_OFFSET          0x30000 /* Offset of Environment Sector         */
 237 #define CFG_ENV_SIZE            0x8000  /* Total Size of Environment Sector     */
 238 #endif  /* CFG_ENV_IS_IN_NVRAM */
 239
 240 #define CFG_RESET_ADDRESS       ((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res)))
 241
 242 /*-----------------------------------------------------------------------
 243  * Cache Configuration
 244  */
 245 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 246 #if defined(CONFIG_CMD_KGDB)
 247 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 248 #endif
 249
 250 /*-----------------------------------------------------------------------
 251  * SYPCR - System Protection Control    32-bit                  12-35
 252  * SYPCR can only be written once after reset!
 253  *-----------------------------------------------------------------------
 254  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 255  */
 256 #if defined(CONFIG_WATCHDOG)
 257 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 258                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 259 #else
 260 #define CFG_SYPCR       (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 261 #endif  /* We can get SYPCR: 0xFFFF0689. */
 262
 263 /*-----------------------------------------------------------------------
 264  * SIUMCR - SIU Module Configuration    32-bit                   12-30
 265  *-----------------------------------------------------------------------
 266  * PCMCIA config., multi-function pin tri-state
 267  */
 268 #define CFG_SIUMCR      (SIUMCR_MLRC10)        /* SIUMCR:0x00000800 */
 269
 270 /*---------------------------------------------------------------------
 271  * TBSCR - Time Base Status and Control  16-bit                  12-16
 272  *---------------------------------------------------------------------
 273  * Clear Reference Interrupt Status, Timebase freezing enabled
 274  */
 275 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
 276 /* TBSCR: 0x00C3 [SAM] */
 277
 278 /*-----------------------------------------------------------------------
 279  * RTCSC - Real-Time Clock Status and Control Register 16-bit    12-18
 280  *-----------------------------------------------------------------------
 281  * [RTC enabled but not stopped on FRZ]
 282  */
 283 #define CFG_RTCSC    (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) /* RTCSC:0x00C1        */
 284
 285 /*-----------------------------------------------------------------------
 286  * PISCR - Periodic Interrupt Status and Control 16-bit          12-23
 287  *-----------------------------------------------------------------------
 288  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 289  * [Periodic timer enabled,Periodic timer interrupt disable. ]
 290  */
 291 #define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)  /* PISCR:0x0083          */
 292
 293 /*-----------------------------------------------------------------------
 294  * PLPRCR - PLL, Low-Power, and Reset Control Register  32-bit   5-7
 295  *-----------------------------------------------------------------------
 296  * Reset PLL lock status sticky bit, timer expired status bit and timer
 297  * interrupt status bit
 298  */
 299 /* up to 64 MHz we use a 1:2 clock */
 300 #if defined(RPXlite_64MHz)
 301 #define CFG_PLPRCR      ( (7 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )   /*PLPRCR: 0x00700000. */
 302 #else
 303 #define CFG_PLPRCR      ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
 304 #endif
 305
 306 /*-----------------------------------------------------------------------
 307  * SCCR - System Clock and reset Control Register               5-3
 308  *-----------------------------------------------------------------------
 309  * Set clock output, timebase and RTC source and divider,
 310  * power management and some other internal clocks
 311  */
 312 #define SCCR_MASK       SCCR_EBDF00
 313 /* Up to 48MHz system clock, we use 1:1 SYSTEM/BUS ratio */
 314 #if defined(RPXlite_64MHz)
 315 #define CFG_SCCR        ( SCCR_TBS | SCCR_EBDF01 )  /* %%%SCCR:0x02020000 */
 316 #else
 317 #define CFG_SCCR        ( SCCR_TBS | SCCR_EBDF00 )  /* %%%SCCR:0x02000000 */
 318 #endif
 319
 320 /*-----------------------------------------------------------------------
 321  * PCMCIA stuff
 322  *-----------------------------------------------------------------------
 323  */
 324 #define CFG_PCMCIA_MEM_ADDR     (0xE0000000)
 325 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 326 #define CFG_PCMCIA_DMA_ADDR     (0xE4000000)
 327 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 328 #define CFG_PCMCIA_ATTRB_ADDR   (0xE8000000)
 329 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 330 #define CFG_PCMCIA_IO_ADDR      (0xEC000000)
 331 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 332
 333 /*-----------------------------------------------------------------------
 334  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 335  *-----------------------------------------------------------------------
 336  */
 337 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 338
 339 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 340 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 341 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 342
 343 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 344 #define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
 345
 346 #define CFG_ATA_IDE0_OFFSET     0x0000
 347 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
 348
 349 /* Offset for data I/O                  */
 350 #define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
 351
 352 /* Offset for normal register accesses  */
 353 #define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
 354
 355 /* Offset for alternate registers       */
 356 #define CFG_ATA_ALT_OFFSET      0x0100
 357
 358 #define         CFG_DER         0
 359
 360 /*
 361  * Init Memory Controller:
 362  *
 363  * BR0 and OR0 (FLASH)
 364  */
 365 #define FLASH_BASE_PRELIM       0xFC000000      /* FLASH base   */
 366 #define CFG_PRELIM_OR_AM        0xFC000000      /* OR addr mask */
 367
 368 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 8, ETHR = 0, BIH = 1 */
 369 #define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_BI)
 370 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 371 #define CFG_BR0_PRELIM  ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
 372
 373 /*
 374  * BR1 and OR1 (SDRAM)
 375  *
 376  */
 377 #define SDRAM_BASE_PRELIM       0x00000000      /* SDRAM base   */
 378 #define SDRAM_MAX_SIZE          0x08000000      /* max 128 MB in system */
 379
 380 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 381 #define CFG_OR_TIMING_SDRAM     0x00000E00
 382 #define CFG_OR_AM_SDRAM         (-(SDRAM_MAX_SIZE & OR_AM_MSK))
 383 #define CFG_OR1_PRELIM  ( CFG_OR_AM_SDRAM | CFG_OR_TIMING_SDRAM )
 384 #define CFG_BR1_PRELIM  ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 385
 386 /* RPXlite mem setting */
 387 #define CFG_BR3_PRELIM  0xFA400001              /* BCSR */
 388 #define CFG_OR3_PRELIM  0xFF7F8900
 389 #define CFG_BR4_PRELIM  0xFA000401              /* NVRAM&SRAM */
 390 #define CFG_OR4_PRELIM  0xFFFE0040
 391
 392 /*
 393  * Memory Periodic Timer Prescaler
 394  */
 395 /* periodic timer for refresh */
 396 #if defined(RPXlite_64MHz)
 397 #define CFG_MAMR_PTA    32
 398 #else
 399 #define CFG_MAMR_PTA    20
 400 #endif
 401
 402 /*
 403  * Refresh clock Prescalar
 404  */
 405 #define CFG_MPTPR       MPTPR_PTP_DIV2
 406
 407 /*
 408  * MAMR settings for SDRAM
 409  */
 410
 411 /* 9 column SDRAM */
 412 #define CFG_MAMR_9COL  ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
 413                         MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10)
 414 /* CFG_MAMR_9COL:0x20904000 @ 64MHz */
 415
 416 /*
 417  * Internal Definitions
 418  *
 419  * Boot Flags
 420  */
 421 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 422 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 423
 424 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
 425 /* Configuration variable added by yooth. */
 426 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
 427 /*
 428  * BCSRx
 429  *
 430  * Board Status and Control Registers
 431  *
 432  */
 433 #define BCSR0 0xFA400000
 434 #define BCSR1 0xFA400001
 435 #define BCSR2 0xFA400002
 436 #define BCSR3 0xFA400003
 437
 438 #define BCSR0_ENMONXCVR 0x01    /* Monitor XVCR Control */
 439 #define BCSR0_ENNVRAM   0x02    /* CS4# Control */
 440 #define BCSR0_LED5      0x04    /* LED5 control 0='on' 1='off' */
 441 #define BCSR0_LED4      0x08    /* LED4 control 0='on' 1='off' */
 442 #define BCSR0_FULLDPLX  0x10    /* Ethernet XCVR Control */
 443 #define BCSR0_COLTEST   0x20
 444 #define BCSR0_ETHLPBK   0x40
 445 #define BCSR0_ETHEN     0x80
 446
 447 #define BCSR1_PCVCTL7   0x01    /* PC Slot B Control */
 448 #define BCSR1_PCVCTL6   0x02
 449 #define BCSR1_PCVCTL5   0x04
 450 #define BCSR1_PCVCTL4   0x08
 451 #define BCSR1_IPB5SEL   0x10
 452
 453 #define BCSR1_SMC1CTS   0x40    /* Added by SAM. */
 454 #define BCSR1_SMC1TRS   0x80    /* Added by SAM. */
 455
 456 #define BCSR2_ENRTCIRQ  0x01    /* Added by SAM. */
 457 #define BCSR2_ENBRG1    0x04    /* Added by SAM. */
 458
 459 #define BCSR2_ENPA5HDR  0x08    /* USB Control */
 460 #define BCSR2_ENUSBCLK  0x10
 461 #define BCSR2_USBPWREN  0x20
 462 #define BCSR2_USBSPD    0x40
 463 #define BCSR2_USBSUSP   0x80
 464
 465 #define BCSR3_BWKAPWR   0x01   /* Changed by SAM. Backup battery situation */
 466 #define BCSR3_IRQRTC    0x02   /* Changed by SAM. NVRAM Battery */
 467 #define BCSR3_RDY_BSY   0x04   /* Changed by SAM. Flash Operation */
 468 #define BCSR3_MPLX_LIN  0x08   /* Changed by SAM. Linear or Multiplexed address Mode */
 469
 470 #define BCSR3_D27       0x10      /* Dip Switch settings */
 471 #define BCSR3_D26       0x20
 472 #define BCSR3_D25       0x40
 473 #define BCSR3_D24       0x80
 474
 475 /*
 476  * Environment setting
 477  */
 478 #define CONFIG_ETHADDR  00:10:EC:00:37:5B
 479 #define CONFIG_IPADDR   172.16.115.7
 480 #define CONFIG_SERVERIP 172.16.115.6
 481 #define CONFIG_ROOTPATH /workspace/myfilesystem/target/
 482 #define CONFIG_BOOTFILE uImage.rpxusb
 483 #define CONFIG_HOSTNAME LITE_H1_DW
 484
 485 #endif  /* __CONFIG_H */