include/configs/RBC823.h

   1 /*
   2  * (C) Copyright 2000, 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * Modified by Udi Finkelstein udif@udif.com
   6  * For the RBC823 board.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * board/config.h - configuration options, board specific
  29  */
  30
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 /*
  35  * High Level Configuration Options
  36  * (easy to change)
  37  */
  38
  39 #define CONFIG_MPC823           1       /* This is a MPC823 CPU         */
  40 #define CONFIG_RBC823           1       /* ...on a RBC823 module        */
  41
  42
  43 #if 0
  44 #define DEBUG                   1
  45 #define CONFIG_LAST_STAGE_INIT
  46 #endif
  47 #define CONFIG_KEYBOARD         1       /* This board has a custom keybpard */
  48 #define CONFIG_LCD              1       /* use LCD controller ...       */
  49 #define CONFIG_HITACHI_SP19X001_Z1A     /* The LCD type we use */
  50
  51 #define CONFIG_8xx_CONS_SMC2    1       /* Console is on SMC2           */
  52 #undef  CONFIG_8xx_CONS_SMC1
  53 #undef  CONFIG_8xx_CONS_NONE
  54 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  55 #if 1
  56 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  57 #else
  58 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  59 #endif
  60
  61 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  62 #define CONFIG_8xx_GCLK_FREQ    48000000L
  63
  64 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  65
  66 #undef  CONFIG_BOOTARGS
  67 #define CONFIG_BOOTCOMMAND                                                      \
  68         "bootp; "                                                               \
  69         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  70         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
  71         "bootm"
  72
  73 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  74 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  75
  76 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  77
  78 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  79
  80 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  81
  82 /*
  83  * BOOTP options
  84  */
  85 #define CONFIG_BOOTP_SUBNETMASK
  86 #define CONFIG_BOOTP_GATEWAY
  87 #define CONFIG_BOOTP_HOSTNAME
  88 #define CONFIG_BOOTP_BOOTPATH
  89 #define CONFIG_BOOTP_BOOTFILESIZE
  90
  91
  92 #undef CONFIG_MAC_PARTITION
  93 #define CONFIG_DOS_PARTITION
  94
  95 #undef  CONFIG_RTC_MPC8xx               /* don't use internal RTC of MPC8xx (no battery)        */
  96
  97 #define CONFIG_HARD_I2C
  98 #define CFG_I2C_SPEED 40000
  99 #define CFG_I2C_SLAVE 0xfe
 100 #define CFG_I2C_EEPROM_ADDR             0x50
 101 #define CFG_I2C_EEPROM_ADDR_LEN         1
 102 #define CFG_EEPROM_WRITE_BITS           4
 103 #define CFG_EEPROM_WRITE_DELAY_MS       10
 104
 105 /*
 106  * Command line configuration.
 107  */
 108 #include <config_cmd_default.h>
 109
 110 #define CONFIG_CMD_ASKENV
 111 #define CONFIG_CMD_BEDBUG
 112 #define CONFIG_CMD_BMP
 113 #define CONFIG_CMD_CACHE
 114 #define CONFIG_CMD_CDP
 115 #define CONFIG_CMD_DHCP
 116 #define CONFIG_CMD_DIAG
 117 #define CONFIG_CMD_DOC
 118 #define CONFIG_CMD_EEPROM
 119 #define CONFIG_CMD_ELF
 120 #define CONFIG_CMD_FAT
 121 #define CONFIG_CMD_I2C
 122 #define CONFIG_CMD_IMMAP
 123 #define CONFIG_CMD_KGDB
 124 #define CONFIG_CMD_PING
 125 #define CONFIG_CMD_PORTIO
 126 #define CONFIG_CMD_REGINFO
 127 #define CONFIG_CMD_SAVES
 128 #define CONFIG_CMD_SDRAM
 129
 130 #undef CONFIG_CMD_SETGETDCR
 131 #undef CONFIG_CMD_XIMG
 132
 133 /*
 134  * Miscellaneous configurable options
 135  */
 136 #define CFG_LONGHELP                    /* undef to save memory         */
 137 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 138 #if defined(CONFIG_CMD_KGDB)
 139 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 140 #else
 141 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 142 #endif
 143 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 144 #define CFG_MAXARGS     16              /* max number of command args   */
 145 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 146
 147 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 148 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 149
 150 #define CFG_LOAD_ADDR           0x0100000       /* default load address */
 151
 152 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 153
 154 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 155
 156 /*
 157  * Low Level Configuration Settings
 158  * (address mappings, register initial values, etc.)
 159  * You should know what you are doing if you make changes here.
 160  */
 161 /*-----------------------------------------------------------------------
 162  * Internal Memory Mapped Register
 163  */
 164 #define CFG_IMMR                0xFF000000
 165
 166 /*-----------------------------------------------------------------------
 167  * Definitions for initial stack pointer and data area (in DPRAM)
 168  */
 169 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 170 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 171 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 172 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 173 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 174
 175 /*-----------------------------------------------------------------------
 176  * Start addresses for the final memory configuration
 177  * (Set up by the startup code)
 178  * Please note that CFG_SDRAM_BASE _must_ start at 0
 179  */
 180 #define CFG_SDRAM_BASE          0x00000000
 181 #define CFG_FLASH_BASE          0xFFF00000
 182 #if defined(DEBUG)
 183 #define CFG_MONITOR_LEN         (384 << 10)     /* Reserve 256 kB for Monitor   */
 184 #else
 185 #define CFG_MONITOR_LEN         (384 << 10)     /* Reserve 192 kB for Monitor   */
 186 #endif
 187 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 188 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 189
 190 /*
 191  * For booting Linux, the board info and command line data
 192  * have to be in the first 8 MB of memory, since this is
 193  * the maximum mapped by the Linux kernel during initialization.
 194  */
 195 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 196
 197 /*-----------------------------------------------------------------------
 198  * FLASH organization
 199  */
 200 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 201 #define CFG_MAX_FLASH_SECT      67      /* max number of sectors on one chip    */
 202
 203 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 204 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 205
 206 #define CFG_ENV_IS_IN_FLASH     1
 207 #define CFG_ENV_OFFSET          0x10000 /*   Offset   of Environment Sector     */
 208 #define CFG_ENV_SIZE            0x10000 /* Total Size of Environment Sector     */
 209
 210 /*-----------------------------------------------------------------------
 211  * Cache Configuration
 212  */
 213 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 214 #if defined(CONFIG_CMD_KGDB)
 215 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 216 #endif
 217
 218 /*-----------------------------------------------------------------------
 219  * SYPCR - System Protection Control                            11-9
 220  * SYPCR can only be written once after reset!
 221  *-----------------------------------------------------------------------
 222  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 223  */
 224 #if defined(CONFIG_WATCHDOG)
 225 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 226                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 227 #else
 228 /*
 229 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 230 */
 231 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP)
 232 #endif
 233
 234 /*-----------------------------------------------------------------------
 235  * SIUMCR - SIU Module Configuration                            11-6
 236  *-----------------------------------------------------------------------
 237  * PCMCIA config., multi-function pin tri-state
 238  */
 239 #define CFG_SIUMCR      (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC)
 240
 241 /*-----------------------------------------------------------------------
 242  * TBSCR - Time Base Status and Control                         11-26
 243  *-----------------------------------------------------------------------
 244  * Clear Reference Interrupt Status, Timebase freezing enabled
 245  */
 246 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 247
 248 /*-----------------------------------------------------------------------
 249  * RTCSC - Real-Time Clock Status and Control Register          11-27
 250  *-----------------------------------------------------------------------
 251  */
 252 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 253
 254 /*-----------------------------------------------------------------------
 255  * PISCR - Periodic Interrupt Status and Control                11-31
 256  *-----------------------------------------------------------------------
 257  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 258  */
 259 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 260
 261 /*-----------------------------------------------------------------------
 262  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 263  *-----------------------------------------------------------------------
 264  * Reset PLL lock status sticky bit, timer expired status bit and timer
 265  * interrupt status bit
 266  *
 267  */
 268
 269 /*
 270  * for 48 MHz, we use a 4 MHz clock * 12
 271  */
 272 #define CFG_PLPRCR                                                      \
 273                 ( (12-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_LOLRE )
 274
 275 /*-----------------------------------------------------------------------
 276  * SCCR - System Clock and reset Control Register               15-27
 277  *-----------------------------------------------------------------------
 278  * Set clock output, timebase and RTC source and divider,
 279  * power management and some other internal clocks
 280  */
 281 #define SCCR_MASK       SCCR_EBDF11
 282 #define CFG_SCCR        (SCCR_RTDIV   | SCCR_RTSEL    | SCCR_CRQEN    | \
 283                          SCCR_PRQEN   | SCCR_EBDF00   | \
 284                          SCCR_COM01   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 285                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD001 | \
 286                          SCCR_DFALCD00)
 287
 288 #ifdef NOT_USED
 289 /*-----------------------------------------------------------------------
 290  * PCMCIA stuff
 291  *-----------------------------------------------------------------------
 292  *
 293  */
 294 #define CFG_PCMCIA_MEM_ADDR     (0xE0000000)
 295 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 296 #define CFG_PCMCIA_DMA_ADDR     (0xE4000000)
 297 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 298 #define CFG_PCMCIA_ATTRB_ADDR   (0xE8000000)
 299 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 300 #define CFG_PCMCIA_IO_ADDR      (0xEC000000)
 301 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 302
 303 /*-----------------------------------------------------------------------
 304  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 305  *-----------------------------------------------------------------------
 306  */
 307
 308 #define CONFIG_IDE_PCCARD       1       /* Use IDE with PC Card Adapter */
 309
 310 #undef  CONFIG_IDE_PCMCIA               /* Direct IDE    not supported  */
 311 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 312 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 313
 314 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 315 #define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
 316
 317 #define CFG_ATA_IDE0_OFFSET     0x0000
 318
 319 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
 320
 321 /* Offset for data I/O                  */
 322 #define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
 323
 324 /* Offset for normal register accesses  */
 325 #define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
 326
 327 /* Offset for alternate registers       */
 328 #define CFG_ATA_ALT_OFFSET      0x0100
 329
 330 #endif
 331
 332 /************************************************************
 333  * Disk-On-Chip configuration
 334  ************************************************************/
 335 #define CFG_MAX_DOC_DEVICE      1       /* Max number of DOC devices            */
 336 #define CFG_DOC_SHORT_TIMEOUT
 337 #define CFG_DOC_SUPPORT_2000
 338 #define CFG_DOC_SUPPORT_MILLENNIUM
 339
 340 /*-----------------------------------------------------------------------
 341  *
 342  *-----------------------------------------------------------------------
 343  *
 344  */
 345 /*#define       CFG_DER 0x2002000F*/
 346 #define CFG_DER 0
 347
 348 /*
 349  * Init Memory Controller:
 350  *
 351  * BR0/1 and OR0/1 (FLASH)
 352  */
 353
 354 #define FLASH_BASE0_PRELIM      0xFFF00000      /* FLASH bank #0        */
 355 #define FLASH_BASE1_PRELIM      0x04000000      /* D.O.C Millenium      */
 356
 357 /* used to re-map FLASH both when starting from SRAM or FLASH:
 358  * restrict access enough to keep SRAM working (if any)
 359  * but not too much to meddle with FLASH accesses
 360  */
 361 #define CFG_PRELIM_OR_AM        0xFFF80000      /* OR addr mask */
 362
 363 /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 7, EHTR = 1        */
 364 #define CFG_OR_TIMING_FLASH  (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR)
 365
 366 #define CFG_OR_TIMING_MSYS   (OR_ACS_DIV1 | OR_BI)
 367
 368 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 369 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
 370
 371 #define CFG_OR1_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_MSYS)
 372 #define CFG_BR1_PRELIM  ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | \
 373                           BR_PS_8 | BR_V)
 374
 375 /*
 376  * BR4 and OR4 (SDRAM)
 377  *
 378  */
 379 #define SDRAM_BASE4_PRELIM      0x00000000      /* SDRAM bank #0        */
 380 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 381
 382 /*
 383  * SDRAM timing:
 384  */
 385 #define CFG_OR_TIMING_SDRAM     (OR_CSNT_SAM)
 386
 387 #define CFG_OR4_PRELIM  (~(SDRAM_MAX_SIZE-1) | CFG_OR_TIMING_SDRAM )
 388 #define CFG_BR4_PRELIM  ((SDRAM_BASE4_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 389
 390 /*
 391  * Memory Periodic Timer Prescaler
 392  */
 393
 394 /* periodic timer for refresh */
 395 #define CFG_MAMR_PTA    187             /* start with divider for 48 MHz        */
 396
 397 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
 398 #define CFG_MPTPR_2BK_4K        MPTPR_PTP_DIV16         /* setting for 2 banks  */
 399 #define CFG_MPTPR_1BK_4K        MPTPR_PTP_DIV32         /* setting for 1 bank   */
 400
 401 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 402 #define CFG_MPTPR_2BK_8K        MPTPR_PTP_DIV8          /* setting for 2 banks  */
 403 #define CFG_MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
 404
 405 /*
 406  * MAMR settings for SDRAM
 407  */
 408
 409 /* 8 column SDRAM */
 410 #define CFG_MAMR_8COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 411                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 412                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 413 /* 9 column SDRAM */
 414 #define CFG_MAMR_9COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 415                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 416                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 417
 418
 419 /*
 420  * Internal Definitions
 421  *
 422  * Boot Flags
 423  */
 424 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 425 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 426
 427 /*
 428  * JFFS2 partitions
 429  *
 430  */
 431 /* No command line, one static partition, whole device */
 432 #undef CONFIG_JFFS2_CMDLINE
 433 #define CONFIG_JFFS2_DEV                "nor0"
 434 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 435 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 436
 437 /* mtdparts command line support */
 438 /* Note: fake mtd_id used, no linux mtd map file */
 439 /*
 440 #define CONFIG_JFFS2_CMDLINE
 441 #define MTDIDS_DEFAULT          ""
 442 #define MTDPARTS_DEFAULT        ""
 443 */
 444
 445 #endif  /* __CONFIG_H */