include/configs/PPChameleonEVB.h

   1 /*
   2  * (C) Copyright 2003-2005
   3  * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
   4  *
   5  * (C) Copyright 2003
   6  * DAVE Srl
   7  *
   8  * http://www.dave-tech.it
   9  * http://www.wawnet.biz
  10  * mailto:info@wawnet.biz
  11  *
  12  * Credits: Stefan Roese, Wolfgang Denk
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 /*
  31  * board/config.h - configuration options, board specific
  32  */
  33
  34 #ifndef __CONFIG_H
  35 #define __CONFIG_H
  36
  37 #define CONFIG_PPCHAMELEON_MODULE_BA    0       /* Basic    Model */
  38 #define CONFIG_PPCHAMELEON_MODULE_ME    1       /* Medium   Model */
  39 #define CONFIG_PPCHAMELEON_MODULE_HI    2       /* High-End Model */
  40 #ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
  41 #define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
  42 #endif
  43
  44
  45 /* Only one of the following two symbols must be defined (default is 25 MHz)
  46  * CONFIG_PPCHAMELEON_CLK_25
  47  * CONFIG_PPCHAMELEON_CLK_33
  48  */
  49 #if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
  50 #define CONFIG_PPCHAMELEON_CLK_25
  51 #endif
  52
  53 #if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
  54 #error "* Two external frequencies (SysClk) are defined! *"
  55 #endif
  56
  57 #undef  CONFIG_PPCHAMELEON_SMI712
  58
  59 /*
  60  * Debug stuff
  61  */
  62 #undef  __DEBUG_START_FROM_SRAM__
  63 #define __DISABLE_MACHINE_EXCEPTION__
  64
  65 #ifdef __DEBUG_START_FROM_SRAM__
  66 #define CFG_DUMMY_FLASH_SIZE            1024*1024*4
  67 #endif
  68
  69 /*
  70  * High Level Configuration Options
  71  * (easy to change)
  72  */
  73
  74 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  75 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  76 #define CONFIG_PPCHAMELEONEVB   1       /* ...on a PPChameleonEVB board */
  77
  78 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  79 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  80
  81
  82 #ifdef CONFIG_PPCHAMELEON_CLK_25
  83 # define CONFIG_SYS_CLK_FREQ    25000000 /* external frequency to pll   */
  84 #elif (defined (CONFIG_PPCHAMELEON_CLK_33))
  85 # define CONFIG_SYS_CLK_FREQ    33333333 /* external frequency to pll   */
  86 #else
  87 # error "* External frequency (SysClk) not defined! *"
  88 #endif
  89
  90 #define CONFIG_BAUDRATE         115200
  91 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  92
  93 #undef  CONFIG_BOOTARGS
  94
  95 /* Ethernet stuff */
  96 #define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
  97 #define CONFIG_ETHADDR  00:50:c2:1e:af:fe
  98 #define CONFIG_HAS_ETH1
  99 #define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd
 100
 101 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 102 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 103
 104 #undef CONFIG_EXT_PHY
 105 #define CONFIG_NET_MULTI        1
 106
 107 #define CONFIG_MII              1       /* MII PHY management           */
 108 #ifndef  CONFIG_EXT_PHY
 109 #define CONFIG_PHY_ADDR         1       /* EMAC0 PHY address            */
 110 #define CONFIG_PHY1_ADDR        2       /* EMAC1 PHY address            */
 111 #else
 112 #define CONFIG_PHY_ADDR         2       /* PHY address                  */
 113 #endif
 114 #define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ
 115
 116
 117 /*
 118  * BOOTP options
 119  */
 120 #define CONFIG_BOOTP_BOOTFILESIZE
 121 #define CONFIG_BOOTP_BOOTPATH
 122 #define CONFIG_BOOTP_GATEWAY
 123 #define CONFIG_BOOTP_HOSTNAME
 124
 125
 126 /*
 127  * Command line configuration.
 128  */
 129 #include <config_cmd_default.h>
 130
 131 #define CONFIG_CMD_DATE
 132 #define CONFIG_CMD_DHCP
 133 #define CONFIG_CMD_ELF
 134 #define CONFIG_CMD_EEPROM
 135 #define CONFIG_CMD_I2C
 136 #define CONFIG_CMD_IRQ
 137 #define CONFIG_CMD_JFFS2
 138 #define CONFIG_CMD_MII
 139 #define CONFIG_CMD_NAND
 140 #define CONFIG_CMD_NFS
 141 #define CONFIG_CMD_PCI
 142 #define CONFIG_CMD_SNTP
 143
 144
 145 #define CONFIG_MAC_PARTITION
 146 #define CONFIG_DOS_PARTITION
 147
 148 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 149
 150 #define CONFIG_RTC_M41T11       1       /* uses a M41T00 RTC            */
 151 #define CFG_I2C_RTC_ADDR        0x68
 152 #define CFG_M41T11_BASE_YEAR    1900
 153
 154 /*
 155  * SDRAM configuration (please see cpu/ppc/sdram.[ch])
 156  */
 157 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
 158
 159 /* SDRAM timings used in datasheet */
 160 #define CFG_SDRAM_CL            2
 161 #define CFG_SDRAM_tRP           20
 162 #define CFG_SDRAM_tRC           65
 163 #define CFG_SDRAM_tRCD          20
 164 #undef  CFG_SDRAM_tRFC
 165
 166 /*
 167  * Miscellaneous configurable options
 168  */
 169 #define CFG_LONGHELP                    /* undef to save memory         */
 170 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 171
 172 #undef  CFG_HUSH_PARSER                 /* use "hush" command parser    */
 173 #ifdef  CFG_HUSH_PARSER
 174 #define CFG_PROMPT_HUSH_PS2     "> "
 175 #endif
 176
 177 #if defined(CONFIG_CMD_KGDB)
 178 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 179 #else
 180 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 181 #endif
 182 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 183 #define CFG_MAXARGS     16              /* max number of command args   */
 184 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 185
 186 #define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
 187
 188 #define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
 189
 190 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 191 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 192
 193 #undef  CFG_EXT_SERIAL_CLOCK            /* no external serial clock used */
 194 #define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
 195 #define CFG_BASE_BAUD           691200
 196
 197 /* The following table includes the supported baudrates */
 198 #define CFG_BAUDRATE_TABLE      \
 199         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 200          57600, 115200, 230400, 460800, 921600 }
 201
 202 #define CFG_LOAD_ADDR   0x100000        /* default load address */
 203 #define CFG_EXTBDINFO   1               /* To use extended board_into (bd_t) */
 204
 205 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 206
 207 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 208
 209 /*-----------------------------------------------------------------------
 210  * NAND-FLASH stuff
 211  *-----------------------------------------------------------------------
 212  */
 213 /*
 214  * nand device 1 on dave (PPChameleonEVB) needs more time,
 215  * so we just introduce additional wait in nand_wait(),
 216  * effectively for both devices.
 217  */
 218 #define PPCHAMELON_NAND_TIMER_HACK
 219
 220 #define CFG_NAND0_BASE 0xFF400000
 221 #define CFG_NAND1_BASE 0xFF000000
 222 #define CFG_NAND_BASE_LIST      { CFG_NAND0_BASE, CFG_NAND1_BASE }
 223 #define NAND_BIG_DELAY_US       25
 224 #define CFG_MAX_NAND_DEVICE     2       /* Max number of NAND devices */
 225
 226 #define NAND_MAX_CHIPS 1
 227
 228 #define CFG_NAND0_CE  (0x80000000 >> 1)  /* our CE is GPIO1 */
 229 #define CFG_NAND0_RDY (0x80000000 >> 4)  /* our RDY is GPIO4 */
 230 #define CFG_NAND0_CLE (0x80000000 >> 2)  /* our CLE is GPIO2 */
 231 #define CFG_NAND0_ALE (0x80000000 >> 3)  /* our ALE is GPIO3 */
 232
 233 #define CFG_NAND1_CE  (0x80000000 >> 14)  /* our CE is GPIO14 */
 234 #define CFG_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
 235 #define CFG_NAND1_CLE (0x80000000 >> 15)  /* our CLE is GPIO15 */
 236 #define CFG_NAND1_ALE (0x80000000 >> 16)  /* our ALE is GPIO16 */
 237
 238 #define MACRO_NAND_DISABLE_CE(nandptr) do \
 239 { \
 240         switch((unsigned long)nandptr) \
 241         { \
 242             case CFG_NAND0_BASE: \
 243                 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
 244                 break; \
 245             case CFG_NAND1_BASE: \
 246                 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
 247                 break; \
 248         } \
 249 } while(0)
 250
 251 #define MACRO_NAND_ENABLE_CE(nandptr) do \
 252 { \
 253         switch((unsigned long)nandptr) \
 254         { \
 255             case CFG_NAND0_BASE: \
 256                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
 257                 break; \
 258             case CFG_NAND1_BASE: \
 259                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
 260                 break; \
 261         } \
 262 } while(0)
 263
 264 #define MACRO_NAND_CTL_CLRALE(nandptr) do \
 265 { \
 266         switch((unsigned long)nandptr) \
 267         { \
 268             case CFG_NAND0_BASE: \
 269                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
 270                 break; \
 271             case CFG_NAND1_BASE: \
 272                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
 273                 break; \
 274         } \
 275 } while(0)
 276
 277 #define MACRO_NAND_CTL_SETALE(nandptr) do \
 278 { \
 279         switch((unsigned long)nandptr) \
 280         { \
 281             case CFG_NAND0_BASE: \
 282                 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
 283                 break; \
 284             case CFG_NAND1_BASE: \
 285                 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
 286                 break; \
 287         } \
 288 } while(0)
 289
 290 #define MACRO_NAND_CTL_CLRCLE(nandptr) do \
 291 { \
 292         switch((unsigned long)nandptr) \
 293         { \
 294             case CFG_NAND0_BASE: \
 295                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
 296                 break; \
 297             case CFG_NAND1_BASE: \
 298                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
 299                 break; \
 300         } \
 301 } while(0)
 302
 303 #define MACRO_NAND_CTL_SETCLE(nandptr) do { \
 304         switch((unsigned long)nandptr) { \
 305         case CFG_NAND0_BASE: \
 306                 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
 307                 break; \
 308         case CFG_NAND1_BASE: \
 309                 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
 310                 break; \
 311         } \
 312 } while(0)
 313
 314 #if 0
 315 #define SECTORSIZE 512
 316 #define NAND_NO_RB
 317
 318 #define ADDR_COLUMN 1
 319 #define ADDR_PAGE 2
 320 #define ADDR_COLUMN_PAGE 3
 321
 322 #define NAND_ChipID_UNKNOWN     0x00
 323 #define NAND_MAX_FLOORS 1
 324
 325 #ifdef NAND_NO_RB
 326 /* constant delay (see also tR in the datasheet) */
 327 #define NAND_WAIT_READY(nand) do { \
 328         udelay(12); \
 329 } while (0)
 330 #else
 331 /* use the R/B pin */
 332 /* TBD */
 333 #endif
 334
 335 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
 336 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
 337 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
 338 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
 339 #endif
 340 /*-----------------------------------------------------------------------
 341  * PCI stuff
 342  *-----------------------------------------------------------------------
 343  */
 344 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 345 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 346 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 347
 348 #define CONFIG_PCI                      /* include pci support          */
 349 #define CONFIG_PCI_HOST PCI_HOST_FORCE   /* select pci host function     */
 350 #undef  CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 351                                         /* resource configuration       */
 352
 353 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 354
 355 #define CFG_PCI_SUBSYS_VENDORID 0x1014  /* PCI Vendor ID: IBM   */
 356 #define CFG_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: ---   */
 357 #define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 358
 359 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
 360 #define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
 361 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 362 #define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
 363 #define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 364 #define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 365
 366 /*-----------------------------------------------------------------------
 367  * Start addresses for the final memory configuration
 368  * (Set up by the startup code)
 369  * Please note that CFG_SDRAM_BASE _must_ start at 0
 370  */
 371 #define CFG_SDRAM_BASE          0x00000000
 372
 373 /* Reserve 256 kB for Monitor   */
 374 /*
 375 #define CFG_FLASH_BASE          0xFFFC0000
 376 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 377 #define CFG_MONITOR_LEN         (256 * 1024)
 378 */
 379
 380 /* Reserve 320 kB for Monitor   */
 381 #define CFG_FLASH_BASE          0xFFFB0000
 382 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 383 #define CFG_MONITOR_LEN         (320 * 1024)
 384
 385 #define CFG_MALLOC_LEN          (256 * 1024)    /* Reserve 256 kB for malloc()  */
 386
 387 /*
 388  * For booting Linux, the board info and command line data
 389  * have to be in the first 8 MB of memory, since this is
 390  * the maximum mapped by the Linux kernel during initialization.
 391  */
 392 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 393 /*-----------------------------------------------------------------------
 394  * FLASH organization
 395  */
 396 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 397 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 398
 399 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 400 #define CFG_FLASH_WRITE_TOUT    1000    /* Timeout for Flash Write (in ms)      */
 401
 402 #define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
 403 #define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
 404 #define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
 405 /*
 406  * The following defines are added for buggy IOP480 byte interface.
 407  * All other boards should use the standard values (CPCI405 etc.)
 408  */
 409 #define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
 410 #define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
 411 #define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
 412
 413 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 414
 415 /*-----------------------------------------------------------------------
 416  * Environment Variable setup
 417  */
 418 #ifdef ENVIRONMENT_IN_EEPROM
 419
 420 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 421 #define CFG_ENV_OFFSET          0x100   /* environment starts at the beginning of the EEPROM */
 422 #define CFG_ENV_SIZE            0x700   /* 2048-256 bytes may be used for env vars (total size of a CAT24WC16 is 2048 bytes)*/
 423
 424 #else   /* DEFAULT: environment in flash, using redundand flash sectors */
 425
 426 #define CFG_ENV_IS_IN_FLASH     1       /* use FLASH for environment vars */
 427 #define CFG_ENV_ADDR            0xFFFF8000      /* environment starts at the first small sector */
 428 #define CFG_ENV_SECT_SIZE       0x2000  /* 8196 bytes may be used for env vars*/
 429 #define CFG_ENV_ADDR_REDUND     0xFFFFA000
 430 #define CFG_ENV_SIZE_REDUND     0x2000
 431
 432 #define CFG_USE_PPCENV                  /* Environment embedded in sect .ppcenv */
 433
 434 #endif  /* ENVIRONMENT_IN_EEPROM */
 435
 436
 437 #define CFG_NVRAM_BASE_ADDR     0xF0000500              /* NVRAM base address   */
 438 #define CFG_NVRAM_SIZE          242                     /* NVRAM size           */
 439
 440 /*-----------------------------------------------------------------------
 441  * I2C EEPROM (CAT24WC16) for environment
 442  */
 443 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 444 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 445 #define CFG_I2C_SLAVE           0x7F
 446
 447 #define CFG_I2C_EEPROM_ADDR     0x50    /* EEPROM CAT28WC08             */
 448 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address             */
 449 /* mask of address bits that overflow into the "EEPROM chip address"    */
 450 /*#define CFG_I2C_EEPROM_ADDR_OVERFLOW  0x07*/
 451 #define CFG_EEPROM_PAGE_WRITE_BITS 4    /* The Catalyst CAT24WC08 has   */
 452                                         /* 16 byte page write mode using*/
 453                                         /* last 4 bits of the address   */
 454 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10   /* and takes up to 10 msec */
 455 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 456
 457 /*
 458  * Init Memory Controller:
 459  *
 460  * BR0/1 and OR0/1 (FLASH)
 461  */
 462
 463 #define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 464
 465 /*-----------------------------------------------------------------------
 466  * External Bus Controller (EBC) Setup
 467  */
 468
 469 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 470 #define CFG_EBC_PB0AP           0x92015480
 471 #define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 472
 473 /* Memory Bank 1 (External SRAM) initialization                                 */
 474 /* Since this must replace NOR Flash, we use the same settings for CS0          */
 475 #define CFG_EBC_PB1AP           0x92015480
 476 #define CFG_EBC_PB1CR           0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
 477
 478 /* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization                      */
 479 #define CFG_EBC_PB2AP           0x92015480
 480 #define CFG_EBC_PB2CR           0xFF458000  /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit  */
 481
 482 /* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization                      */
 483 #define CFG_EBC_PB3AP           0x92015480
 484 #define CFG_EBC_PB3CR           0xFF058000  /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit  */
 485
 486 #ifdef CONFIG_PPCHAMELEON_SMI712
 487 /*
 488  * Video console (graphic: SMI LynxEM)
 489  */
 490 #define CONFIG_VIDEO
 491 #define CONFIG_CFB_CONSOLE
 492 #define CONFIG_VIDEO_SMI_LYNXEM
 493 #define CONFIG_VIDEO_LOGO
 494 /*#define CONFIG_VIDEO_BMP_LOGO*/
 495 #define CONFIG_CONSOLE_EXTRA_INFO
 496 #define CONFIG_VGA_AS_SINGLE_DEVICE
 497 /* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
 498 #define CFG_ISA_IO 0xE8000000
 499 /* see also drivers/video/videomodes.c */
 500 #define CFG_DEFAULT_VIDEO_MODE 0x303
 501 #endif
 502
 503 /*-----------------------------------------------------------------------
 504  * FPGA stuff
 505  */
 506 /* FPGA internal regs */
 507 #define CFG_FPGA_MODE           0x00
 508 #define CFG_FPGA_STATUS         0x02
 509 #define CFG_FPGA_TS             0x04
 510 #define CFG_FPGA_TS_LOW         0x06
 511 #define CFG_FPGA_TS_CAP0        0x10
 512 #define CFG_FPGA_TS_CAP0_LOW    0x12
 513 #define CFG_FPGA_TS_CAP1        0x14
 514 #define CFG_FPGA_TS_CAP1_LOW    0x16
 515 #define CFG_FPGA_TS_CAP2        0x18
 516 #define CFG_FPGA_TS_CAP2_LOW    0x1a
 517 #define CFG_FPGA_TS_CAP3        0x1c
 518 #define CFG_FPGA_TS_CAP3_LOW    0x1e
 519
 520 /* FPGA Mode Reg */
 521 #define CFG_FPGA_MODE_CF_RESET  0x0001
 522 #define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
 523 #define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
 524 #define CFG_FPGA_MODE_TS_CLEAR  0x2000
 525
 526 /* FPGA Status Reg */
 527 #define CFG_FPGA_STATUS_DIP0    0x0001
 528 #define CFG_FPGA_STATUS_DIP1    0x0002
 529 #define CFG_FPGA_STATUS_DIP2    0x0004
 530 #define CFG_FPGA_STATUS_FLASH   0x0008
 531 #define CFG_FPGA_STATUS_TS_IRQ  0x1000
 532
 533 #define CFG_FPGA_SPARTAN2       1               /* using Xilinx Spartan 2 now    */
 534 #define CFG_FPGA_MAX_SIZE       128*1024        /* 128kByte is enough for XC2S50E*/
 535
 536 /* FPGA program pin configuration */
 537 #define CFG_FPGA_PRG            0x04000000      /* FPGA program pin (ppc output) */
 538 #define CFG_FPGA_CLK            0x02000000      /* FPGA clk pin (ppc output)     */
 539 #define CFG_FPGA_DATA           0x01000000      /* FPGA data pin (ppc output)    */
 540 #define CFG_FPGA_INIT           0x00010000      /* FPGA init pin (ppc input)     */
 541 #define CFG_FPGA_DONE           0x00008000      /* FPGA done pin (ppc input)     */
 542
 543 /*-----------------------------------------------------------------------
 544  * Definitions for initial stack pointer and data area (in data cache)
 545  */
 546 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 547 #define CFG_TEMP_STACK_OCM      1
 548
 549 /* On Chip Memory location */
 550 #define CFG_OCM_DATA_ADDR       0xF8000000
 551 #define CFG_OCM_DATA_SIZE       0x1000
 552 #define CFG_INIT_RAM_ADDR       CFG_OCM_DATA_ADDR /* inside of SDRAM            */
 553 #define CFG_INIT_RAM_END        CFG_OCM_DATA_SIZE /* End of used area in RAM    */
 554
 555 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 556 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 557 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 558
 559 /*-----------------------------------------------------------------------
 560  * Definitions for GPIO setup (PPC405EP specific)
 561  *
 562  * GPIO0[0]     - External Bus Controller BLAST output
 563  * GPIO0[1-9]   - Instruction trace outputs -> GPIO
 564  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 565  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 566  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 567  * GPIO0[24-27] - UART0 control signal inputs/outputs
 568  * GPIO0[28-29] - UART1 data signal input/output
 569  * GPIO0[30]    - EMAC0 input
 570  * GPIO0[31]    - EMAC1 reject packet as output
 571  */
 572 #define CFG_GPIO0_OSRH          0x40000550
 573 #define CFG_GPIO0_OSRL          0x00000110
 574 #define CFG_GPIO0_ISR1H         0x00000000
 575 /*#define CFG_GPIO0_ISR1L       0x15555445*/
 576 #define CFG_GPIO0_ISR1L         0x15555444
 577 #define CFG_GPIO0_TSRH          0x00000000
 578 #define CFG_GPIO0_TSRL          0x00000000
 579 #define CFG_GPIO0_TCR           0xF7FF8014
 580
 581 /*
 582  * Internal Definitions
 583  *
 584  * Boot Flags
 585  */
 586 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 587 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 588
 589
 590 #define CONFIG_NO_SERIAL_EEPROM
 591
 592 /*--------------------------------------------------------------------*/
 593
 594 #ifdef CONFIG_NO_SERIAL_EEPROM
 595
 596 /*
 597 !-----------------------------------------------------------------------
 598 ! Defines for entry options.
 599 ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
 600 !       are plugged in the board will be utilized as non-ECC DIMMs.
 601 !-----------------------------------------------------------------------
 602 */
 603 #undef          AUTO_MEMORY_CONFIG
 604 #define         DIMM_READ_ADDR 0xAB
 605 #define         DIMM_WRITE_ADDR 0xAA
 606
 607 #define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register               */
 608 #define CPC0_BOOT    (CNTRL_DCR_BASE+0x1)  /* Chip Clock Status register        */
 609 #define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register           */
 610 #define CPC0_EPRCSR  (CNTRL_DCR_BASE+0x3)  /* EMAC PHY Rcv Clk Src register     */
 611 #define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register               */
 612 #define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register             */
 613 #define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register               */
 614 #define CPC0_JTAGID  (CNTRL_DCR_BASE+0x7)  /* JTAG ID register                  */
 615 #define CPC0_SPARE   (CNTRL_DCR_BASE+0x8)  /* Spare DCR                         */
 616 #define CPC0_PCI     (CNTRL_DCR_BASE+0x9)  /* PCI Control register              */
 617
 618 /* Defines for CPC0_PLLMR1 Register fields */
 619 #define PLL_ACTIVE              0x80000000
 620 #define CPC0_PLLMR1_SSCS        0x80000000
 621 #define PLL_RESET               0x40000000
 622 #define CPC0_PLLMR1_PLLR        0x40000000
 623     /* Feedback multiplier */
 624 #define PLL_FBKDIV              0x00F00000
 625 #define CPC0_PLLMR1_FBDV        0x00F00000
 626 #define PLL_FBKDIV_16           0x00000000
 627 #define PLL_FBKDIV_1            0x00100000
 628 #define PLL_FBKDIV_2            0x00200000
 629 #define PLL_FBKDIV_3            0x00300000
 630 #define PLL_FBKDIV_4            0x00400000
 631 #define PLL_FBKDIV_5            0x00500000
 632 #define PLL_FBKDIV_6            0x00600000
 633 #define PLL_FBKDIV_7            0x00700000
 634 #define PLL_FBKDIV_8            0x00800000
 635 #define PLL_FBKDIV_9            0x00900000
 636 #define PLL_FBKDIV_10           0x00A00000
 637 #define PLL_FBKDIV_11           0x00B00000
 638 #define PLL_FBKDIV_12           0x00C00000
 639 #define PLL_FBKDIV_13           0x00D00000
 640 #define PLL_FBKDIV_14           0x00E00000
 641 #define PLL_FBKDIV_15           0x00F00000
 642     /* Forward A divisor */
 643 #define PLL_FWDDIVA             0x00070000
 644 #define CPC0_PLLMR1_FWDVA       0x00070000
 645 #define PLL_FWDDIVA_8           0x00000000
 646 #define PLL_FWDDIVA_7           0x00010000
 647 #define PLL_FWDDIVA_6           0x00020000
 648 #define PLL_FWDDIVA_5           0x00030000
 649 #define PLL_FWDDIVA_4           0x00040000
 650 #define PLL_FWDDIVA_3           0x00050000
 651 #define PLL_FWDDIVA_2           0x00060000
 652 #define PLL_FWDDIVA_1           0x00070000
 653     /* Forward B divisor */
 654 #define PLL_FWDDIVB             0x00007000
 655 #define CPC0_PLLMR1_FWDVB       0x00007000
 656 #define PLL_FWDDIVB_8           0x00000000
 657 #define PLL_FWDDIVB_7           0x00001000
 658 #define PLL_FWDDIVB_6           0x00002000
 659 #define PLL_FWDDIVB_5           0x00003000
 660 #define PLL_FWDDIVB_4           0x00004000
 661 #define PLL_FWDDIVB_3           0x00005000
 662 #define PLL_FWDDIVB_2           0x00006000
 663 #define PLL_FWDDIVB_1           0x00007000
 664     /* PLL tune bits */
 665 #define PLL_TUNE_MASK           0x000003FF
 666 #define PLL_TUNE_2_M_3          0x00000133      /*  2 <= M <= 3                 */
 667 #define PLL_TUNE_4_M_6          0x00000134      /*  3 <  M <= 6                 */
 668 #define PLL_TUNE_7_M_10         0x00000138      /*  6 <  M <= 10                */
 669 #define PLL_TUNE_11_M_14        0x0000013C      /* 10 <  M <= 14                */
 670 #define PLL_TUNE_15_M_40        0x0000023E      /* 14 <  M <= 40                */
 671 #define PLL_TUNE_VCO_LOW        0x00000000      /* 500MHz <= VCO <=  800MHz     */
 672 #define PLL_TUNE_VCO_HI         0x00000080      /* 800MHz <  VCO <= 1000MHz     */
 673
 674 /* Defines for CPC0_PLLMR0 Register fields */
 675     /* CPU divisor */
 676 #define PLL_CPUDIV              0x00300000
 677 #define CPC0_PLLMR0_CCDV        0x00300000
 678 #define PLL_CPUDIV_1            0x00000000
 679 #define PLL_CPUDIV_2            0x00100000
 680 #define PLL_CPUDIV_3            0x00200000
 681 #define PLL_CPUDIV_4            0x00300000
 682     /* PLB divisor */
 683 #define PLL_PLBDIV              0x00030000
 684 #define CPC0_PLLMR0_CBDV        0x00030000
 685 #define PLL_PLBDIV_1            0x00000000
 686 #define PLL_PLBDIV_2            0x00010000
 687 #define PLL_PLBDIV_3            0x00020000
 688 #define PLL_PLBDIV_4            0x00030000
 689     /* OPB divisor */
 690 #define PLL_OPBDIV              0x00003000
 691 #define CPC0_PLLMR0_OPDV        0x00003000
 692 #define PLL_OPBDIV_1            0x00000000
 693 #define PLL_OPBDIV_2            0x00001000
 694 #define PLL_OPBDIV_3            0x00002000
 695 #define PLL_OPBDIV_4            0x00003000
 696     /* EBC divisor */
 697 #define PLL_EXTBUSDIV           0x00000300
 698 #define CPC0_PLLMR0_EPDV        0x00000300
 699 #define PLL_EXTBUSDIV_2         0x00000000
 700 #define PLL_EXTBUSDIV_3         0x00000100
 701 #define PLL_EXTBUSDIV_4         0x00000200
 702 #define PLL_EXTBUSDIV_5         0x00000300
 703     /* MAL divisor */
 704 #define PLL_MALDIV              0x00000030
 705 #define CPC0_PLLMR0_MPDV        0x00000030
 706 #define PLL_MALDIV_1            0x00000000
 707 #define PLL_MALDIV_2            0x00000010
 708 #define PLL_MALDIV_3            0x00000020
 709 #define PLL_MALDIV_4            0x00000030
 710     /* PCI divisor */
 711 #define PLL_PCIDIV              0x00000003
 712 #define CPC0_PLLMR0_PPFD        0x00000003
 713 #define PLL_PCIDIV_1            0x00000000
 714 #define PLL_PCIDIV_2            0x00000001
 715 #define PLL_PCIDIV_3            0x00000002
 716 #define PLL_PCIDIV_4            0x00000003
 717
 718 #ifdef CONFIG_PPCHAMELEON_CLK_25
 719 /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
 720 #define PPCHAMELEON_PLLMR0_133_133_33_66_33      (PLL_CPUDIV_1 | PLL_PLBDIV_1 |  \
 721                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
 722                               PLL_MALDIV_1 | PLL_PCIDIV_4)
 723 #define PPCHAMELEON_PLLMR1_133_133_33_66_33      (PLL_FBKDIV_8  |  \
 724                               PLL_FWDDIVA_6 | PLL_FWDDIVB_4 |  \
 725                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 726
 727 #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
 728                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |  \
 729                               PLL_MALDIV_1 | PLL_PCIDIV_4)
 730 #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8  |  \
 731                               PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
 732                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 733
 734 #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |      \
 735                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
 736                               PLL_MALDIV_1 | PLL_PCIDIV_4)
 737 #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
 738                               PLL_FWDDIVA_3 | PLL_FWDDIVB_4 |  \
 739                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 740
 741 #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |      \
 742                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |  \
 743                               PLL_MALDIV_1 | PLL_PCIDIV_2)
 744 #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10      |  \
 745                               PLL_FWDDIVA_3 | PLL_FWDDIVB_4 |  \
 746                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
 747
 748 #elif (defined (CONFIG_PPCHAMELEON_CLK_33))
 749
 750 /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
 751 #define PPCHAMELEON_PLLMR0_133_133_33_66_33      (PLL_CPUDIV_1 | PLL_PLBDIV_1 |  \
 752                                   PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |      \
 753                                   PLL_MALDIV_1 | PLL_PCIDIV_4)
 754 #define PPCHAMELEON_PLLMR1_133_133_33_66_33      (PLL_FBKDIV_4  |  \
 755                                   PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
 756                                   PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 757
 758 #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
 759                                   PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |      \
 760                                   PLL_MALDIV_1 | PLL_PCIDIV_4)
 761 #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6  |  \
 762                                   PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
 763                                   PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 764
 765 #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |      \
 766                                   PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |      \
 767                                   PLL_MALDIV_1 | PLL_PCIDIV_4)
 768 #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
 769                                   PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
 770                                   PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 771
 772 #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |      \
 773                                   PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |      \
 774                                   PLL_MALDIV_1 | PLL_PCIDIV_2)
 775 #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10      |  \
 776                                   PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
 777                                   PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
 778
 779 #else
 780 #error "* External frequency (SysClk) not defined! *"
 781 #endif
 782
 783 #if   (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
 784 /* Model HI */
 785 #define PLLMR0_DEFAULT  PPCHAMELEON_PLLMR0_333_111_37_55_55
 786 #define PLLMR1_DEFAULT  PPCHAMELEON_PLLMR1_333_111_37_55_55
 787 #define CFG_OPB_FREQ    55555555
 788 /* Model ME */
 789 #elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
 790 #define PLLMR0_DEFAULT  PPCHAMELEON_PLLMR0_266_133_33_66_33
 791 #define PLLMR1_DEFAULT  PPCHAMELEON_PLLMR1_266_133_33_66_33
 792 #define CFG_OPB_FREQ    66666666
 793 #else
 794 /* Model BA (default) */
 795 #define PLLMR0_DEFAULT  PPCHAMELEON_PLLMR0_133_133_33_66_33
 796 #define PLLMR1_DEFAULT  PPCHAMELEON_PLLMR1_133_133_33_66_33
 797 #define CFG_OPB_FREQ    66666666
 798 #endif
 799
 800 #endif /* CONFIG_NO_SERIAL_EEPROM */
 801
 802 #define CONFIG_JFFS2_NAND 1                     /* jffs2 on nand support */
 803 #define NAND_CACHE_PAGES 16                     /* size of nand cache in 512 bytes pages */
 804
 805 /*
 806  * JFFS2 partitions
 807  */
 808
 809 /* No command line, one static partition */
 810 #undef CONFIG_JFFS2_CMDLINE
 811 #define CONFIG_JFFS2_DEV                "nand0"
 812 #define CONFIG_JFFS2_PART_SIZE          0x00400000
 813 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 814
 815 /* mtdparts command line support */
 816 /*
 817 #define CONFIG_JFFS2_CMDLINE
 818 #define MTDIDS_DEFAULT          "nor0=PPChameleon-0,nand0=ppchameleonevb-nand"
 819 */
 820
 821 /* 256 kB U-boot image */
 822 /*
 823 #define MTDPARTS_DEFAULT        "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
 824                                         "1792k(user),256k(u-boot);" \
 825                                 "ppchameleonevb-nand:-(nand)"
 826 */
 827
 828 /* 320 kB U-boot image */
 829 /*
 830 #define MTDPARTS_DEFAULT        "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
 831                                         "1728k(user),320k(u-boot);" \
 832                                 "ppchameleonevb-nand:-(nand)"
 833 */
 834
 835 #endif  /* __CONFIG_H */